JPH02309673A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable a chip to be rationally constituted meeting the requirements of the circuits by a method wherein transistors in multiple gate widths are formed in the same conductivity type transistor regions. CONSTITUTION:Two each of long gate width transistors and four each of short gate width transistors are formed of long gate width polysilicon gate electrodes 3, short gate width polysilicon gate electrodes 4 and 5 in a P channel MOS transistor region 1. Similar transistors are formed also in an N channel MOS transistor region 2. On the other hand, in such a transistor as a switching transistor for memory requiring of no performances at all, the circuits are constituted using short gate width transistors while the short gate width transistors are assembled together to be used for the transistors requiring of performances sililar to the long gate width transistors. Through these procedures, a chip can be rationally constituted meeting the requirements of the circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to a gate array type semiconductor integrated circuit, and particularly relates to a semiconductor integrated circuit with an improved basic cell structure.

・[Summary] The present invention provides a gate array type semiconductor integrated circuit in which a basic cell is composed of a plurality of field effect transistors having gate widths of different lengths, thereby achieving a rational chip configuration according to the circuit requirements. It was made possible to do this.

[Conventional technology]

Conventionally, a basic cell of a gate array using complementary MO3) transistors (CMO3) consists of two or three long gate width polysilicon electrodes 3 with equal gate widths, as shown in FIGS. 5(a) and 5(a). It was composed of a P-channel MO3) transistor region 1 and an N-channel MO3) transistor region 2.

[Problem that the invention seeks to solve]

The conventional CMOS gate array described above is shown in FIG. 5(a).
In this case, one NAND gate or N0R gate, or two inverter circuits, can be realized in one basic cell. However, when constructing a storage circuit for one bit of a static RAM as shown in FIG. 2, two cells are required.

By the way, the switch N-channel transistor 7 shown in Figure 2) is used as a switch gate for the memory loop when reading or writing memory data, and requires the same driving force as a normal logic gate. I haven't been. Further, the same can be said about the two transfer gates 8 used in the latch circuit shown in FIG. 3(b).

In other words, conventional gate array MOS) transistors are all designed with the same gate width, so SRAM
When configuring a large number of latches or latches, the number of cells and chip area will be occupied more than necessary, which has the disadvantage of reducing the utilization efficiency of basic cells.

It is an object of the present invention to provide a gate array type semiconductor integrated circuit which eliminates the above-mentioned drawbacks and allows a chip to be configured rationally in accordance with circuit requirements without occupying an unnecessarily large number of cells or chip area. Our goal is to provide the following.

[Means for solving problems]

The present invention provides a gate array type semiconductor integrated circuit having a plurality of basic cells arranged in an array, wherein the basic cells are composed of a plurality of field effect transistors having a plurality of different gate widths. Features.

Further, in the present invention, the field effect transistors constituting the basic cell are P-channel and N-channel field effect transistors, and can be configured by field effect transistors of the same conductivity type with a long gate width and a short gate width.

[Effect]

For example, the present invention includes, in a basic cell of a CMOS gate array, a P-channel transistor and an N-channel transistor with a long gate width, and a P-channel transistor and an N-channel transistor with a short gate width,
Circuits are constructed using transistors with short gate widths in places where performance is not required, such as memory switch transistors. In addition, transistors with short gate widths are combined and used in places where the same performance as transistors with long gate widths is required.

Therefore, by configuring a basic cell using transistors with different gate widths in accordance with the required circuit characteristics, it becomes possible to perform a rational chip configuration in accordance with the circuit requirements.

〔Example〕

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 is a layout showing a first embodiment of the present invention.
The basic cell of the OS gate array is shown.

The basic cell of the second embodiment includes a long gate width polysilicon gate electrode 3 in a P channel MOS transistor region 1,
The short gate width polysilicon gate electrodes 4 and 5 form two long gate width transistors and four short gate width transistors. The same applies to N-channel MO5) transistor region 2. A feature of the present invention is that, in FIG. 1, a MOS transistor with short gate width polysilicon electrodes 4 and 5 is provided.

FIG. 2(a) is a schematic layout diagram showing a second embodiment of the present invention, and FIG. 2(b) is a circuit diagram thereof, showing a 1-bit storage portion of an SRAM.

This second embodiment is based on the CMOS of the first embodiment shown in FIG.
The basic cell is applied to the 1-bit storage portion of the static RAM shown in FIG. 2, etc., in the following manner.

First, the two inverters 6 shown in FIG. 2(a) are constructed using two P-channel transistors having the long gate width polysilicon electrode 3 shown in FIG. 1, and two N-channel transistors. . In addition, the two N-channel transistors 7 for switches are constructed by setting the short gate width polysilicon gate electrode 5 in the N channel MOS transistor region 2 in FIG. 1 to the ground (GND) potential. A channel transistor is formed.

The actual wiring connection uses two-layer wiring of the first-layer wiring 9 and the second-layer wiring 10, and between the first wiring 9 and the underlying contact 11 and the first-layer wiring 9 and the second-layer wiring 10. This is done through the through hole 12 as shown in FIG. 2(a).

In FIG. 2(a), a short gate width transistor has a short gate width polysilicon gate electrode 5 connected to a ground potential (N
(in the case of a channel), so it is not affected by the logic level of a transistor with a long gate width.

FIG. 3(a) is a schematic layout diagram showing a third embodiment of the present invention, and FIGS. 3(a) and 3(a) are circuit diagrams thereof, showing the case of a latch circuit.

In the third embodiment, the CMO3 basic cell shown in FIG. 1 is applied to the latch circuit of FIG. 3, etc. in the following manner.

The third embodiment uses two P-channel transistors and two N-channel transistors each having short gate width polysilicon electrodes 4 and 5, as in the second embodiment shown in FIG. 2(a). Two transfer gates 8 shown in FIG. 3(a) are constructed. In this case, the short gate width polysilicon electrode 5 of the P channel MOS transistor region 1 is connected to VD
It is necessary to keep it at D potential.

FIG. 4(a) is a schematic layout diagram showing a fourth embodiment of the present invention, and FIG. 4(a) is a circuit diagram thereof.
An ND circuit is shown.

In the fourth embodiment, the CMO3 basic cell shown in FIG. 1 is applied to the three-man power NAND circuit shown in FIG. 4, etc.).

The fourth embodiment shows that the short gate width transistors shown in the first, second and third embodiments are not only used as switch gates in memory circuits and latch circuits. .

In other words, by combining transistors with short gate widths, it is possible to achieve the driving power of one transistor with long gate widths, and it has been shown that ordinary logic gates can be configured with one basic cell without waste. It is.

In the above description, the gate widths are set to two lengths, one long and one short, but the gate widths may be three or more if necessary.

Further, although a MOS transistor is used as a field effect transistor, the present invention can be similarly applied to a compound semiconductor field effect transistor.

〔Effect of the invention〕

As explained above, the present invention is capable of, for example, forming transistors with a plurality of gate widths in a transistor region of the same conductivity type in the basic cell structure of a CMOS gate array. Long gate widths are suitable for constructing logic gates, while short gate widths can be used for switch gates in storage circuits and latches. Further, since a combination of transistors with short gate widths can provide the same driving force as transistors with long gate widths, all transistors with short gate widths can be used in the circuit configuration.

As described above, according to the present invention, any circuit can be designed by effectively allocating basic cells by combining long, short, and both gate width transistors, and the effect is great.

[Brief explanation of the drawing]

FIG. 1 is a layout diagram showing a first embodiment of the present invention. FIG. 2(a) is a schematic layout diagram showing a second embodiment of the present invention. FIG. 2(b) is its circuit diagram. FIG. 3(a) is a schematic layout diagram showing a third embodiment of the present invention. Figure 3) is the circuit diagram. FIG. 4(a) is a schematic layout diagram showing a fourth embodiment of the present invention. ) in Figure 4 is its circuit diagram. FIGS. 5(a) and 5(b) are layout diagrams showing a conventional example. 1... P channel MOS transistor region, 2...
N-channel MO3) transistor region, 3... long gate width polysilicon gate electrode, 4.5... short gate width polysilicon gate electrode, 6... inverter, 7...
N-channel transistor, 8... Transfer gate, 9... First layer wiring, 10... Second layer wiring, 11.
...Contact, 12...Through hole.

Claims (1)

[Claims] 1. In a gate array type semiconductor integrated circuit comprising a plurality of basic cells arranged in an array, the basic cells are composed of a plurality of field effect transistors having a plurality of different gate widths. A semiconductor integrated circuit characterized by: 2. The field effect transistor constituting the basic cell is P
2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is comprised of channel and N-channel field effect transistors having the same conductivity type and having a long gate width and a short gate width.