JPH0230117B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device configured with a CMOS (complementary metal insulator semiconductor) circuit and including a static RAM (random access memory).

In CMOS integrated circuit devices including RAM,
If you want to be able to constantly supply power to RAM to protect the memory contents, independent of the power supply to RAM and the power supply to the logic circuit section,
A well area for forming the memory matrix section of the RAM and its peripheral circuits, and a well area for forming the input/output circuits and other logic circuit sections are configured independently, and the input/output circuits and other logic circuits are It has been considered to selectively supply power to the well region for the circuit section depending on the operating mode.

In this case, in order to prevent punch-through, etc., the well regions to which power is supplied independently must be spaced apart from each other by a predetermined distance or more, which has the disadvantage of increasing the chip area. Moreover, in the case of a static RAM, the number of elements constituting the input/output circuit and the logic gate circuit is relatively small, so the separately formed well region is used inefficiently, leading to a deterioration in the degree of integration.

An object of the present invention is to provide a semiconductor integrated circuit device that can improve the degree of integration.

According to the basic feature of the present invention, a well region for configuring a memory matrix section of RAM and a word line selection circuit, a bit line selection circuit and input/output circuit for RAM, and a well region for configuring a necessary logic gate circuit. The latter well region is separated from the well region, and power is selectively supplied to the latter well region depending on the operation mode.

Hereinafter, this invention will be explained in detail together with examples.

FIG. 1 is a circuit diagram showing an embodiment in which the present invention is applied to a static RAM.

Memory cells are p-channel MISFETQ ₁ , Q ₂
A well-known flip-flop circuit consisting of an n-channel MISFETQ ₃ and Q ₄ , and an n-channel transmission gate provided at its pair of input/output terminals.
Consists of MISFETQ ₅ and Q ₆ .

The gates of the transmission gates MISFETQ ₅ and Q ₆ are connected to the word line W. On the other hand, transmission gate
The input/output terminals of the memory cell via MISFETQ ₅ and Q ₆ are connected to a pair of bit lines B.

A memory matrix section is constructed by arranging a plurality of similar word lines (not shown) and a plurality of bit lines so as to be orthogonal to each other, and providing memory cells similar to those described above at each intersection.

In addition, the bit line B is provided with the following as a load means:
Although not particularly limited, resistance means R ₁ and R ₂ are provided. This load means can be replaced by MISFET or precharge means.

In addition, the p channel that constitutes the memory cell
MISFETQ ₁ and Q ₂ may be high resistance means made of polysilicon or the like.

p channel MISFETQ ₇ and n channel
The inverter circuit made up of MISFETQ ₈ constitutes the word line drive circuit WD, and together with the Y address decoder circuit YD provided in the previous stage,
Configure a word line selection circuit.

On the other hand, a pair of bit wires B, are n-channel
The common bit line is connected via a transmission gate circuit (column gate circuit) consisting of MISFETQ ₉ and Q ₁₀ .
CB. The above common bit line CB,
CB is coupled to another corresponding bit line (not shown) via a similar column gate circuit (not shown). The common bit line CB is connected to the input/output circuit I/0. Note that this input/output circuit I/
Specifically, O is composed of a read circuit and a write circuit (both not shown).

The gates of the above transmission gates MISFETQ ₉ and Q ₁₀ include p-channel MISFETQ ₁₁ and n-channel MISFETQ 11.
The output signal of the inverter circuit IV made up of MISFETQ ₁₂ is supplied. The above MISFETQ ₉ , Q ₁₀ , the inverter circuits Q ₁₁ , Q ₁₂ and the X address decoder circuit XD provided in the previous stage of the above inverter circuit
constitutes a bit line selection circuit.

Above Y decoder circuit YD and X decoder circuit
XD has a Y address signal and an X
An address signal is provided.

The input/output terminal T ₁ and read/write control terminal T ₂ of the input/output circuit I/O are connected to the logic circuit
Combined with LGC.

Although the above logic circuit LGC is not particularly limited,
It is used to configure computer circuits. Therefore, the data in the above memory array is stored in the above logic circuit.
Used by LGC.

Above Y decoder circuit YD and X decoder circuit
The XD is composed of, for example, a known CMOS NOR circuit.

Each MISFET for configuring each circuit shown in the diagram is
It is formed on one semiconductor substrate by known CMOSIC technology.

FIG. 2 shows a cross section of a semiconductor substrate constituting a CMOSIC. In the figure, a semiconductor substrate 10 made of n-type single crystal silicon
P-type well regions 21 and 22 are formed on the surfaces of the p-type well regions 21 and 22, and n-type regions 31, 41, 32 and 42 are formed on the surfaces of the p-type well regions 21 and 22, respectively. A conductor layer 51 is formed on the surface of the p-type well region 21 in a portion sandwiched between the n-type regions 31 and 41 with a gate insulating film interposed therebetween. Similarly, a conductor layer 52 is formed on the surface of the p-type well region 22 in a portion sandwiched between the n-type regions 32 and 42 with a gate insulating film interposed therebetween. As a result, an n-channel MISFETQ ₅ is constructed, in which the p-type well region 21 serves as a base gate, the n-type regions 31 and 41 serve as source/drain regions, and the conductor layer 51 serves as a gate electrode. Similarly, 2
n channel by 2, 32, 42 and 52
MISFETQ ₉ is configured.

Although not shown, a p-channel MISFET consists of a semiconductor substrate 10, a p-type region formed on the surface of the semiconductor substrate 10 with a minute interval, and a gate insulating film formed on the surface of the semiconductor substrate 10 between the p-type regions. and a conductor layer formed by

Although not shown in FIG. 2,
One p-type well region has multiple n-channels.
A MISFET will be formed.

In this embodiment, when a RAM consisting of each of these circuits is formed on one silicon chip, each circuit is operated by the power supply voltage -V _EX as shown by the two-dot chain line in the figure. The circuit 1 is divided into two circuits: a circuit 1 that is operated by a power supply voltage _-VDD , and a circuit 2 that is operated by a power supply voltage -VDD. That is, the memory matrix section composed of a group of memory cells and its word line drive circuit WD are considered as one of the divided circuits, and the Y decoder circuit YD and the bit line selection circuit IV
and XD, input/output circuit I/O and logic circuit LGC
is the other circuit of the division.

The power supply voltage -V _DD is cut off in power down mode. On the contrary,
The power supply voltage -V _EX is maintained at a predetermined value regardless of the power down mode.

In the above configuration, when the p-type well region for forming the n-channel MISFET in circuit 1 and the p-type well region for forming the n-channel MISFET in circuit 2 are made common,
When the power down mode is set, the pn junction between the common well region and the source or drain region of the n-channel MISFET in the circuit supplied with the power supply voltage V _DD is put into a forward bias state.

Therefore, the n-channel in circuit 1
a p-type well region for forming a MISFET;
The p-type well region for forming the n-channel MISFET in circuit 2 is configured to be separated from each other. A negative power supply voltage -V _EX is fixedly supplied to the well region on the circuit 1 side, and a negative power supply voltage -V _DD is selectively supplied to the well region on the circuit 2 side depending on the operation mode. Ru. 0 for n-type substrate
A ground potential of volts is given.

In the normal operating mode in which the power supply voltages -V _DD and V _EX are each at predetermined levels, the word line W is at a low level of -V _EX when not selected, and approximately 0 volts when selected. be raised to a high level. Memory cell transmission gate
MISFETQ ₅ and Q ₆ are turned on by setting the word line W to high level. Similarly, the column selection line CL is approximately 0 when selected.
The voltage is set to high level, and the transmission gates MISFETQ ₉ and Q ₁₀ are turned on accordingly.
As a result, the input/output circuit I/O and the flip-flop circuit of the memory cell are coupled via the MISFETs _{Q 5} , Q ₆ , Q ₉ and Q ₁₀ , and data is read from or written to the memory cell. It will be done.

In power-down mode, the power supply voltage -
By setting V _DD to 0 volts, the output of the Y decoder circuit YD is set to 0 volts. In response, the word line W is brought to a low level of approximately _-VEX .

Due to the low level of the word line W, the transmission gates MISFETQ ₅ and Q ₆ in each memory cell are turned off. Bit line B and load means
R ₁ and R ₂ etc. make it almost 0 volts, which is the ground potential. In this case, for example, MISETQ ₅ is configured as shown in FIG.
A potential of V _EX is given. Therefore, no forward bias voltage is applied between the n-type region 41 and the p-type well region 21, and no direct current is caused to flow.

On the other hand, even if the well region _P2 is set to 0 volts by cutting off the power supply voltage -V _DD on the circuit 2 side, the bit line B() remains at 0 volts as shown in FIG.
MISFETQ ₉ by being bolted
The pn junctions in the well, source, drain, and substrate that make up the device are not forward-biased, so no direct current flows between them.

In this way, a so-called power-down operating mode can be realized.

In a RAM like the one in this example,
The memory array, word line drive circuit WD, Y decoder circuit YD, column switch CG, inverter circuit IV, and X decoder circuit XD are repeated along the rows and columns of the memory array. Accordingly, each circuit element for configuring these circuits can be formed with high integration density on a semiconductor substrate. In contrast, the input/output circuit I/O has a relatively small number of circuit elements and has a relatively low integration density.

According to this embodiment, the input/output circuit I/O is connected to the power supply voltage -V _DD along with the logic circuit LGC as described above.
operated by. Accordingly, the n-type MISFET in the input/output circuit I/O is
p to form n-type MISFET in LGC
Since it can be formed in the mold well region, it can be arranged at a high integration density.

In this embodiment, the p-type well region for forming the n-channel MISFET in circuit 1 and the similar p-type well region in circuit 2 are as follows:
As mentioned above, in order to prevent punch-through or the like from occurring between them in the power down mode, it is necessary to form them at a predetermined distance or more. _In this embodiment, the above two types of p
The area required to separate the mold well regions from each other can be reduced.

This can be better understood from the following FIGS. 8 and 4.

FIG. 3 shows an example of a layout when the circuit 1 of FIG. 1 is formed on a semiconductor substrate.

In FIG. 4, the word line drive circuit WD, Y decoder circuit YD, column gate circuit CG, X decoder circuit XD, and input/output circuit I/O are connected to the power supply voltage -
An example of a layout when configured to operate with V _EX is shown.

In the case of the layout shown in FIG. 3, the size of the circuit 1 is made relatively small, so the opposing length of the circuits 1 and 2 is relatively small. As a result, the area required to separate the two types of well regions may be relatively small. Further, since the n-channel MISFET in the input/output circuit I/O can be formed integrally with that of the logic circuit, it can be formed with a substantially small occupied area.

On the other hand, in the case of Fig. 4, the circuit of circuit 1
Circuit 1 includes YD, XD, I/O, etc.
The pairwise increase of and 2 is made relatively long. Also, in this case, the circuits MA, WD, YD, CG, and XD are configured repeatedly as described above, and the integration density is relatively high, so the input/output circuit I/O makes use of empty space like in a logic circuit. This results in a relatively low integration density.

The present invention is not limited to the embodiments described above, and the conductivity types of each semiconductor region may be all reversed. In this case, positive power supply voltages V _EX and V _DD are used as the polarity of the power supply voltage applied to the n-type well.

The present invention can be widely used in semiconductor integrated circuits that are composed of CMOS circuits and include static RAM. In this case, it goes without saying that in the logic circuit added to the CMOSRAM, a MISFET of one conductivity type is formed using the well on the circuit 2 side.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention;
FIG. 2 is a cross-sectional view of a partial structure thereof, FIG. 3 is a pattern diagram of an IC constituting the circuit of FIG. 1, and FIG. 4 is a pattern diagram of another IC. 1, 2... Divided circuit blocks.

Claims (1)

[Claims] 1. Consisting of CMOS circuit, static type
In semiconductor integrated circuit devices including RAM,
The well regions constituting the memory matrix section and word line drive circuit of the RAM are shared and connected to the power supply terminal, and the well regions constituting the bit line selection circuit, decoder circuit, and input/output circuit of the RAM are A semiconductor integrated circuit device characterized in that the well region constituting the memory matrix section and the word line drive circuit is independently shared and connected to a power supply terminal depending on the operation mode. 2 Consists of CMOS circuit, static type
In a semiconductor integrated circuit device including a RAM and a computer circuit, a well region constituting a memory matrix portion of the RAM and a word line drive circuit is shared and connected to a power supply terminal,
The well areas constituting the bit line selection circuit, decoder circuit, input/output circuit, and computer circuit of the RAM are made independent of the well areas constituting the memory matrix section and word line drive circuit, and are shared and selectively selected. A semiconductor integrated circuit device, characterized in that it is coupled to a power supply terminal.