JPS59231917A - Semiconductor device - Google Patents

Abstract

PURPOSE:To drive effectively a signal line having a large load capacity in high speed by converting an external power voltage in a chip, generating a pulse voltage by the converted voltage and driving a part of circuits in the chip through the use of this pulse voltage. CONSTITUTION:A phiil is inputted to a transistor (TR)QL'' and a phiil' is inputted to a TRQD'' in a push-pull buffer circuit and a signal having a voltage controlled by the voltage of the phiil and in-phase with the phiil is outputted to an output phio''. Further, the leading edge of the output phio'' is outputted by a driving capability decided by the W/L of the QL'' and the trailing edge is outputted with a driving capability decided by W/L of the QD'' respectively, the driving capability as required is realized easily respectively and the load capacitor is driven in high speed, where W is the channel width and L indicates the channel length.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to semiconductor integrated circuits, particularly high-density integrated circuits composed of microscopic elements.
Due to the reduction in element breakdown voltage associated with the miniaturization of semiconductor devices, the operating voltage of integrated circuits has been forced to be reduced accordingly. However, from the user's point of view, it is desirable to use the same power supply voltage as before, for example, a 5V single power supply, in terms of ease of use. It is conceivable to lower the voltage Vb at a lower voltage Vb and operate the fine element with the lowered voltage Vb.

FIG. 1 shows an example of this. For example, the circuit a' of the entire chip 10 including the input/output interface circuit is
This is an example of operation using the internal power supply voltage VL lowered by the Mitsuta 30. In this example, the entire chip can be composed of elements having approximately the same size.

FIG. 2 is a 1% application previously filed in No. 56-57143, in which a fine element is used for the circuit a that determines the actual integration density of the chip 10, and the external power supply voltage Vcc is limited by voltage limiter 30. This is an example of operation with a lowered voltage VL.

On the other hand, drive circuits that do not contribute much to integration density, such as input/output interfaces, are generally high! This is an example in which a relatively large element is used because the source voltage is easier to design, and it is operated by applying Vcc 'E to it.

This enables a highly integrated circuit (hereinafter referred to as LSI) that operates at Vcc when viewed from outside the chip. This idea is based on l5SOO'83. DIGERT 0FTF30HNI
It is also seen in OAL PAPFR8, PP234-235°, etc. Note that the circuits a, a', and b are bipolar transistors or MOSs such as 0-MOS and [-MOS.
It may be composed of any transistor. Further, these two types of transistors may be used together. Also, it is not necessarily necessary to stick to 5V as the normal operating point Vcc.

It is clear that it can be set arbitrarily depending on the design convenience, such as Vcc = 3 V, ■L = 2 V, etc.0 Here, the chip refers to the memory LS1. Logic LSI.

Or it shows a piece in which other LSI is built.

In other words, in a memory LSI, one circuit a is a memory array and its related circuits, and in a logic LSI, for example, a microcomputer has various types of ROM or R.
This indicates an area such as an AM area that is made up of a certain type of cell repetition.

A specific example of the voltage limiter circuit in the above voltage limiter system is disclosed in Japanese Patent Application No. 56-57143.

Patent Application No. 168698/1982 or Patent Application No. 2/1983
It is described in No. 20083.

Although details are not shown in FIGS. 1 and 2 to simplify the explanation, the voltage limiter 30 has the function of lowering and outputting not only a simple DC voltage but also a signal. . In general, this signal generating circuit may be functionally the same as the circuit existing in part b in FIG. 2, etc., with the only difference being the output voltage.

Therefore, it is often more efficient to design 30 and b in FIG. 2 in a mixed manner. In some cases, for the same reason, 30. It is of course possible that the circuits a and b coexist.

Figure 3 is an example where 30 and b are mixed, and in the same figure, P()1
．． PG4 is the signal in the 5 circuit (in this case, the signal to the next stage)
and the signal given to a are output. This example is disclosed in Japanese Patent Application No. 56-57143. In the figure, 13 is a voltage converter that lowers the external power supply voltage, for example, VL, and PGI-PG4 are various signal generation circuits, such as a timing pulse generation circuit in a memory LSI, and logic gates such as NAND and NOR in a logic LSI. Corresponds to a circuit, etc. The outputs of PGI and PG4 generate a signal dropped to a low voltage (VL) and supply the signal to the part of circuit a. In this example, the application range of the voltage limiter can be limited to only the circuits that supply signals to circuit a, which is effective in reducing the load on the voltage limiter. Furthermore, since the circuits 30 and b can be used in common, the efficiency of chip area utilization can be increased.

Japanese Patent Application No. 56-168698 discloses a more detailed embodiment of PGI and PG4, taking as an example a dynamic pulse generation circuit used in a memory LSI. The details of the operation of this pulse generating circuit PG are described in 1981 IEICE Semiconductor/Materials Division National Conference Proceedings 69. The outline will be explained with reference to FIG. That is, when the input φ□ is applied, the gate voltage of QD is discharged from a high potential to a low potential, and the QD is turned off, and at the same time, the gate voltage of QL is discharged from a low potential to a high potential (using the bootstrap voltage). As a result, QL turns ON and output φ. varies from low potential (Ov) to high potential (v
cc). PG2 in Figure 3. PG3 is configured by this PG, for example. FIG. 5 shows an example of a specific circuit configuration of PGI or P,04 in FIG. 3, and uses the above PGB to generate a signal φ. (for part b), signal φ. t (
This figure shows a circuit that generates both signals for part a).
φ in the output stage in the figure. This is an example in which inverters QL' and QD' are added in parallel. QLL is φ. This MO8T is used to lower the output amplitude of the motor, and may be either an acknowledgment type or a deblessing blind type.

130 is a voltage converter that converts vcc to vL' and outputs the voltage. At this time, the high potential voltage of φ0' becomes vL'-VT (QLL threshold voltage), and according to this relationship, vL' can be determined so as to obtain the desired voltage. In this example, in the same circuit, a and b in Figure 2 are
It can be generated simultaneously with the signal to the image area, which is useful for simplifying one circuit.

Now, 1. In normal integrated circuits, after the final manufacturing process, 1. a voltage higher than the voltage used in normal operation is intentionally applied to each transistor in the circuit, and the transistors that are prone to failure due to gate oxide film defects, etc. The aging test) has been carried out to ensure reliability. To improve the detection rate of defects through this aging test,
It is necessary to apply a slightly lower voltage to each element than would destroy a normal element. However, in an integrated circuit chip that is configured to supply power supply voltage to circuit portion a with low withstand voltage through a constant voltage circuit inside the chip as described above, sufficient aging voltage is not applied to this portion. .

Therefore, a specific example in which the above aging test can be performed also on part a is published in Japanese Patent Application Laid-Open No. 56-1686.
98. and JP-A-57-220083r
has been disclosed. Figures 6 and 7 are examples of this.
In order to enable an aging test, the relationship between the voltage VL applied to section a in FIG. 2 and the external power supply voltage Vcc is determined. If you make it a characteristic like this.

Normal operating conditions and aging test conditions can be set appropriately for the circuit sections a and b in FIG. 2, making it possible to carry out aging tests in the same manner as in the past. In particular, in FIG. 7, the slope of the dependence on vL and Vcc is divided into two stages: m1m'. More detailed condition settings are possible.

1 having the above characteristics occurs at 30 in FIGS. 1 to 3 or 130 in FIG. In addition.

In the case of 130, it is output through the MOS) run lister Q, so as mentioned earlier, it is necessary to be careful that VL/" is generated which is corrected for the drop in the threshold voltage of QL, but it is considered that they are essentially the same. Various specific circuit structures for generating these voltages are disclosed in Japanese Patent Application No. 56-168698 and Japanese Patent Application No. 57-220083.

FIG. 8 shows the implementation cost of a buffer circuit for increasing the load driving capability of VL generated as described above.

It is disclosed in Japanese Patent Application No. 57-220083. In the same figure, L
This is a circuit that generates the above-mentioned V L f in MI.

MOS) run listers QIOI and Q102 constitute a buffer circuit. Here vPP1 ma vL ten Vth
(MOS transistor threshold voltage) higher.

Further, P is set to be much larger than the equivalent on-resistance of the QIOI. As a result, the gate voltage of Q102 is
vL+Vt h (!: Nari, Q102)/-Sumi pressure vL1 becomes equal to VL by appropriately selecting W'/L (channel width/channel length) of Q and o2.

A buffer circuit having desired driving capability can be realized.

The conventional technology described above enables highly integrated L
SI%, but there was a problem in driving the circuit at a portion such as a in FIG. 2 at high speed. That is, in a circuit as shown in FIG. 5, the signal φ has a voltage lower than both external temperature voltages.

' is generated and supplied to the circuit of FIG. 2a, but φ. In the output section of ', the equivalent on-resistance becomes large because the MOS run listers QLL and QL' are connected in series. Therefore, high-speed driving is difficult when the load capacity is large.

[Purpose of the invention]

Therefore, one object of the present invention is to provide a circuit configuration suitable for high-speed driving of a signal line having such a large load capacity.

[Summary of the invention]

The present invention provides a circuit configuration capable of high-speed operation in a semiconductor integrated circuit in which at least a part of one circuit operates with a signal whose voltage or amplitude is limited to a lower value than an external voltage by a voltage limiter. This relates to a circuit configuration that drives a part that operates at a voltage as low as 1% at high speed.

In other words, in the present invention, the output section of the voltage limiter has:
A buffer circuit is provided to drive the load and at high speed. More specifically, the buffer circuit is as follows.

Signal y controlled to low voltage by voltage limiter;-
, is input to the gate of an MO8 transistor, and the output is taken out from its drain 1 or source.

[Embodiments of the invention]

The details of the present invention will be explained below using examples.

Although the following explanation will be given using an N-channel type MOS transistor as an example, the present invention can also be applied to other types of run listers (for example, P-channel type MOS) by reversing the potential relationship.

9 and 10 show a basic embodiment of the present invention. In other words, FIG. 9 shows the MOS) run lister QL//
A signal φttf whose voltage or amplitude is controlled by a circuit such as that shown in FIG. 5 is input to the gate of the circuit, and the output is taken out from the source. As a result, a signal that is in phase with the input φi is output, and by appropriately selecting the W/L (channel width/channel length) value of QL//, it is possible to obtain any drive capability and load the load. It becomes possible to drive the capacitor OL at high speed. According to this embodiment, unlike the prior art, there is no problem of the equivalent on-resistance increasing due to two MOS) run resistors being inserted in series, and high-speed operation is possible because the QL'I alone determines the driving capability. easily obtained. Also, the output voltage V on the high potential side. ut (hereinafter referring to the high potential side of the signal voltage unless otherwise specified) is,
Let the voltage of φij be Vin, and the threshold voltage of QL'' be ■.

vout=vio-VT(1) Therefore, by controlling Vin'E, the output voltage on the high potential side can be controlled, and the required Vout
Figure 10 shows that Vin'F can be fixed according to the voltage of
A similarly controlled signal φi is input to the gate of QD/l, and the output is taken out from the drain, which is shown on the left. In this embodiment, an inverted signal of φi is output to the output terminal.QD//
CLl is driven with a driving ability determined by W/L. Therefore, as in FIG. 9, by appropriately selecting the W/L%, any large driving capacity can be obtained.

In the embodiment shown in FIG. 9 described above, the elements on the ground side, and in FIG. 10, the elements on the source voltage side are not particularly shown.

Needless to say, appropriate elements are inserted depending on the purpose.

FIG. 11 shows an example in which a push-pull type buffer circuit is constructed using the embodiments shown in FIGS. 9 and 10.
The inverted signal φiI of φi is input to φ!j-QD'' to L'', and the output φ. ″ is in phase with φi, and φi
A signal having a voltage controlled by the voltage of j is output.

According to this embodiment, φ. The rising part of ″ is W/ of QL″
The L and falling portions are outputted with driving capabilities determined by QD'' (7) W/L.

In each case, it is possible to easily realize the driving capacity as required, and it becomes possible to drive the load capacitance OL at high speed. In addition,
Although each of the above embodiments has been explained using an N-channel type MOS run lister as an example, the present invention can also be applied to a P-channel type by reversing all relative potential relationships. For example, if a p-channel type MO8) run lister is used in the circuit shown in Fig. 11, and the power supply voltage is -5V (-5V m OV), the tmm range operation is QL.
It is only necessary to operate the drain of `` with -5V and the source of QI/ with OV (ground). At this time, the output voltage is the same as before, and the voltage of the input φi is assumed to be vin.

vout=vin-VT, for example vin=
'V, VT=-10.5v'' (threshold voltage is negative for p-channel type) is V.=-4-(-9,5)=-
It becomes 3.5v. Therefore, in this case as well, V depends on the value of vtn. It becomes possible to perform ut'F control. In addition, the above operating range') OV (corresponding to the above 15V) 4+5V
(corresponding to the above □v), it is only necessary to shift the entire unit as it is in the positive direction by 5v. That is, the drain of Q,'' is set to Ov, the source of QD'' is set to 5V, and vin
= 1v. Output voltage V at this time. ut is 1.
It becomes 5V (a signal that changes to 1.5V with +5V as a reference). As mentioned above for the 0M08 type LSI. Both n-channel and p-channel MOS transistors are used, but in that case, one of the above-mentioned ones can be used depending on the purpose. In addition, in the case of not only a MOS) run lister but also a bipolar transistor, the same operation can be achieved by configuring a circuit in which the collector of the bipolar transistor corresponds to the drain, the emitter source corresponds to the gate, and the pace corresponds to the gate. Therefore, the principle of the present invention can be applied to that end.

The above description also applies to the following embodiments.

Now, in the embodiments shown in FIGS. 9 to 11, it was mentioned earlier that the input signal is generated and provided by the circuit shown in FIG.
In the embodiment shown in FIGS. 1 and 11, as shown in equation 1 (1),
A voltage lower than the voltage vin of the input signal φi by ①A is output. Therefore, the value of -vin is the required voltage ■
It is necessary to generate only a high voltage. for that purpose,
In FIG. 5, the output voltage V of the voltage converter 130,
/ should be adjusted.

FIGS. 12 and 13 show embodiments that allow the above adjustment easily. Each circuit configuration is based on the configuration shown in FIG. 8, and each has a Ql. 3 and Q104 are the same except for the added parts. Therefore, in FIG. 12, Ql. The gate voltage of 2 is vL+2v,r, Ql in FIG. The gate voltage of 2 is v, +3vT, solenoid output cover vL1=VL+V, r.

VL'1'=v+2VT. If higher voltage is required, use Q,ol,Q,. 3. Ql
. 4 MOS) Further MOS in the series circuit of the run lister)
Just add a runlister. It goes without saying that the values of v and p should be set as Vpp>V, + k VT in accordance with the purpose, where k is the total number of MOS runlisters connected in series. Therefore, the first
In Figure 2, vpp>vL+2■, in Figure 13, V, p>
It must be as follows: VL+3V.

With the embodiments described above, any required voltage can be easily obtained. Therefore, these examples are
For example, when applied to 130 of the circuit in FIG. 5, the output φ. By applying ' to the circuits shown in FIGS. 9 to 11, a signal having an arbitrary value can be obtained as an output. For example, Figure 12, 5
When the circuit is configured according to the embodiments shown in FIGS.
The gate voltage of QLL in FIG. 5 is VT+DT, and the output φ. ′
The voltage of is V, so the final output φ in FIG. ″
The voltage is VL-V. Moreover, if FIG. 13 is applied instead of FIG. 12 above, the gate voltage of QLL becomes ■A+2vT, so φ. '' is vL. In this way, any output voltage can be easily obtained.

With the above method, it is possible to obtain a signal with a desired voltage and a large drive ability, but depending on the case.

Like the area where vco is lower than vo in Figures 6 and 7,
V as vL. A value equal to C may be required. In that case, as can be seen from equation (1), the signal vin of the input signal φi is set to V. It becomes necessary to raise the temperature higher than C.

tP, 14 figure is V. This is an embodiment for outputting a signal with a higher voltage than C, and differs from the circuit shown in FIG. 5 in that the voltage at the drain of QLL is changed from vcc to 15'.

Here 'pp' is the output φ. The voltage of I is selected to be higher than the required value. Namely.

This output φ. ' as the input in Fig. 11, the output φ in Fig. 1.1. ” voltage as V+L (in this case, vL>voc)
If you want to use φ. Since the voltage value of ' is vL+VT, it is selected as vppI>vcc+v, r. According to this embodiment, the output φ is greater than or equal to the required vc. '+ can be obtained.

For the same reason as above, ■1' in Figures 5 and 14 is also used as ■. . There may be cases where a higher value is required. 81
Figure 5 shows an example of realizing this.

Figure 13 is Ql. Drain voltage of 2') from vcc to v
, p''.Here, ■, pzz is selected to have a voltage value higher than the value required as the output vLIII. That is, the circuit is configured as shown in FIGS. 15, 14, and 11, Output φ in Fig. 11. If the voltage of II is closed, then d Gi V,, ">VL," = V, + 2
VT (D). Note that for the above purpose, it goes without saying that vPP>Vpp"-1-VT should be selected. According to this embodiment, even if it is more than vcc, It is possible to obtain the value shown in Fig. 14,
It goes without saying that even if a voltage value of 1, vcc or less is required in FIG. 15, it can be realized with the same configuration.

Now, the 14th prisoner, vpp above ■cc in Figure 15.

It is necessary to generate a DC voltage of v' vII.

pp'pp Regarding this, the circuit disclosed in FIG. 29 of Japanese Patent Application No. 57-220083 can be applied as is.
vo. This is a voltage doubler rectifier type circuit that generates a DC voltage of −V, r), but in order to further increase the DC voltage supply capability and reduce ripple noise due to rectification, it is necessary to A wave rectifier type voltage doubler rectifier circuit may be used. In the same figure, φ8. φ8 is a negation/affirmation signal of a repetitive signal oscillated within the chip, and is generated, for example, by a circuit as shown in FIGS. 3 and 32 of the above-mentioned prior application. C is a parasitic capacitance that occurs parasitically in the output wiring. The same diagram of the operation of this embodiment (B
), as shown in N1. N1/ is Q respectively. ,.

V at Qc1/. It is precharged to the voltage of C-VT in advance. Then φ3. φ. ′ becomes vc, then OB
.

Due to the capacitive coupling of OB', N1. N1/ is respectively.

The voltage increases to 2 vco-vT during the time period T, , T2. This voltage is Q. 2. appears at the output VP via Qo2', and its voltage is Q. Due to the drop due to the threshold voltage of 2-QC2', VP=2 (Vcc-vT).

This v is V l,
I'P is fine.

According to the above embodiment, T1. Since the output receives charge from the capacitors OB and CB' during any time period T2, the current supply capability can be increased and ripple noise can also be reduced.

FIG. 17 shows another embodiment in which a voltage higher than Vco is generated, in which the signal φ of FIG. ′ is provided. In the same figure, PG,
The configuration of PG is exactly the same as that shown in FIGS. 4 and 14.

The operation of this embodiment will be explained with reference to the same figure (Bl).

, ■,' are precharged to ■oc-vT by QBB. P.G.

When input φi of PC) rises, φBB, φ0 . φ0 begins to rise.

Therefore, the VP' point increases due to the capacitive coupling of CBB. At this time, the VP' point rises due to capacitive coupling of OBB. At this time, so that ■A'〉VL'-VT,
The value of CB11 is fixed. Therefore, φ.

φ. is V. The rise stops at C, but the potential of φ0' is Vc
yLl above c = ■ increases to the value of a (vL'〉vc
c+"r) According to this embodiment, since the voltage is boosted only when necessary, an efficient design can be achieved in terms of power consumption and the like.

In the above embodiment, the inputs of PG and PG are set to the same φi, but it is also possible to change one phase as appropriate. For example, it is also possible to input the PG somewhat later than φi and to boost the voltage after φ0'- has once risen to Vcc-VT.

Although various boosting methods have been described above, these embodiments can also be applied not only to n-channel type MO8) run-listers but also to other types of transistors, as explained in the embodiments shown in FIGS. 9 to 11. can. For example, the case of a p-channel MO8) run lister can be directly applied by reversing all relative potential relationships as previously described. That is, the source voltage; 4. −
5. V (operates in the range of -5V→Ov),
In each embodiment, grounding is also the key, and Vo. All you have to do is close it and apply -5v. Talented. If you want to shift the overall voltage by 5v in the positive direction and operate in the range of QV→5v, you can operate as is with the ground terminal set to 5v and the voc terminal set to Ov. In the case of a 0MO8 type LSI, either n-channel or p-channel type transistors or a combination thereof may be used as appropriate depending on the purpose.

FIG. 18 shows an example in which the embodiment shown in FIG. 1M9 is applied as a power supply means for various circuits. Here, various circuits are generally
This corresponds to part a in FIG. 2, that is, a circuit composed of microscopic elements, but it is not necessary to limit it to 1%. Although an example is shown in which the present invention is used as a power supply means for a data line in a memory, it can also be used as various power supply means in other decoders, microcontrollers (7), ROMs, RAMs, etc.

In FIG. 18, reference numeral 1 indicates a memory array, which is composed of static type memory cells or dynamic type memory cells of IMOS transistor type. D,~D
n, Do-Dn are data lines, Q6. Q7～Q
a', Q? ' acts as a feeding element. Here, an example of a memory that processes differential signal voltages appearing on data pairs such as Do and bo is shown. In addition, a plurality of memory cell beams are connected to data lines such as D. The connection method differs depending on the type of memory cell, but for example, it is connected as disclosed in Japanese Patent Application No. 58/24579. φ, 2
゜ is the power supply signal, and Q6 from the desired data line voltage
It is a signal (generally a pulse signal) controlled to a voltage higher than the threshold voltage of Q7' by V and r. This signal can be easily generated by each of the previously mentioned embodiments.
The voltage of the data line is supplied to a predetermined voltage controlled by the voltage of φp21. In addition, Q6 and Q7. Alternatively, if there are large manufacturing variations in the threshold voltages of Q6' and Q7'', a difference may occur in the power supply voltage between the data lines Do, 'r5o-Dn and Dn, but if this becomes a problem, , by adding q and QB′ shown by the broken line in the same figure, φ2
□, give a signal φ,1 with a higher voltage to the gate,
Do. ~D, Tori. By shorting both data lines.

The above problem can be easily avoided.

According to this embodiment, the driving capacity described above is increased;
This circuit can also serve as a power supply means that is originally required, and it is possible to realize a semiconductor integrated circuit that is easy to design at high speed and has high chip area utilization efficiency. Note that although the power feeding means is illustrated here as a power feeding means for two data line pairs, the number of data line pairs is not particularly limited. For example, an open bit line (0pen bit 1!) in a dynamic memory is used.
ne) It can be applied as is even when there is only one data line, such as in a memory or ROM.

FIG. 19 shows one of the more specific embodiments of FIG. 18, taking a one-transistor type MO8 dynamic memory circuit as an example, and comparing it to a memory array circuit that mainly uses a voltage lower than the externally applied power supply voltage. An example in which the present invention is applied to a related circuit is shown. In the same figure, the circuit group 1 surrounded by the dashed-dotted line is a memory array circuit, and the circuit group 2 surrounded by the dashed-dotted line is a circuit that controls the memory array circuit and amplifies the signal from the memory cell (direct peripheral circuit). A circuit group 3 surrounded by a chain line is a circuit (indirect peripheral circuit) that provides a signal to the direct peripheral circuit, amplifies the memory signal from the memory array circuit, and commits the memory signal to the memory array circuit. The basics of the above circuit configuration are already known in Japanese Patent Application No. 58-245.
79, and the details of the structure and operation are detailed in the retrospective specification. In the embodiment shown in FIG. 19, the embodiment shown in FIG. 18 is applied as a power supply means (in this case, precharging) for the common source terminal of the sense amplifier composed of the data line, D, Ql, and Q2, and the embodiment shown in FIG. q7 deri.

D, Qlg connect the common source terminal to a signal φ applied to the gate, 2. The point of precharging to a value lower by the threshold voltage than the voltage of , and accompanying this, E.

This application differs from the above application in that parts F, G, and H have been changed. In the figure, the voltage of the data line when the external power supply voltage is co=5V is shown as 3.5V (here, for convenience, this value is
), MOS) run lister threshold voltage VVT=
This is an example of the voltage value of each main part when the voltage is set to 0.5.

E is a circuit that generates a voltage that serves as a reference for operation, and vo
With c=5v as input, TVL□' (4,OV), vL
z" (4,5V), outputs B. As this generating circuit, the embodiments shown in FIG. 12, FIG. 13, or FIG.
=VL+V, r=3.5V+o, 5V=
4. Ov, in figure 13 or figure 15 VL1''=
vL+2 VT=3.5 V + 1. OV =
4.5 V can be used as it is as VL□', ■1□''. Fig. 20 shows the embodiments of Figs. 12 and 13 realized in one circuit. The above two-value voltage can be generated with one circuit. Therefore,
It has the advantage of reducing the semiconductor chip area and since it operates based on the same LMI, variations between vL□' and V42II can be reduced. In addition, in the same figure, QI O2'
, Q102'' can be selected from various values as in the several embodiments already described, but here, the drain voltage of Q1o2'' which outputs vL2'' which requires a relatively high voltage is set to the drain voltage shown in FIG. The voltage vP (
Vcc is directly applied to the drain of Q1o2' which is used as VPP□' and outputs VL2' with a relatively low voltage. In addition, the VPP in the same figure is patent application No. 57-2200.
The voltage generated in the example of FIG. 29 of 83 may be used.

In Fig. 19, F is a signal iP2 and v with a voltage amplitude of 5V.
L□'' (4,5V) is input, and a signal of φ, 2, which is lower than VL2 by VT, is output.As a concrete circuit for this, examples such as those shown in FIGS. 5 and 14 can be used, but for example, here Now, we will use the circuit shown in Figure 5. In this case, PG
'VL' is generated by E in Figure 19.
, "v" is given, so ■ 130 for L1 generation does not require anything special.Also.

φ. It goes without saying that QLQD, which generates QLQD, can be omitted if unnecessary. Here, in order to prevent fluctuations in the data line voltage due to variations in the threshold voltages of Q6 and Q7, the gate voltage of Q5 is made slightly higher than the gate voltage φPIVφpHj, and Q5 is turned on. As mentioned earlier, it is sufficient to short-circuit φ, 1, but the voltage of φ, 1 is V. If it is set to 0, the above conditions may not be satisfied. To solve this, for example l8800
83. DIGBSTOF TECHNICAL P
A-PER8゜PP224-225. The voltage of φP1 may be increased to be higher than vcc (strictly speaking, higher than the voltage of φ, 2.) by the method shown in FIG.

Figure 19G shows the signal φ with a voltage amplitude of 5V, and v1□
This is a circuit which takes ``(4,5V) as an input and outputs a signal φX having the same voltage amplitude as VL□.As a specific circuit, a circuit as shown in FIG. 23 of Japanese Patent Application No. 56-168698 may be used. This φX becomes the word line signal of the memory cell, and is selected to be 2v (1v here) higher than the voltage of the data line.In this way, the word line voltage is set higher than the data line voltage of the transfer transistor of the memory cell (for example, QMl) by increasing the threshold voltage preparatively.

It is possible to eliminate memory signal loss due to the threshold voltage of this transistor during reading. Furthermore, since the write voltage to the memory cell can be increased by this amount, stable memory operation is possible.

Figure 19H shows VL2' (4, OV), ``cc (
This is a circuit that generates a DC voltage of VcP (3.5V) by inputting 5V). As for this specific circuit configuration.

As shown in Figure 21, VCO is connected to the drain, and ■
A so-called source follower type circuit which inputs Lm' and outputs vcP from a source is given as an example. This circuit is simply configured with one MOS (27912901) and occupies a small area, making it easy to reduce the voltage. It is possible to generate P. In addition, as shown in the same figure, insert a high resistance R, between the output terminal and the connection, and let a small amount of current flow.
It is also possible to stabilize the operation. Here, VcP is Ilo.

l109 precharge voltage or Q23~Q2s
It provides a write voltage by a write circuit composed of Although a method of inputting an internally controlled voltage is shown, similar to the data line power supply means, Q, 8. Q2. A pulse signal whose voltage is controlled inside the chip is applied to the gate of Il.
It goes without saying that a method may be adopted in which the voltages of o and Ilo are controlled to predetermined values.

According to the embodiment described above, high-speed design is easy and effective for the same reason as the embodiment shown in FIG.

A semiconductor integrated circuit with high efficiency in the use of board area can be realized.

Although a dynamic type memory is described here as an example, it goes without saying that the present invention is also applicable to a static type memory as disclosed in FIG. 4 of Japanese Patent Application No. 58-24579. In addition, in FIG. 19, a part of the memory array is shown as one block for ease of explanation, but
It is not limited to this, but for example,
1042.57-125687.58-4162, the present invention can be applied as is to a memory array configuration in which the data rear end is divided into a plurality of parts to increase the number of 87N.

Among these, it is also possible to have a configuration in which the circuit related to the power feeding means constituted by Q5 to Q7 in FIG. 19 is shared by a plurality of divided data lines as shown in FIG. 17 of Japanese Patent Application No. 56-81042. Furthermore, as shown in Table 1, it is also possible to adopt a combination of MOS (MOS) run lister dimensions as disclosed in Japanese Patent Application No. 58-24579. The reason for determining the dimensions of each MO8) run lister in the same table is as stated in the previous application, but in the same table, in order to give priority to high-speed operation, Lg of Q3 and Q4 is 1.6 μm, ToX
, = 20nm (prior application Lg = 2.1 fim, Tox
= 40nm), and stable operation is prioritized, Q1. +
, C2゜(7) I,g=2.7μmTox=40
This differs from the previous application in that the thickness was set to 2.5 nm (Lg = 2.1 μm, Tox = 40 nm). Note that this table shows an example of a combination, and it goes without saying that other combinations can be adopted depending on the purpose.Also, the value of Lg in the same table gives an approximate central value, and the caroieties of the manufacturing process It must be taken into consideration that fluctuations of approximately ±0.1 to ±0.5 μm may occur due to variations. MO shown in the same table
S) By combining the run listers, the number of micro-sized transistors can be minimized depending on the circuit operation conditions, so the number and load of the voltage limiter can be reduced.

It becomes easier to realize highly integrated memory. Also, in the 19th V
L2/, VL□'I, etc. have relatively high wiring impedance, so depending on the design, they may easily generate noise.
As disclosed in Fig. 16, a noise capacitor can be added to any location (connection method such as C1 shown in Fig. 16 (5)).
, or other noise sources.

For example, it appears on an integrated circuit with a built-in substrate voltage generation circuit.
1. In order to avoid the influence of substrate voltage fluctuation noise, which is often a problem, it is possible to reduce noise caused by coupling with the noise source by providing a shielding electrode between the noise source and the noise source.

Furthermore, the circuits of each part used here are merely examples, and it goes without saying that various modifications can be made in the details. For example, C3° to Q3 in FIG. It is also possible to use a circuit such as that described in B8 553 of the 58th Annual General Conference of the Institute of Electronics and Communication Engineers as the high potential level regeneration circuit configured with the following.

Although the present invention has been described in detail with reference to each embodiment, the scope of application of the present invention is not limited thereto. For example, here we mainly describe memory circuits, but 5
As stated at the beginning of this specification, memory LSI, logic LSI
It is applicable to SI or all other LSIs. In addition, regarding the types of elements used, there are LSIs using both p-type and n-type MOS transistors, 0MO8-type LSIs that use a combination of both, LSIs that use bipolar transistors, and a combination of 0M0O-type and bipolar-type LSIs. Not only BI10MO8 type LSI and LSI using 8i material, but also LSI using compound semiconductor,
For example, the present invention can be applied directly to an LSI in which elements are formed on a GaAs type substrate.

In addition, in FIG. 2, a, b
Although the circuit section BMO8) is distinguished by the size of the run lister, it is not limited to this. For example, 0M
In order to solve the problem of a drop in breakdown voltage due to the latch-up phenomenon that often occurs in O8 type LSIs, a high integration density is required.

The part a, which requires a small isolation distance between elements (that is, a low latch-up withstand voltage), is connected to the external power supply voltage fa part 2 by 30. The parts that are connected directly to external input/output terminals and require a high withstand voltage are operated at a voltage lower than the withstand voltage.

It is also possible to increase the isolation distance between elements, increase the breakdown voltage, and operate directly with an external power supply voltage. Note that here, a configuration based on a combination of element dimensions and inter-element separation distances is also possible. Furthermore, even when using elements of the same size, part b is operated at a high voltage for easy external interface circuit design or high-speed design, and part a is operated at a high voltage for purposes such as low power consumption. A voltage operated configuration is also possible. In addition, in the embodiment, the external power supply voltage was mainly explained as cc = =: 5V, but it is not limited to this. For example, if electricity is used as a power supply, the external power supply voltage is 3V (1.5V x 2, etc.), and the internal operating voltage is (v
It is also possible to set L) to 2V.

〔Effect of the invention〕

According to the present invention described above, even if a fine element with a low breakdown voltage is used, it can operate stably at a relatively high voltage.

0 that can provide semiconductor integrated circuits that are easy to design at high speeds.

[Brief explanation of drawings]

Figures 1 to 8 are diagrams explaining the prior art, Figures 9 to 2
Figure 1 is a detailed explanation of the present invention0 Figure 1n Figure 2, ? θ 67 Figure 7 δ Country L J Arithmetic 9 Yen %10 Painter Ti Figure 12 Figure 14 Figure 16 - Diagram! 8th φ door 2 no, ■ ■ ■ 蓼■ ■

Claims (1)

[Claims] 1. Voltage converting means for converting an external power supply voltage to another voltage within the chip; pulse generating means for generating a pulse signal based on the voltage converted within the chip; A semiconductor device, wherein at least a portion of the circuit operates in accordance with the pulse signal. 2. In claim 1, the output of the pulse generating means is passed through the current amplifying means. 2. The semiconductor device according to claim 1, wherein the semiconductor device is supplied to at least some of the circuits.