KR960010572B1 - Data output buffer using level converter circuit - Google Patents

Abstract

The circuit improves a semiconductor memory device using an inner voltage source by increasing the operation speed under a low voltage condition, and includes pull-up/down inputs controlled by an enable signal to receive a couple of data signals according to the inner voltage source, an output pull-up transistor consisting of a PMOS using an external voltage source as a power, an output pull-down transistor consisting of an NMOS whose drain is connected to the ground, an inverter connected between the pull-down input and the gate of the pull-down transistor, a level converter connected between the pull-up input and the gate of the pull-up transistor to increase the "high" level biased from the pull-up input to the external source and biase the "low" level biased from the pull-up input as the ground level.

Description

Data output buffer using level conversion circuit

1 is a data output buffer circuit diagram according to the prior art.

2 is a data output buffer circuit diagram according to an embodiment of the present invention.

3 is a voltage waveform diagram of a data output buffer according to an embodiment of the present invention compared with the prior art.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a data output buffer for outputting data read from a memory chip to an outside of a chip.

As semiconductor memory devices are highly integrated and large in capacity, there is a demand for higher chip operating speeds. Accordingly, in order to speed up the operation speed of the chip, a voltage boosting circuit, an equalization or precharge circuit, which is a voltage pumping circuit, is provided in the chip to satisfy the demand of the operation speed. The voltage boosting circuit is a circuit that outputs a boosted voltage Vpp having a voltage level higher than the power supply voltage Vcc as the operating constant voltage of the chip is gradually lowered. The equalization or precharge circuit is a circuit for bringing an enable timing of a signal at a high speed.

In particular, as is well known in the art, the transfer operation of the data output buffer which outputs data read from the memory module to the outside of the chip is an important factor for high-speed data access. Furthermore, in the case of the data output buffer, the data read out from the memory module is output to the outside of the chip of the high impedance state, that is, the system. Therefore, it is important that the data output buffer not only outputs the high speed output but also outputs data of higher voltage level. Therefore, in the case of the output stage of the data output buffer, that is, the data output driver, the channel size of the transistor constituting the circuit is usually made larger than that of other circuits.

By doing so, it prepares for the large loading of the data output terminal of the chip, that is, the DOUT pin, and outputs the data at a high voltage level. However, a design and layout problem arises as a signal for controlling the gate of the data output driver must be applied at a signal level sufficient to drive a transistor having a large channel of the data output driver.

A circuit diagram of a conventional data output buffer to solve this problem is shown in FIG. The data output buffer shown in FIG. 1 is an output terminal consisting of an output pull up transistor M1 and a pull down transistor M2 in which an NMOS transistor is used, and read out from a predetermined memory 쎌. The data signals DB and DBB, which have been output, are respectively input and are composed of a pull-up control circuit for controlling the output pull-up transistor M1 and a pull-down control circuit for controlling the output pull-down transistor M2. The pull-up control circuit includes first and second NAND gates 1 and 17, first and second capacitors 2, 11 and 15, and transistors 3, 4, 5, 6, 7, 8, and 12. And 13, 16 and 18 and inverters 9, 10 and 14. The pull down control circuit includes a third NAND gate 19 and an inverter 20.

The pull-up control circuit and the pull-down control circuit are controlled by a PITRST signal that enables the output operation of the data output buffer. The PIS signal, to which the PIS signal for setting an initial value is input, is enabled by the row address strobe signal (/ RAS). In the configuration of the pull-up control circuit, the first capacitor 2 having one end of the electrode connected to the output terminal of the first NAND gate 1 has the voltage level of the n1 node which is precharged to the Vcc-Vth level when the chip is enabled. To pump to a voltage level higher than the precharge voltage level. The second capacitor 11 having one end of the electrode connected to the PIS signal through the inverters 9 and 10 is for precharging the voltage level of the n1 node. The third capacitor 15 having one end of the electrode connected to the output terminal of the first NAND gate 1 through the inverter 14 has a voltage of the n2 node precharged to the Vcc-Vth level when the chip is enabled. To pump the level to a higher voltage level than the precharge voltage level. Therefore, the rest of the pull-up control circuit except for the first NAND gate 17 and the transistor 18 becomes a boost trap circuit.

The operation characteristic of the conventional first circuit as described above will now be described. In FIG. 1, the external power supply voltage (ext. Vcc) is applied to the source power supply of the pull-up and pull-down transistors M1 and M2 and the internal power supply voltage (int. Vcc) is applied to the remaining components. In addition, since the chip's output data (DOUT) pin or pad has a heavy loading, the size of the output pull-up and pull-down transistors M1 and M2 for the data output driver is significantly larger than other transistors. Accordingly, in order to sufficiently drive the large output pull-up transistor M1, the pull-up control circuit includes first, second, and third capacitors 2, 11, and 15 for pumping the MOS transistor as shown in the drawing. In this case, the n1 node is precharged to the Vcc-Vth level by the EnMOS transistors 3 and 12 simultaneously with the power-up of the chip, and the Vcc + 2Vth simultaneously with the chip being enabled. The voltage level is about. The n2 node is precharged to the Vcc-Vth voltage level by the NMOS transistor 8 during power-up of the chip, and at the same time as the enable of the chip, the power supply voltage (int. Vcc) is increased by the NMOS transistor 7. ) Precharged to level. In addition, the two NMOS transistors 5 and 6 in which the channels are connected in series with each other are clampers designed to prevent the voltage level of the n1 node from being higher than the level of Vcc + 2Vth.

Therefore, for example, when the DB signal is input as a high level signal and the PITRST signal is enabled in a high state, the output signal of the first NAND gate 1 becomes a low level. At this time, the order may be interchanged. Accordingly, due to the coupling effect of the first capacitor 2, the voltage level of the n1 node becomes a voltage level for turning off the NMOS transistor 7. The voltage level of the n2 node is pumped to a voltage level approximately twice that of the previous internal power supply voltage (int. Vcc) level by the coupling effect of the third capacitor 15. The PMOS transistor 16, which is a switching transistor, is turned on by the low level output signal of the first NAND gate 1, and the pull-up transistor M1 is turned on from the high level data. Output to the outside. As described above, the conventional data output buffer as shown in FIG. 1 improves the operation speed and characteristics when high level data is output. When the DB signal is input as a low level signal, the output pull-up transistor M1 is turned off and the output pull-down transistor M2 is turned on to output low-level data to the outside of the chip.

The circuit of FIG. 1 has the following problems as the pull-up transistor M1 uses an EnMOS transistor. Since pumping is performed using a capacitor made of a MOS transistor, the junction may be broken due to a sudden increase in voltage. In addition, the circuit configuration is not only complicated, but the layout area occupied by the capacitor is much larger than that of other devices, which is disadvantageous for high integration. In a real process, the realization of one MOS transistor takes a lot of area, which is well known in the art. In addition, when the supply power supply voltage Vcc of the circuit of FIG. 1 is low Vcc, the boosting efficiency of the boosting circuit decreases, and the operation speed drops sharply.

Accordingly, an object of the present invention is to provide a data output buffer which is advantageous in high integration due to its compact circuit configuration.

Another object of the present invention is to provide a data output butter in which the output operation is stabilized.

Another object of the present invention is to provide a data output buffer in which the operation speed is increased even under a low power supply voltage.

The data output buffer of the present invention for achieving the object of the present invention comprises a level shifter for controlling the output pull-up transistor between the pull-up input stage and the output pull-up transistor, the output pull-up transistor as a PMOS transistor; Characterized in having a. In addition, the level conversion circuit uses an external power supply voltage (ext. Vcc) as a supply voltage, and raises the high level applied to the gate of the output pull-up transistor to the external power supply voltage (ext. Vcc).

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. A circuit of a data output buffer according to an embodiment of the present invention is shown in FIG. 3 shows a voltage waveform of the data output buffer of FIG. 2 according to the present invention as compared with the prior art.

First, the data output buffer of FIG. 2 according to the present invention uses an output pull-up transistor (MPU), unlike the prior art, using a PMOS transistor. By using such a PMOS transistor, there is no need to use a pumping circuit using a capacitor unlike in the related art. Accordingly, the circuit configuration is compact, which is advantageous for high integration.

Meanwhile, in the highly integrated semiconductor memory device, as the low power supply voltage is used, the internal power supply voltage int. Vcc is lower than the external power supply voltage ext. Vcc. Therefore, since the signal according to the internal power supply voltage (int. Vcc) is applied to the output pull-up transistor, when the output pull-up transistor (MPU) is used as the PMOS transistor as described above, the output pull-up transistor (MPU) is completely turned off. You won't be able to. That is, due to the difference between the internal power supply voltage (int. Vcc) and the external power supply voltage (ext. Vcc), the output pull-up transistor (MPU), which is a PMOS transistor, is not completely turned off, so that the DC current flows to the ground voltage terminal (Vss). Will flow. In order to prevent such a phenomenon, the present invention controls the output pull-up transistor (MPU) with an external power supply voltage (ext. Vcc) by additionally using the level converting circuit 100 as shown in FIG.

The configuration of the circuit of FIG. 2 showing an embodiment of the data output buffer according to the present invention as described above will be described. The first and second NAND gates 51 and 57 are controlled by a PITRST signal as a fall-up input terminal and a pull-down input terminal, respectively, and are input by a pair of data signals DB and DBB read out from a predetermined memory V, respectively. In this case, the data signals DB and DBB are signals according to the internal power supply voltage int. Vcc as described above. The output pull-up transistor (MPU) consisting of a PMOS transistor uses an external power supply voltage (ext. Vcc) as the source voltage. An output pull-down transistor MPD including an NMOS transistor is coupled to the output terminal of the second NAND gate 57 through an inverter 58 and is connected between the drain and the ground of the output pull-up transistor MPU. The level conversion circuit 100 is connected between the output terminal of the first NAND gate 51 and the gate of the output pull-up transistor (MPU). The level converting circuit 100 is composed of the NMOS transistors 52 and 54, the inverter 53, and the PMOS transistors 55 and 56. The level converting circuit 100 having such a configuration is known in the art. Since it is a well-known structure, detailed description is abbreviate | omitted.

The operation characteristic of the data output buffer of FIG. 2 according to the present invention will now be described.

First, when the data read out from the predetermined memory is at the high level, the DB signal is high and the DBB signal is low level. At this time, when the PITRST signal is input as a high level signal, the first NAND gate 51 outputs a low signal. As such, the low signal output from the first NAND gate 51 turns on the NMOS transistor 54 in the level converting circuit 100 so that the gate voltage level of the NO1 node, that is, the output pull-up transistor (MPU), is set to ground voltage (Vss). ) Descend to the level of OV. Accordingly, the output pull-up transistor (MPU) is turned on so that the output day (DOUT) is output at the external power supply voltage (ext. Vcc) level. The output of the second NAND gate 57 becomes high and is inverted by the inverter 58. Accordingly, the voltage level of the NO2 node, that is, the gate of the output pull-down transistor MPD becomes OV, and the output pull-down transistor MPD is turned off.

At this time, since the pull-up transistor (MPU) for outputting the internal power supply voltage (int. Vcc) and the external power supply voltage (ext.Vcc) is a PMOS transistor, the output pullup transistor even if the output data DOUT rises to the external power supply voltage (ext. Vcc) level. Since the V _GS (gate-to-source voltage) of the (MPU) always maintains the external power supply voltage (ext. Vcc), the current always maintains the saturation current because it operates in a saturation region.

Unlike the above, when the data read out from the predetermined memory cell is low, the DB signal is low and the DBB signal is high. At this time, when the PITRST signal is input as a high level signal, the first NAND gate 51 outputs a high signal. As such, the high signal output from the first NAND gate 51 turns on the NMOS transistor 52 in the level converting circuit 100 and raises it to the external power supply voltage (ext. Vcc) level of the NO1 node. Turn off the MPU). The output signal of the second NAND gate 57 is output low and the NO2 node is turned high, so the output pull-down transistor MPD is turned on and the output data DOUT is output at OV which is the ground voltage Vss level.

At this time, even if there is a voltage difference, the output pull-up transistor (MPU), which is a PMOS transistor, can be completely turned off by the level conversion circuit 100. Accordingly, DC current is prevented from flowing to the ground voltage terminal Vss.

Therefore, the data output buffer according to the present invention has a simple circuit configuration by using an output pull-up transistor (MPU) as a PMOS transistor, and speeds up the operation speed even under a low power supply voltage by using the level conversion circuit 100. .

This can be easily understood with reference to FIG. 3, which is a voltage waveform diagram of the data output buffer of FIG. 2 according to the present invention as compared with the prior art as shown in FIG. In FIG. 3, reference numerals DB and DBB denote data signals read out from the memory V, DOUT1 denotes a voltage waveform of the output data DOUT output from the data output buffer of FIG. 2 according to the present invention, and DOUT2 denotes the prior art. Voltage waveform of the output data (DOUT) output from the data output buffer. As shown in FIG. 3, the data output buffer according to the present invention has a voltage level of the output data DOUT even under an internal power supply voltage (int. Vcc) in which the voltage level is lower than the external power supply voltage (ext. Vcc). Not only is this output high, but also the operation speed is increased.

As described above, the present invention is not only advantageous for high integration due to its compact circuit configuration, but also for stable output operation and high speed of operation even under a low power supply voltage, and therefore, a semiconductor memory device using an internal power supply voltage in particular. Has the effect of improving performance.

Claims (1)

A data output buffer of a semiconductor memory device using a low power supply voltage lower than an external power supply voltage of a chip as an internal power supply voltage, the data output buffer being controlled by a signal that enables the output operation of the data output buffer and is controlled by a predetermined signal in the semiconductor memory device. An output pull-up comprising a pull-up input terminal 51 and a pull-down input terminal 57 for respectively inputting a pair of data signals corresponding to the internal power supply voltage read out from the memory V, and a PMOS transistor using the external power supply voltage as a source voltage; An output pull-down transistor (MPD) comprising a transistor (MPU), an gate coupled to the pull-down input terminal (57), and connected between a drain and the ground of the output pull-up transistor (MPU); and the pull-down input terminal ( 57 and a gate of the pull-down transistor MPD. A high level connected between the inverter 58 and the gate of the pull-up input terminal 51 and the output pull-up transistor (MPU) and applied to the gate of the output pull-up transistor (MPU) from the pull-up input terminal 51; And a level converting circuit (100) for raising the power supply voltage and applying a low level applied from the pull-up input terminal (51) to the gate of the output pull-up transistor (MPU) to a ground level. Used data output buffer.