JP6637564B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and is suitably used, for example, in a semiconductor device having an SRAM circuit (Static Random Access Memory).

  In order to reduce the leakage current of the SRAM circuit during standby, it is effective to set the potential of the ground wiring of the memory array to a potential higher than the ground potential (0 V) (a potential between the power supply potential and the ground potential). is there. As a result, the sub-threshold leakage current of the off-state MOS (Metal Oxide Semiconductor) transistor constituting the memory cell can be reduced.

  For example, in Japanese Unexamined Patent Application Publication No. 2004-206745 (Patent Document 1), the potential of the ground wiring during standby is controlled to about 0.4 V by providing a potential control circuit that controls the potential of the ground wiring. Specifically, the potential control circuit includes a switch for fixing the potential of the ground wiring to the ground potential during operation, a diode-connected NMOS (N-channel MOS) transistor for determining the potential of the ground wiring during standby, and It is composed of three elements of a resistor that always flows current.

JP 2004-206745 A

  In the case of a MOS transistor manufactured by a conventional process, the leakage current of a PMOS (P-channel MOS) transistor is smaller than that of an NMOS transistor. For this reason, the leakage current of the SRAM circuit has only to be considered in consideration of the leakage current of the NMOS transistor forming the memory cell.

  However, in recent processes, since the performance of the PMOS transistor has been improved, the leakage current of the PMOS transistor may raise the potential of the ground wiring during standby more than expected. In particular, in the latest process using a finFET (fin Field Effect Transistor), the above problem is serious because the global variation is larger than before. Specifically, when the NMOS transistor has a characteristic at a Slow corner where the drain current becomes small and the PMOS transistor has a characteristic at a Fast corner where the drain current becomes large, the rise of the potential of the ground wiring during standby is particularly large. Therefore, data held in each memory cell of the SRAM circuit may be destroyed.

  Other problems and novel features will be apparent from the description of this specification and the accompanying drawings.

  In the semiconductor device according to one embodiment, the SRAM circuit includes a ground wiring potential control circuit for controlling the potential of the ground wiring for the memory array according to an operation mode. The ground line potential control circuit includes an NMOS transistor and a PMOS transistor connected in parallel between a ground line and a ground node for providing a ground potential.

  According to the above embodiment, it is possible to prevent the potential of the ground wiring from excessively rising when the SRAM circuit is in the standby state.

FIG. 1 is a plan view schematically showing a microcomputer configured as a system-on-chip as an example of a semiconductor device according to a first embodiment. FIG. 2 is a block diagram schematically illustrating a configuration of the SRAM circuit in FIG. 1. FIG. 3 is a circuit diagram showing a more detailed configuration of a memory cell MC and a ground line potential control circuit 16 of FIG. FIG. 3 is a circuit diagram illustrating an example of a configuration of an operation mode control circuit 20 of FIG. 2. 4 is a timing chart illustrating an operation of the operation mode control circuit 20. It is a circuit diagram of the modification of FIG. FIG. 3 is a plan view for explaining an arrangement of N wells in a cell. FIG. 3 is a plan view schematically showing a layout of the SRAM circuit in FIG. 2. FIG. 3 is a plan view showing a more detailed arrangement of a ground wiring potential control circuit in the SRAM circuit of FIG. 2. FIG. 10 is a diagram for explaining another arrangement example of the ground line potential control circuit. FIG. 11 is a plan view schematically showing a layout of the SRAM circuit of FIG. 10. FIG. 11 is a plan view showing a more detailed arrangement of the ground wiring potential control circuit of FIG. 10. FIG. 13 is a block diagram schematically illustrating a configuration of an SRAM circuit in the semiconductor device according to the third embodiment. FIG. 14 is a plan view schematically showing a layout of the SRAM circuit in FIG. 13. FIG. 14 is a plan view showing a more detailed arrangement of a power supply wiring potential control circuit in the SRAM circuit of FIG. 13. FIG. 16 is a plan view schematically showing the structure of the PMOS transistor of FIG. 15 formed using a finFET. FIG. 16 is a perspective view schematically showing a structure of the PMOS transistor of FIG. 15 formed using a finFET. It is sectional drawing which shows typically the structure of the NMOS transistor formed of finFET. It is sectional drawing which shows typically the structure of the PMOS transistor formed by finFET. FIG. 2 is a plan view schematically showing a layout of an entire dual-port SRAM circuit. FIG. 21 is a diagram showing a more detailed configuration of the SRAM circuit of FIG. 20.

  Hereinafter, each embodiment will be described in detail with reference to the drawings. The same or corresponding parts have the same reference characters allotted, and description thereof will not be repeated.

<First embodiment>
[Configuration Example of Semiconductor Device]
FIG. 1 is a plan view schematically showing a microcomputer configured as a system-on-chip as an example of the semiconductor device according to the first embodiment. Referring to FIG. 1, a microcomputer chip includes a CPU (Central Processing Unit) 101, a digital logic circuit 102, an SRAM circuit 10, a flash memory 104, and an analog circuit 103 formed on a semiconductor substrate 100. , An input / output (I / O) circuit 105.

  Digital logic circuit 102 includes, for example, a peripheral logic circuit of CPU 101 and a dedicated signal processing circuit. The SRAM circuit 10 is used as a built-in RAM (Random Access Memory), and the flash memory 104 is used as a built-in ROM (Read Only Memory). The analog circuit 103 includes, for example, an A / D (Analog to Digital) converter, a D / A (Digital to Analog) converter, and the like. The input / output circuit 105 is an interface for inputting and outputting signals to and from the outside.

  The SRAM circuit 10 has, as operation modes, a normal operation (Normal Operation: NOP) mode, a resume standby (Resume Standby: RS) mode, and a shutdown (SD) mode. The normal operation mode is an operation mode for performing data reading and data writing. The resume standby mode is an operation mode in which power consumption is reduced while holding written data. The shutdown mode is an operation mode in which the function is stopped without holding the written data. Hereinafter, the resume standby mode may be simply described as the standby mode.

[Configuration of SRAM circuit]
FIG. 2 is a block diagram schematically showing the configuration of the SRAM circuit of FIG. Referring to FIG. 1, an SRAM circuit 10 includes a memory array 11, a plurality of word lines WL, a plurality of bit line pairs BL and / BL, a plurality of word line drivers 12, and a plurality of inputs / outputs (I / O) A circuit 13 and a control circuit & address decoder 14 are included. The SRAM circuit 10 further includes a ground wiring ARVSS, a power supply wiring ARVDD (not shown), a plurality of ground wiring potential control circuits 16, and an operation mode control circuit 20.

  Memory array 11 includes a plurality of memory cells MC arranged in a matrix. In FIG. 2, the memory cell MC at the i-th row and j-th column (0 ≦ i ≦ m; 0 ≦ j ≦ n) is described as MC [i, j]. The memory array 11 includes (m + 1) × (n + 1) memory cells in m + 1 rows and n + 1 columns in total. FIG. 2 typically shows memory cells MC [0,0] to MC [1,3] in two rows and four columns.

  Word lines WL extending in the row direction (X direction) are provided corresponding to the respective rows of memory array 11, and bit line pairs extending in the column direction (Y direction) corresponding to the columns of memory array 11, respectively. BL, / BL are provided. Each word line WL is connected to a memory cell MC provided in a corresponding row. Each bit line pair BL, / BL is connected to each memory cell MC provided in the corresponding column.

  The word line driver 12 is provided corresponding to each of the plurality of word lines WL. Each word line driver 12 activates a word line WL of a corresponding row when a corresponding row is selected in accordance with a decoding result of an address signal given from outside of the SRAM circuit 10 (that is, the logic level of the corresponding row is changed). A high level (H level) voltage is applied).

  One I / O circuit 13 is provided for each of a plurality of columns. FIG. 2 shows the configuration of MUX2 (multiplex 2) provided one for every two columns. Unlike the configuration of FIG. 2, a configuration such as MUX4 provided one for every four columns or MUX8 provided one for every eight columns may be used. The I / O circuit 13 receives write data from outside the SRAM circuit 10 and writes data to a selected memory cell MC in a corresponding column. Further, I / O circuit 13 reads data from the selected memory cell MC in the corresponding column, and outputs the read data to the outside of SRAM circuit 10.

  The control circuit & address decoder 14 controls the timing of data writing and data reading in the I / O circuit 13 in accordance with externally applied commands (write command, read command). Further, control circuit & address decoder 14 decodes an address signal given from outside SRAM circuit 10, and controls word line driver 12 and I / O circuit 13 corresponding to the row and column selected based on the decoding result. Drive.

  The ground wiring ARVSS is wired in a mesh shape in the memory array 11, and is connected to each memory cell MC. In the normal operation mode, a ground potential (0 V) is supplied to each memory cell MC via the ground wiring ARVSS. In the memory array 11, a power supply wiring ARVDD (not shown) wired in a mesh shape is also provided to supply a power supply potential to each memory cell MC.

  The ground wiring potential control circuit 16 is arranged for each I / O circuit 13 in the example of FIG. The ground wiring potential control circuit 16 controls the potential of the ground wiring ARVSS to be a predetermined potential according to the operation mode. Specifically, in the normal operation mode, the ground wiring potential control circuit 16 controls the potential of the ground wiring ARVSS to be the ground potential, and in the resume standby mode, the potential of the ground wiring ARVSS is set between the ground potential and the power supply potential. It is controlled so as to have an intermediate potential between them. Further, the ground wiring potential control circuit 16 sets the ground wiring ARVSS to a floating state in the shutdown mode.

  The operation mode control circuit 20 controls the operation of each ground line potential control circuit 16 according to a signal indicating the operation mode given from the control circuit & address decoder 14.

[Configuration of Memory Cell and Ground Wiring Potential Control Circuit]
FIG. 3 is a circuit diagram showing a more detailed configuration of memory cell MC and ground line potential control circuit 16 in FIG.

(Memory cell MC)
Referring to FIG. 3, each memory cell MC includes a latch circuit including two complementary MOS (CMOS) inverters and two transfer NMOS transistors NM1 and NM2.

  The first CMOS inverter forming the latch circuit includes a PMOS transistor PM1 and an NMOS transistor NM3 connected in series between a power supply wiring ARVDD and a ground wiring ARVSS. The second CMOS inverter forming the latch circuit includes a PMOS transistor PM2 and an NMOS transistor NM4 connected in series between a power supply wiring ARVDD and a ground wiring ARVSS. The connection node ND1 between the PMOS transistor PM1 and the NMOS transistor NM3 is connected to the gates of the PMOS transistor PM2 and the NMOS transistor NM4. The connection node ND1 between the PMOS transistor PM2 and the NMOS transistor NM4 is connected to the gates of the PMOS transistor PM1 and the NMOS transistor NM3.

  The transfer NMOS transistor NM1 is connected between the connection node ND1 and the bit line BL. The transfer NMOS transistor NM2 is connected between the connection node ND2 and the bit line / BL. The gates of the NMOS transistors NM1 and NM2 are connected to a common word line WL.

  Each memory cell MC holds a potential complementary to the connection nodes ND1 and ND2 (a potential at which one is at an H level and the other is at an L level (low level)). Hereinafter, the procedure of the write operation will be briefly described. For example, when the connection node ND1 holds a high-level voltage and the connection node ND2 holds a low-level (L-level) voltage, first, the potential of the bit line BL is set to the H level, and the bit line / BL Is set to L level. Next, by maintaining the state in which the potential of the word line WL is changed from L level to H level for a predetermined time, the potential of the connection node ND1 changes to H level and the potential of the connection node ND2 changes to L level. .

  Next, the procedure of the read operation will be briefly described. It is assumed that the potential of connection node ND1 is preset to H level, and the potential of connection node ND2 is preset to L level. First, the bit line pair BL, / BL is precharged to the power supply potential. Thereafter, when the word line WL is changed from the L level to the H level, the potential of the bit line BL connected to the connection node ND1 holding the H level voltage does not change, but the L level voltage is changed. The held potential of the bit line / BL connected to the connection node ND2 decreases. The data held in the memory cell MC can be read by amplifying the potential difference between the bit lines BL and / BL by a sense amplifier (not shown) provided in the I / O circuit 13.

(Ground wiring potential control circuit 16)
The ground wiring potential control circuit 16 includes an NMOS transistor NM10 and a PMOS transistor PM10 connected in parallel between the ground wiring ARVSS and a ground node VSS for providing a ground potential. That is, the NMOS transistor NM10 has a common source, while the PMOS transistor PM10 has a common drain (source follower). Further, the gate of the NMOS transistor NM10 is connected to the ground wiring ARVSS via the NMOS transistor NM11 provided in the operation mode control circuit 20. The operation mode control circuit 20 sets the gates of the NMOS transistors NM10 and NM11 and the gate of the PMOS transistor PM10 to a potential according to the operation mode.

  Specifically, in the resume standby (RS) mode, the gate potential of the NMOS transistor NM11 is set to the H level (power supply potential), so that the NMOS transistor NM10 is in a diode-connected state. Further, the PMOS transistor PM10 is turned on by setting the gate potential of the PMOS transistor PM10 to L level (ground potential).

  According to the above configuration, the potential of the ground wiring ARVSS rises from the ground potential to a certain potential due to the diode connection of the NMOS transistor NM10. As the leakage current of the PMOS transistor forming the memory cell MC increases, the floating of the ground wiring ARVSS increases. On the other hand, the current is extracted from the ground wiring ARVSS through the PMOS transistor PM10, so that the potential of the ground wiring ARVSS decreases. As a result of these balances, the final potential of the ground wiring ARVSS is determined.

  When the NMOS transistor has the characteristic at the Slow corner and the PMOS transistor has the characteristic at the Fast corner due to global variation, the grounding caused by the leakage current of the PMOS transistor constituting the memory cell is achieved only with the NMOS transistor NM10. Excessive floating of the potential of the wiring ARVSS cannot be suppressed. In the configuration of FIG. 3, an excessive floating of the potential of the ground wiring ARVSS in the standby mode can be prevented by extracting charges from the ground wiring ARVSS via the PMOS transistor PM10.

  On the other hand, in the normal operation mode (NOP mode), the operation mode control circuit 20 turns off the NMOS transistor NM11 by setting the gate potential of the NMOS transistor NM11 to L level, and sets the gate potential of the NMOS transistor NM10 to H level. By setting the level, the NMOS transistor NM10 is turned on. Further, the PMOS transistor PM10 is turned on by setting the gate potential of the PMOS transistor PM10 to L level. Thus, the potential of the ground wiring ARVSS is maintained at the ground potential.

  In the shutdown mode (SD mode), the operation mode control circuit 20 turns off the NMOS transistors NM10 and NM11 by setting the gate potentials of the NMOS transistors NM10 and NM11 to L level. Further, the operation mode control circuit 20 turns off the PMOS transistor PM10 by setting the gate potential of the PMOS transistor PM10 to the H level. As a result, the ground wiring ARVSS enters a floating state.

[Configuration Example of Operation Mode Control Circuit 20]
FIG. 4 is a circuit diagram showing an example of the configuration of the operation mode control circuit 20 of FIG. FIG. 4 shows only a portion corresponding to one I / O circuit 13 in the SRAM circuit 10 of FIG. Hereinafter, two columns corresponding to one I / O circuit 13 in the memory array 11 may be referred to as a memory cell group 17. One ground wiring potential control circuit 16 is provided for each I / O circuit 13.

  Referring to FIG. 4, the gate of NMOS transistor NM10 forming ground line potential control circuit 16 is connected to a common control line ARYSWN in each ground line potential control circuit 16. The source of the NMOS transistor NM10 is connected to the ground node VSS, and the drain is connected to the ground wiring ARVSS. The back gate of the NMOS transistor NM10 is connected to the ground node VSS.

  The gate of the PMOS transistor PM10 constituting each ground wiring potential control circuit 16 is connected to a common control line ARYSWP in each ground wiring potential control circuit 16. The source of the PMOS transistor PM10 is connected to the ground wiring ARVSS, and the drain is connected to the ground node VSS. The back gate of the PMOS transistor PM10 is connected to a power supply node VDD for providing a power supply potential.

  The operation mode control circuit 20 outputs a control signal to the control lines ARYSWN, ARYSWP based on the control signals RS, SD received from the control circuit & address decoder 14 of FIG. Specifically, the operation mode control circuit 20 includes a PMOS transistor PM11 as a switch, NMOS transistors NM11 and NM12 as switches, inverters 23, 24, 25, a NAND gate 21, and a NOR gate 22.

  The PMOS transistor PM11 and the NMOS transistor NM12 are connected in series in this order between the power supply node VDD and the ground node VSS. The NMOS transistor NM11 is connected between a connection node ND3 of the PMOS transistor PM11 and the NMOS transistor NM12 and the ground wiring ARVSS.

  A control signal SD is input to a first input terminal of the NAND gate 21 and a first input terminal of the NOR gate 22. The control signal RS is input to the second input terminal of the NAND gate 21 via the inverters 23 and 24 (therefore, a signal having the same logic level as the control signal RS). A control signal RS is input to a second input terminal of the NOR gate 22 via the inverter 23.

  The control signal RS is input to the gate of the PMOS transistor PM11 via the inverters 23 and 24 (accordingly, a signal of the same logic level as the control signal RS). The output signal of the NAND gate 21 is input to the gate of the NMOS transistor NM12 and the control line ARYSWP after being inverted by the inverter 25. The control line ARYSWN is connected to a connection node ND3 of the PMOS transistor PM11 and the NMOS transistor NM12. The output signal of the NOR gate 22 is input to the gate of the NMOS transistor NM11.

[Operation of Operation Mode Control Circuit 20]
FIG. 5 is a timing chart showing the operation of the operation mode control circuit 20. Hereinafter, the operation of the operation mode control circuit will be described with reference to FIGS.

  The normal operation (NOP) mode corresponds to before time t1, from time t2 to time t3, and after time t4 in FIG. In the normal operation (NOP) mode, the control signals RS and SD are both at the L level. In this case, since the gate potential of the NMOS transistor NM11 is set to L level, the NMOS transistor NM11 is turned off. Since the gate potential of the PMOS transistor PM11 is set to the L level, the PMOS transistor PM11 is turned on. Since the gate potential of the NMOS transistor NM12 is set to L level, the NMOS transistor NM12 is turned off. As a result, the potential of the control line ARYSWN is set to the H level, and the NMOS transistor NM10 provided in each ground line potential control circuit 16 is turned on. Further, since the potential of the control line ARYSWP is set to the L level, the PMOS transistor PM10 provided in each ground line potential control circuit 16 is turned on. As described above, in the normal operation (NOP) mode, the potential of the ground wiring ARVSS becomes substantially equal to the ground potential.

  The resume standby (RS) mode corresponds to a period from time t1 to time t2 in FIG. In the resume standby (RS) mode, the control signal RS goes high and the control signal SD goes low. In this case, since the gate potential of the NMOS transistor NM11 is set to the H level, the NMOS transistor NM11 is turned on. Further, the gate potential of the PMOS transistor PM11 is set to H level, and the gate potential of the NMOS transistor NM12 is set to L level, so that these transistors PM11 and NM12 are turned off. As described above, in the resume standby (RS) mode, the connection node ND3 and the control line ARYSWN are connected to the ground wiring ARVSS without being connected to either the power supply node VDD or the ground node VSS. As a result, the NMOS transistor NM10 is in a diode-connected state. Further, in the resume standby (RS) mode, the potential of the control line ARYSWP is set to L level, so that the PMOS transistor PM10 is turned on.

  According to the above configuration, the potential of the ground wiring ARVSS rises from the ground potential to a certain potential due to the diode connection of the NMOS transistor NM10. On the other hand, since the electric charge of the ground wiring ARVSS is extracted via the PMOS transistor PM10, the potential of the ground wiring ARVSS decreases and settles to the final potential ΔV1 of the ground wiring ARVSS.

  The shutdown (SD) mode corresponds to a period from time t3 to time t4 in FIG. In the shutdown (SD) mode, both the control signals RS and SD go to H level. In this case, since the gate potential of the NMOS transistor NM11 is set to L level, the NMOS transistor NM11 is turned off. Since the gate potential of the PMOS transistor PM11 is set to the H level, the PMOS transistor PM11 is turned off. Since the gate potential of the NMOS transistor NM12 is set to the H level, the NMOS transistor NM12 is turned on. As a result, the potential of the control line ARYSWN is set to L level, so that the NMOS transistor NM10 provided in each ground line potential control circuit 16 is turned off. Further, since the potential of the control line ARYSWP is set to the H level, the PMOS transistor PM10 is turned off. As described above, in the resume standby (RS) mode, the ground wiring ARVSS is in a floating state.

[Modified Example of Ground Wiring Potential Control Circuit and Operation Mode Control Circuit]
When the operation mode of the SRAM circuit has only the normal operation mode and the resume standby mode and does not have the shutdown mode, the configurations of the ground line potential control circuit 16 and the operation mode control circuit 20 of FIG. 4 are simplified. be able to. Hereinafter, a specific description will be given with reference to the drawings.

  FIG. 6 is a circuit diagram of a modified example of FIG. The ground line potential control circuit 16A of FIG. 6 differs from the ground line potential control circuit 16 of FIG. 4 in that the gate of the PMOS transistor PM10 is always connected to the ground node VSS (and is therefore always in the ON state). And different. Specifically, the source of the PMOS transistor PM10 is connected to the ground wiring ARVSS, and its drain and gate are connected to the ground node VSS. The back gate of the PMOS transistor PM10 is connected to the power supply node VDD. In the case of FIG. 6, the control line ARYSWP is not provided. The connection of NMOS transistor NM10 is the same as that of FIG. 4, and therefore description will not be repeated.

  The operation mode control circuit 20A shown in FIG. 6 is connected to a control line commonly connected to the gate of the NMOS transistor NM10 of each ground line potential control circuit 16A based on the control signal RS received from the control circuit & address decoder 14 shown in FIG. The potential of ARYSWN is controlled. Specifically, the operation mode control circuit 20A includes an NMOS transistor NM11 as a switch and a PMOS transistor PM11 as a switch.

  The NMOS transistor NM11 is connected between the ground wiring ARVSS and the control line ARYSWN. The PMOS transistor PM11 is connected between the power supply node VDD and the control line ARYSWN. The control signal RS is input to the gates of the NMOS transistor NM11 and the PMOS transistor PM11.

  In the normal operation (NOP) mode, the control signal RS is at the L level. In this case, the NMOS transistor NM11 is turned off and the PMOS transistor PM11 is turned on, so that the potential of the control line ARYSWN is set to the H level (power supply potential). Therefore, the NMOS transistor NM10 is turned on, and the potential of the ground wiring ARVSS is lowered to the ground potential together with the PMOS transistor PM10 in the on state.

  In the resume standby (RS) mode, the control signal RS is at the H level. In this case, the NMOS transistor NM11 is turned on and the PMOS transistor PM11 is turned off, so that the NMOS transistor NM10 is diode-connected. Therefore, although the potential of the ground wiring ARVSS is higher than the ground potential, the charge of the ground wiring ARVSS is drawn out by the drain-grounded PMOS transistor PM11 in the ON state, so that excessive floating of the potential of the ground wiring ARVSS is suppressed. it can.

[Effect of First Embodiment]
As described above, according to the first embodiment, the NMOS transistor NM10 and the PMOS transistor PM10 are provided between the ground wiring ARVSS connected to each memory cell MC of the SRAM circuit and the ground node VSS for providing the ground potential. Provided in parallel. In the resume standby mode, the gate of the NMOS transistor NM10 is connected to the ground wiring ARVSS, so that the NMOS transistor NM10 is in a diode-connected state. When an L-level signal is applied to the gate of the PMOS transistor PM10, the PMNOS transistor PM10 is turned on.

  With the above configuration, in the resume standby mode, the potential of the ground wiring ARVSS is raised to a level that does not destroy the data held in the memory cell MC and that can reduce the leak current of the memory cell. Can be. In particular, due to global variation, even when the NMOS transistor has the characteristic at the Slow corner and the PMOS transistor has the characteristic at the Fast corner, from the ground wiring ARVSS via the PMOS transistor PM10 having the characteristic at the Fast corner. Since the current can be extracted, excessive floating of the potential of the ground wiring ARVSS can be prevented.

  In particular, in the latest process using the finFET, the performance of the PMOS transistor is improved more than before and the global variation is larger than before, so that the potential of the ground wiring ARVSS at the time of resume standby tends to rise excessively. is there. The above configuration is particularly useful when a MOS transistor is formed using a finFET.

<Second embodiment>
In the second embodiment, an arrangement of the ground wiring potential control circuit 16 described in FIGS. 2 and 4 on a semiconductor substrate will be described. Hereinafter, first, a desirable arrangement of the P well and the N well in the cell will be described.

[Arrangement of N-well and P-well in cell]
Generally, a power supply potential is supplied to the N well and a ground potential is supplied to the P well. In the case of a cell-based IC (Integrated Circuit), there is no problem even if N wells of a plurality of cells using the same power supply voltage are brought into contact with each other. However, N wells of a plurality of cells using different power supply voltages (for example, a standard cell and an IO cell) cannot be brought into contact with each other. In this case, it is necessary to further increase the interval between the N wells. For the above reasons, the arrangement of the N-well in the cell is restricted.

  FIG. 7 is a plan view for explaining the arrangement of N wells in a cell. Referring to FIG. 7, N well 31 is desirably arranged at a distance a or b from frame 32A or 32B of cell 30, respectively. This is to satisfy the design rule no matter what kind of cell is arranged next to the cell 30. Therefore, it is desirable to dispose a P well in a region adjacent to the cell frame 32. This is because, if an N well is arranged in a region close to the cell frame 32, it is necessary to further increase the interval between adjacent cells. Also in the case of the SRAM circuit described below, it is desirable that the end of the layout region of the SRAM circuit be a P-well as much as possible.

[Example of arrangement of ground wiring potential control circuit]
FIG. 8 is a plan view schematically showing a layout of the SRAM circuit of FIG. FIG. 9 is a plan view showing a more detailed arrangement of the ground wiring potential control circuit in the SRAM circuit of FIG. Hereinafter, the row direction of the memory array 11 is referred to as an X direction, and the column direction is referred to as a Y direction. Furthermore, when distinguishing the directions along the X direction, they are denoted by reference numerals such as the + X direction and the −X direction. The same applies to the Y direction.

  Referring to FIGS. 8 and 9, when the substrate on which SRAM circuit 10 is formed is viewed in a plan view, I / O circuit 13 corresponds to a corresponding portion of memory array 11 (that is, via bit line pair BL, / BL). Are arranged on the column direction side (the −Y direction side) with respect to the portion connected by the connection. Ground line potential control circuit 16 is arranged between memory array 11 and I / O circuit 13.

  An NMOS transistor NM13 is provided on the opposite side of the memory array 11 from the ground line potential control circuit 16. The NMOS transistor NM13 is provided, for example, for each ground line potential control circuit 16 (accordingly, for each I / O circuit 13). The drain of the NMOS transistor NM13 is connected to the ground wiring ARVSS, and the source is connected to the ground node VSS. The gate of the NMOS transistor NM13 is connected to a common control line ARYSWN2 for each NMOS transistor NM13.

  The NMOS transistor NM13 is provided to ensure that the ground wiring ARVSS is substantially equal to the ground potential VSS in the normal operation mode. Specifically, a control signal is supplied to the control line ARYSWN2 from the operation mode control circuit 20 in FIG. In the normal operation (NOP) mode, the potential of the control line ARYSWN2 is set to the H level, so that each NMOS transistor NM13 is turned on. This ensures that the potential of the ground wiring ARVSS for the memory array 11 drops to the ground potential. In the resume standby (RS) mode and the shutdown (SD) mode, the potential of the control line ARYSWN2 is set to a low level, so that each NMOS transistor NM13 is turned off.

  The region where the NMOS transistor NM13 is arranged is a P-well (PWELL) region 70. Therefore, the terminal on the + Y direction side of the SRAM circuit macro can be a P well, so that an area efficient arrangement can be achieved.

  On the other hand, the NMOS transistor NM10 forming the ground line potential control circuit 16 is formed in the P well region 71 extending in the X direction adjacent to the region where the memory array 11 is arranged. The PMOS transistor PM10 constituting the ground line potential control circuit 16 is arranged in an N-well (NWELL) region 72 adjacent to the P-well region 71 on the side opposite to the memory array 11 (−Y direction side).

  By arranging the ground line potential control circuit 16 as described above, the N well region 72 in which the PMOS transistor PM10 is arranged can be shared with the precharge circuit CPC provided in the I / O circuit 13. Area saving can be achieved. As shown in FIG. 9, the precharge circuit CPC includes PMOS transistors PM20, PM21, PM22. The PMOS transistor PM20 is connected between the first and second bit lines BL and / BL forming a bit line pair. The PMOS transistor PM21 is connected between the power supply node VDD and the first bit line BL. PMOS transistor PM22 is connected between power supply node VDD and second bit line / BL. A common control signal is input to the gates of these PMOS transistors PM20, PM21, PM22.

[Other arrangement examples of the ground wiring potential control circuit]
FIG. 10 is a diagram for explaining another arrangement example of the ground line potential control circuit. The layout of the SRAM circuit 10A shown in FIG. 10 is a modification of the layout of the SRAM circuit 10 of FIG.

  Specifically, when there is no space for arranging the operation mode control circuit 20 between the arrangement area of the word line driver 12 and the control circuit & address decoder 14, the operation mode control circuits 20 are compared as shown in FIG. The word line driver 12 can be arranged at the end on the + Y direction side of the word line driver 12 having a sufficient target space. In this case, the ground line potential control circuit 16 is also arranged on the + Y direction side with respect to the memory array 11, that is, on the opposite side of the memory array 11 from the I / O circuit 13.

  FIG. 11 is a plan view schematically showing a layout of the SRAM circuit of FIG. FIG. 12 is a plan view showing a more detailed arrangement of the ground wiring potential control circuit of FIG. Referring to FIGS. 11 and 12, ground line potential control circuit 16 is arranged on the opposite side of I / O circuit 13 with memory array 11 interposed therebetween. The PMOS transistor PM10 constituting the ground line potential control circuit 16 is formed in an N well region 74 extending in the X direction adjacent to the arrangement region of the memory array 11. The NMOS transistor NM10 forming the ground line potential control circuit 16 is arranged in the P well region 73 adjacent to the N well region 74 on the opposite side (+ Y direction side) from the memory array 11. Therefore, the terminal on the + Y direction side of the SRAM circuit macro can be a P well, so that an area efficient arrangement can be achieved.

  Further, as described with reference to FIG. 9, the SRAM circuit 10A has the NMOS transistor NM13 on the side opposite to the ground line potential control circuit 16 with the memory array 11 interposed therebetween, that is, between the memory array 11 and the I / O circuit. Is provided. The drain of the NMOS transistor NM13 is connected to the ground wiring ARVSS, and the source is connected to the ground node VSS. The gate of the NMOS transistor NM13 is connected to a common control line ARYSWN2. The NMOS transistor NM13 is controlled so as to be turned on in the normal operation (NOP) mode, thereby reliably lowering the potential of the ground wiring ARVSS to the ground potential.

  As shown in FIG. 12, the NMOS transistor NM13 is provided in a P well region 75 extending in the X direction adjacent to the arrangement region of the memory array 11. The precharge circuit CPC provided in the I / O circuit 13 is arranged in the N-well region 76 adjacent to the P-well region 75 on the side opposite to the memory array 11 (−Y direction side).

[Effect of Second Embodiment]
According to the second embodiment, in addition to the same effects as those of the first embodiment, a circuit arrangement with good area efficiency becomes possible, so that the area can be saved.

<Third embodiment>
[Configuration of SRAM circuit]
FIG. 13 is a block diagram schematically illustrating a configuration of an SRAM circuit in the semiconductor device according to the third embodiment. The SRAM circuit 10B of FIG. 13 differs from the SRAM circuit 10 of FIG. 2 in that the SRAM circuit 10B of FIG. 13 further includes a power supply wiring potential control circuit 50 for controlling the potential of the power supply wiring ARVDD for the memory array. The power supply wiring potential control circuit 50 is arranged for each I / O circuit 13.

  Specifically, as shown in FIG. 13, the power supply wiring ARVDD is wired in a mesh shape in the memory array 11, and is connected to each memory cell MC. Although different from the layout of FIG. 13, the power supply wiring ARVDD may be independently wired for each I / O circuit 13. The power supply wiring potential control circuit 50 applies a power supply potential to the power supply wiring ARVDD by connecting the power supply wiring ARVDD and the power supply node VDD in the normal operation mode and the resume standby mode. In the shutdown mode, the power supply wiring potential control circuit 50 puts the power supply wiring ARVDD into a floating state by disconnecting the power supply wiring ARVDD from the power supply node VDD. The operation of the power supply wiring potential control circuit 50 is controlled by a control signal from the operation mode control circuit 20.

  Since the other points in FIG. 13 are the same as those in FIG. 2, the same or corresponding portions are denoted by the same reference characters, and description thereof will not be repeated.

  FIG. 14 is a plan view schematically showing a layout of the SRAM circuit of FIG. 13 on a substrate. FIG. 15 is a plan view showing a more detailed arrangement of a power supply wiring potential control circuit in the SRAM circuit of FIG. FIG. 15 shows only a portion corresponding to one I / O circuit 13 in the SRAM circuit 10B of FIG. The ground wiring potential control circuit 16 and the power supply wiring potential control circuit 50 are arranged one for each I / O circuit 13.

  As described with reference to FIG. 9, the NMOS transistor NM10 forming the ground line potential control circuit 16 is formed in the P well region 71 extending in the X direction adjacent to the region where the memory array 11 is arranged. The PMOS transistor PM10 forming the ground line potential control circuit 16 is arranged in the N-well region 72 adjacent to the P-well region 71 on the side opposite to the memory array 11 (−Y direction side).

  Power supply wiring potential control circuit 50 includes a PMOS transistor PM12 connected between power supply node VDD and power supply wiring ARVDD of memory array 11 (memory cell group 17). The PMOS transistor PM12 is arranged in the same N well region 72 as the PMOS transistor PM10 forming the ground line potential control circuit 16. The gate of the PMOS transistor PM12 is connected to a common control line ARYSWP with the gate of the PMOS transistor PM10. As a result, both the PMOS transistors PM10 and PM12 are turned on in the normal operation mode and the resume standby mode, and are turned off in the shutdown mode.

  The other points in FIG. 15 are the same as those in FIG. 9, and the same or corresponding parts are denoted by the same reference characters and description thereof will not be repeated.

[Configuration example using finFET]
Hereinafter, a configuration example of the PMOS transistors PM10 and PM12 using the finFET will be described.

  FIG. 16 is a plan view schematically showing the structure of the PMOS transistor of FIG. 15 formed using finFET. FIG. 17 is a perspective view schematically showing the structure of the PMOS transistor of FIG. 15 formed using finFET. The end faces in the x direction and the y direction in FIG. 17 indicate cut surfaces.

  Referring to FIGS. 16 and 17, a plurality of fins (fin) are formed on a silicon substrate (Si). The fin is used as a channel of the MOS transistor. The number of fins is determined according to the required drain current. The surface of the Si substrate other than the fins is covered with an oxide film (MO) for interlayer insulation. A gate is formed of polysilicon (PO) so as to straddle a plurality of fins (fin). A gate oxide film is previously formed between the gate and the fin. The gate is connected to the upper metal wiring layer (M0_PO). Further, a metal wiring for a drain and a metal wiring for a source (M0_OD) are formed by straddling a plurality of fins on both sides of the gate.

  As described above, in the PMOS transistor PM10 forming the ground wiring potential control circuit 16 and the PMOS transistor PM12 forming the power supply wiring potential control circuit 50, each of the gate, source wiring, and drain wiring is shared. There is an advantage that it can be formed with a single wiring, and the area can be reduced.

  FIG. 18 is a cross-sectional view schematically showing a configuration of an NMOS transistor formed of a finFET. Referring to FIG. 18, the NMOS transistor is formed in a P-well (Pwell) region formed on a P-type substrate (Psub). N-type (n +) impurity regions (source and drain regions) are formed in the P well. Fins are formed on a P-well to connect these impurity regions. A gate is formed of polysilicon (PO) with a gate oxide film interposed so as to straddle a fin between the source region and the drain region. A metal wiring layer (M0_PO) is formed above the gate. A source metal wiring layer and a drain metal wiring layer (M0_OD) are formed above the source region and the drain region (n +). On the upper portions of the gate metal wiring layer (M0_PO) and the source and drain metal wiring layers (M0_OD), vias (via0, via1, via2,. M3,...) Are sequentially formed. Furthermore, it is also possible to use a method of increasing drain current by applying strained silicon using silicon germanium or the like to a fin portion.

  FIG. 19 is a cross-sectional view schematically showing a configuration of a PMOS transistor formed of a finFET. Referring to FIG. 19, a PMOS transistor is formed in an N-well region formed on a P-type substrate (Psub). Further, a P-type (p +) impurity region (source region and drain region) is formed in the N well. The fin (fin) is formed on the N-well so as to connect these impurity regions.

  Since the configuration of the PMOS transistor in FIG. 19 other than the above is the same as the configuration of the NMOS transistor in FIG. 18, the same or corresponding portions are denoted by the same reference characters and description thereof will not be repeated.

[Effects of Third Embodiment]
According to the third embodiment, substantially the same effects as those of the first and second embodiments can be obtained. Further, according to the third embodiment, the gate of the PMOS transistor PM12 provided for switching the potential of the power supply wiring of the memory array is connected to the gate control line common to the PMOS transistor PM10 constituting the ground wiring potential control circuit 16. Since it can be connected to ARYSWP, it is advantageous in area.

<Fourth embodiment>
In the fourth embodiment, the ground wiring potential control circuit 16 of the first and second embodiments and the power supply wiring potential of the third embodiment are applied to a dual-port SRAM circuit having two input / output ports. An example in which the control circuit 50 is applied will be described.

[Overall Configuration of Dual Port SRAM Circuit]
FIG. 20 is a plan view schematically showing a layout of the entire dual-port SRAM circuit. Referring to FIG. 20, in a dual-port type SRAM circuit 10C, a region provided with a plurality of first I / O circuits 13A and a plurality of second I / O circuits 13B are sandwiched across memory array 11. The provided area is arranged. The plurality of first I / O circuits 13A, the memory array 11, and the plurality of second I / O circuits 13B are arranged in this order in the column direction (Y direction) of the memory array 11. A plurality of word line drivers 12A and 12B are provided adjacent to the memory array 11 in the row direction (X direction). The plurality of word line drivers 12A and 12B are used for a first word line driver 12A used for data access from the first I / O circuit 13A and for a data access from the second I / O circuit 13B. And a second word line driver 12B used for the above. A control circuit 14A for controlling the operation of the first I / O circuit 13A is provided adjacent to the first I / O circuit 13A in the row direction (-X direction). Further, a control circuit 14B for controlling the operation of the second I / O circuit 13B is provided adjacent to the second I / O circuit 13B in the row direction (-X direction).

  The ground wiring potential control circuit 16 described in the first and second embodiments and the power supply wiring potential control circuit 50 described in the third embodiment are connected to the memory array 11 and the plurality of first I / O circuits 13A. It is arranged between the memory array 11 and the plurality of second I / O circuits 13B. The operation mode control circuit 20 is arranged between the arrangement area of the plurality of word line drivers 12A and 12B and the arrangement area of the plurality of first control circuits 14A.

[Configuration of memory array]
FIG. 21 is a diagram showing a more detailed configuration of the SRAM circuit of FIG. The configuration diagram of the SRAM circuit of FIG. 21 corresponds to the configuration diagram of FIG. 15, and the portions corresponding to one first I / O circuit 13A and one second I / O circuit 13B It is shown.

  Referring to FIGS. 20 and 21, the dual-port SRAM circuit includes a first pair of bit lines BLA and / BLA and a second pair of bit lines BLB and / BLB for each column of memory array 11. . The first bit line pair BLA, / BLA is connected to the first I / O circuit 13A, and the second bit line pair BLB, / BLB is connected to the second I / O circuit 13B. The dual-port SRAM circuit further includes a first word line WLA and a second word line WLB for each row of the memory array 11. The first word line WLA is connected to the output node of the first word line driver 12A in FIG. 20, and the second word line WLB is connected to the output node of the second word line driver 12B in FIG. .

  Each memory cell MC includes a latch circuit composed of two CMOS inverters and four transfer NMOS transistors. The connection relationship between PMOS transistors PM1, PM2 and NMOS transistors NM1, NM2 forming the latch circuit is the same as that described with reference to FIG. 3, and therefore, description thereof will not be repeated.

  The transfer NMOS transistor NM1 is connected between the connection node ND1 and the bit line BLA, and the NMOS transistor NM2 is connected between the connection node ND2 and the bit line / BLA. The gates of the NMOS transistors NM1 and NM2 are connected to a common word line WLA. The transfer NMOS transistor NM3 is connected between the connection node ND1 and the bit line BLB, and the NMOS transistor NM4 is connected between the connection node ND2 and the bit line / BLB. The gates of the NMOS transistors NM3 and NM4 are connected to a common word line WLB.

[Arrangement of ground wiring potential control circuit and power supply wiring potential control circuit]
In the following description, as shown in FIG. 21, the reference numerals of the ground wiring potential control circuit and the power supply wiring potential control circuit arranged between the memory array 11 and the first I / O circuit 13A are 16C and 50C, respectively. It is described. The reference numerals of the ground wiring potential control circuit and the power supply wiring potential control circuit disposed between the memory array 11 and the second I / O circuit 13B are described as 16D and 50D, respectively.

  Referring to FIGS. 20 and 21, more specifically, NMOS transistor NM10C forming ground line potential control circuit 16C on first I / O circuit 13A side is adjacent to the region where memory array 11 is arranged. Is formed in the P well region 71 extending in the X direction. The gate of the NMOS transistor NM10C is connected to the control line ARYSWN. The PMOS transistor PM10C constituting the ground line potential control circuit 16C is arranged in the N-well region 72 adjacent to the P-well region 71 on the side opposite to the memory array 11 (−Y direction side). The PMOS transistor PM12C forming the power supply wiring potential control circuit 50C is arranged in the same N-well region 72 as the PMOS transistor PM10C forming the ground wiring potential control circuit 16C. The gate of the PMOS transistor PM12C is connected to a control line ARYSWP common to the gate of the PMOS transistor PM10C. The precharge circuit CPC provided in the first I / O circuit 13A is also formed in the N well region 72 where the PMOS transistors PM10C and PM12C are arranged.

  Similarly, the NMOS transistor NM10D constituting the ground wiring potential control circuit 16D on the side of the second I / O circuit 13B is connected to the P well region 70 extending in the X direction adjacent to the region where the memory array 11 is arranged. It is formed. The gate of the NMOS transistor NM10B is connected to the control line ARYSWN2. The PMOS transistor PM10D forming the ground line potential control circuit 16D is arranged in the N-well region 69 adjacent to the P-well region 70 on the opposite side (+ Y direction side) from the memory array 11. The PMOS transistor PM12D forming the power supply wiring potential control circuit 50D is arranged in the same N-well region 69 as the PMOS transistor PM10D forming the ground wiring potential control circuit 16D. The gate of the PMOS transistor PM12D is connected to the control line ARYSWP2 common to the gate of the PMOS transistor PM10D. The precharge circuit CPC provided in the first I / O circuit 13B is also formed in the N well region 69 where the PMOS transistors PM10D and PM12D are arranged.

  The operation mode control circuit 20 supplies a common control signal to the control lines ARYSWN and ARYSWN2, and supplies a common control signal to the control lines AYRSWP and ARYSWP2. The logic level of the control signal for each operation mode is the same as that described in FIG. 5 and the like, and will not be repeated here.

[Effect of Fourth Embodiment]
As described above, the ground wiring potential control circuit 16 and the power supply wiring potential control circuit 50 described in the first to third embodiments can be applied to a dual-port SRAM circuit. Therefore, the semiconductor device of the fourth embodiment has substantially the same effects as those of the semiconductor devices of the first to third embodiments.

  As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say. In particular, it is needless to say that terms such as MOS (Metal Oxide Semiconductor) are conventionally used and do not indicate that the material and the like are limited to metals and oxides.

  10, 10A, 10B, 10C SRAM circuit, 11 memory array, 12, 12A, 12B word line driver, 13, 13A, 13B I / O circuit, 14, 14A, 14B Control circuit & address decoder, 16, 16A Ground wiring potential Control circuit, 17 memory cell groups, 20 and 20A operation mode control circuit, 50 power supply wiring potential control circuit, 100 semiconductor substrate, 101 CPU, ARVDD power supply wiring, ARVSS ground wiring, ARYSWN, ARYSWN2, ARYSWP control lines, BL, BLA, BLB, / BL, / BLA, / BLB bit line, CPC precharge circuit, MC memory cell, NM10 to NM13 NMOS transistor, PM10 to PM12, PM20 to PM22 PMOS transistor, RS, SD control signal, VDD Power supply node, VSS ground node, WL, WLA, WLB Word line.

Claims (8)

An SRAM circuit having a first operation mode and a second operation mode,
The SRAM circuit includes:
A first bit line pair extending in a first direction;
A first word line extending in a second direction crossing the first direction;
A memory cell electrically connected to the first bit line pair and the first word line;
A latch circuit included in the memory cell;
A first wiring that is electrically connected to the latch circuit and supplies a first potential to the latch circuit;
A second wiring that is electrically connected to the latch circuit and supplies a second potential lower than the first potential;
A first potential control circuit electrically connected to the memory cell via the second wiring;
A second potential control circuit that controls the potential of the first wiring ,
The latch circuit includes a first CMOS inverter and a second CMOS inverter,
The first potential control circuit includes:
A first NMOS transistor electrically connected between the second wiring and a third wiring for supplying a third potential lower than the second potential;
A first PMOS transistor electrically connected between the second wiring and the third wiring in parallel with the first NMOS transistor;
In the second operation mode, a gate electrode and a drain electrode of the first NMOS transistor are electrically connected to each other via the second wiring ,
The second potential control circuit includes a second PMOS transistor connected between a node that supplies the first potential and the first wiring,
The first PMOS transistor includes:
A first fin extending in a first direction;
A first gate electrode extending across the first fin in a second direction intersecting the first direction;
A first source electrode extending in the second direction so as to straddle the first fin;
A first drain electrode that extends in the second direction so as to straddle the first fin, and that is different from the first source electrode;
A semiconductor device , wherein a gate electrode of the first PMOS transistor and a gate electrode of the second PMOS transistor are formed by the first gate electrode . The SRAM circuit further includes an operation mode control circuit that controls an operation of the first potential control circuit,
2. The semiconductor according to claim 1, wherein the operation mode control circuit controls the first NMOS transistor to be in an on state in the first operation mode, and controls the first NMOS transistor to be in a diode connection state in the second operation mode. apparatus. The operation mode control circuit further includes a second NMOS transistor electrically connected between the second wiring and a gate electrode of the first NMOS transistor,
3. The semiconductor device according to claim 2, wherein in the second operation mode, a gate electrode of the first NMOS transistor and the second wiring are electrically connected to each other via the second NMOS transistor. A first control line electrically connected to a gate electrode of the first NMOS transistor;
A gate electrode of the first PMOS transistor is electrically connected to the third wiring;
The operation mode control circuit,
A second NMOS transistor electrically connected between the first control line and the second wiring;
A third PMOS transistor electrically connected between the first control line and a fourth wiring for supplying a fourth potential higher than the first potential;
The operation mode control circuit,
In the first operation mode, the first NMOS transistor is turned on, and the second NMOS transistor is turned off,
3. The semiconductor device according to claim 2, wherein in the second operation mode, the first NMOS transistor is turned off and the second NMOS transistor is turned on .   2. The semiconductor device according to claim 1, wherein each of said first NMOS transistor and said first PMOS transistor comprises a FinFET. An SRAM circuit having a first operation mode and a second operation mode,
The SRAM circuit includes:
A plurality of first bit line pairs and a plurality of second bit line pairs extending in a first direction;
A plurality of first word lines and a plurality of second word lines extending in a second direction intersecting the first direction;
Memory cells respectively connected to the first bit line pair, the second bit line pair, the first word line, and the second word line;
A first CMOS inverter and a second CMOS inverter included in each of the memory cells and forming a latch circuit;
A memory array in which the memory cells are arranged in a matrix,
A first wiring electrically connected to each of the memory cells and supplying a first potential to each of the memory cells;
A second wiring electrically connected to each of the memory cells and supplying a second potential lower than the first potential;
A second wiring potential control circuit electrically connected to the memory cell via the second wiring;
A third wiring potential control circuit electrically connected to the memory cell via the second wiring,
Each of the second wiring potential control circuit and the third wiring potential control circuit includes:
A first NMOS transistor electrically connected between the second wiring and a third wiring for supplying a third potential lower than the second potential;
A first PMOS transistor electrically connected between the second wiring and the third wiring in parallel with the first NMOS transistor;
A gate electrode and a drain electrode of the first NMOS transistor are electrically connected to each other via the second wiring;
The first bit line pair is electrically connected to a first input / output circuit for reading data from a selected memory cell and writing data to a selected memory cell,
The second bit line pair is electrically connected to a second input / output circuit for reading data from a selected memory cell and writing data to a selected memory cell,
In a plan view, the first input / output circuit and the second input / output circuit are arranged on opposite sides of the memory array in the first direction,
In a plan view, the second wiring potential control circuit is disposed between the memory array and the first input / output circuit in the first direction,
The semiconductor device, wherein the third wiring potential control circuit is disposed between the memory array and the second input / output circuit in the first direction in a plan view. A P-well region adjacent to the memory array in plan view and extending in the second direction;
An N-well region adjacent to the P-well region in the first direction and extending in the second direction in plan view;
The N-well region is provided on the opposite side of the memory array with the P-well region interposed in the first direction;
The first PMOS transistor is disposed in the N-well region;
7. The semiconductor device according to claim 6, wherein said first NMOS transistor is arranged in said P-well region.   8. The semiconductor device according to claim 7, wherein each of said first NMOS transistor and said first PMOS transistor is constituted by a FinFET.

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