JP2013232257A - Semiconductor device including multiport memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device including a multiport memory, in which a leak current of memory cells in a standby mode is reduced so as to achieve low power consumption.SOLUTION: A semiconductor device includes a memory unit (MP1) that has a plurality of memory cells which are selected on the basis of a first port address (ADDA) and a second port address (ADDB); and a mode switching control circuit (MS_CTL1) that generates a first control signal (STB) on the basis of a first operation mode setting signal (RSA) and a second operation mode setting signal (RSB). The device controls, on the basis of the first control signal, a voltage of a cell power supply wiring that supplies a power supply voltage to the plurality of memory cells.

Description

  The present invention relates to a semiconductor device, for example, a semiconductor device including a multiport memory.

  Along with miniaturization of transistors mounted on semiconductor devices, power supply voltages and threshold voltages of transistors are being reduced. As a result, in a semiconductor device to which a power supply voltage is supplied, an increase in the leakage current of the transistor in a state where the transistor is not operating (hereinafter referred to as a standby mode) becomes a problem. Note that in this specification, a state in which a transistor operates with a power supply voltage supplied to a semiconductor device is referred to as a normal operation mode. In the case of a semiconductor device incorporating an SRAM (Static Random Access Memory), the SRAM in the standby mode needs to hold data in the immediately preceding normal operation mode. As a result, as the storage capacity of the SRAM increases, the leakage current of the SRAM in the standby mode, that is, the consumption current also increases.

  Japanese Patent Laying-Open No. 2003-67241 (Patent Document 1) discloses a configuration for realizing power saving of a dual port memory in which a single port RAM can be accessed from two access ports via a control circuit. When the two units connected to each access port are both operating in the power saving mode, the power consumption of the dual port memory is suppressed by stopping the operation of the control circuit.

  Japanese Patent Laid-Open No. 9-45079 (Patent Document 2) discloses a control for setting timing and a period of data reading and writing for each port in a dual port RAM capable of reading / writing asynchronously with respect to a memory cell. A configuration provided with a circuit is disclosed. This prevents data from being destroyed by access from the respective ports to the same memory cell.

  Japanese Patent Laying-Open No. 2004-206745 (Patent Document 3) discloses a configuration for reducing the leakage current of the SRAM. In Patent Document 3, the power supply voltage supplied to the memory cell included in the SRAM is changed between the switch and the transistor in the standby mode and the normal operation mode, thereby reducing the leakage current of the SRAM.

JP 2003-67241 A JP 9-45079 A JP 2004-206745 A

  Patent Document 1 does not have a power saving function of a memory cell included in a dual port memory, and cannot suppress power consumption caused by a leak current of the memory cell in the standby mode. Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a memory cell array having a plurality of memory cells each having a first and a second power supply node, a cell power supply line connected to the first power supply node of each of the plurality of memory cells, A cell power supply for controlling the voltage of the cell power supply wiring connected to the first and second ports for selecting the memory cells based on the first address and the second address supplied, respectively, the first power supply wiring and the cell power supply wiring A voltage control circuit; and a mode switching control circuit that generates a first control signal based on a first operation mode setting signal and a second operation mode setting signal that respectively set the operation mode of the first port and the second port; The cell power supply voltage control circuit determines the voltage of the cell power supply wiring based on the first control signal when at least one of the first port and the second port is in the normal operation mode. When the first voltage level is set and both the first port and the second port are in the standby mode, the voltage of the cell power supply line is changed from the first voltage level toward the voltage of the second power supply node. A semiconductor device comprising a multi-port memory set to a second voltage level.

  According to the embodiment, it is possible to reduce the current consumption of the memory cell in the standby mode of the semiconductor device including the multiport memory.

1 is a configuration diagram of a semiconductor device including a multiport memory according to a first embodiment. 1 is a configuration diagram of a dual port memory according to a first embodiment. 3 is a circuit diagram of a memory cell according to the first embodiment. FIG. 4 is a detailed circuit diagram of a dual port memory according to the first embodiment. FIG. 2 is a circuit diagram of a cell power supply voltage control circuit according to the first embodiment. FIG. FIG. 4 is a timing chart for explaining the operation of the dual port memory according to the first embodiment. FIG. 6 is a configuration diagram of a semiconductor device including a multiport memory according to a second embodiment. FIG. 6 is a configuration diagram of a dual port memory according to a second embodiment. 4 is a detailed circuit diagram of a dual port memory according to a second embodiment. FIG. FIG. 6 is a circuit diagram of a bit line precharge circuit according to a second embodiment. FIG. 10 is a timing chart for explaining the operation of the bit line precharge circuit according to the second embodiment. FIG. 10 is a timing chart for explaining the operation of the dual port memory according to the second embodiment. FIG. 10 is a configuration diagram of a dual port memory according to a modification of the second embodiment. FIG. 10 is a configuration diagram of a semiconductor device including a multiport memory according to a third embodiment. FIG. 10 is a timing diagram illustrating an operation of a semiconductor device including a multiport memory according to a third embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. In the description of the embodiment, reference to the number, amount, and the like is not necessarily limited to the number, amount, and the like unless otherwise specified. In the drawings of the embodiments, the same reference numerals and reference numerals represent the same or corresponding parts. Further, in the description of the embodiments, the overlapping description may not be repeated for the portions with the same reference numerals and the like.

<Embodiment 1>
A configuration of a semiconductor device LSI (hereinafter referred to as a semiconductor device) including the multiport memory according to the first embodiment will be described with reference to FIG.

  The semiconductor device LSI includes a first functional block FB_A, a second functional block FB_B, and a dual port memory DP_SRAM. The first functional block FB_A is, for example, a CPU (Central Processing Unit) or a DSP (Digital Signal Processor), and outputs image data to the dual port memory DP_SRAM primarily. The second functional block FB_B sends the data stored in the dual port memory DP_SRAM to a device for rendering an image.

  The dual port memory DP_SRAM has an A port and a B port, and data can be read or written asynchronously at both ports. The first functional block FB_A is connected to the A port, and the second functional block FB_B is connected to the B port. The dual port memory DP_SRAM includes a memory unit MP1 and a mode switching control circuit MS_CTL1.

  The dual port memory DP_SRAM performs a read operation and a write operation based on the clock CLKA and the clock CLKB output from each functional block. The designation of the read operation and the write operation is set for each A port and B port by the operation control signal CENA, the control signal CTLA, the operation control signal CENB, and the control signal CTLB. A memory cell included in the memory unit MP1 is designated by an address ADDA and an address ADDB, and in a read operation, data in the memory cell is output as output data QA and output data QB. In the case of a write operation, input data DA and input data DB are written into the memory cell.

  The mode switching control circuit MS_CTL1 sets the A port and the B port to the standby mode or the normal operation mode based on the mode setting signal RSA and the mode setting signal RSB output from the first functional block FB_A and the second functional block FB_B, respectively. Set to. According to the mode set for the A port and the B port, the mode switching control circuit MS_CTL1 supplies the supply voltage to the memory unit MP1 by the standby signal STB, the AB port power cut-off signal AB_PC, and the AB port word line suppression signal AB_WC. To control.

  The configuration of the dual port memory DP_SRAM according to the first embodiment will be described with reference to FIG.

  The dual port memory DP_SRAM includes a memory cell array MA, an A port word line selection circuit A_WX, a B port word line selection circuit B_WX, an AB port I / O unit AB_PT, and a control unit PT_CTL. The mode switching control circuit MS_CTL1 constitutes a part of the control unit PT_CTL. Accordingly, the memory unit MP1 shown in FIG. 1 is a part constituting the dual port memory DP_SRAM other than the mode switching control circuit MS_CTL1.

  The memory cell array MA includes a plurality of memory cells MC arranged in an array, a plurality of A port word lines wd_A and B port word lines wd_B extending in the row direction, and a plurality of A port bits extending in the column direction. It has a line pair blt_A / blb_A and a plurality of B port bit line pairs blt_B / blb_B. The memory cell MC is a dual port memory cell, and is connected to the first functional block FB_A via the A port word line wd_A and the A port bit line blt_A / blb_A, and from the second functional block FB_B to the B port word line wd_B and Data is exchanged via the B port bit line blt_B / blb_B.

  AB port I / O unit AB_PT includes A port I / O circuit A_IO connected to A port bit line pair blt_A / blb_A and B port I / O circuit B_IO connected to B port bit line pair blt_B / blb_B. Have multiple. The read operation or the write operation with respect to the memory cell MC of the first functional block FB_A and the second functional block FB_B is independent from each other from the first functional block FB_A and the second functional block FB_B (that is, asynchronously). ) Supplied.

  Operations such as reading and writing of the A port I / O circuit A_IO and the B port I / O circuit B_IO are performed by a control signal CTLA, a clock CLKA, an operation control signal CENA, a control signal CTLB, a clock CLKB, and an operation control signal. Control based on CENB. A port word line selection circuit A_WX and B port word line selection circuit B_WX select A port word line wd_A and B port word line wd_B based on address ADDA and address ADDB, respectively.

A circuit diagram of the memory cell MC according to the first embodiment will be described with reference to FIG.
The memory cell MC shown in FIG. 3A is a dual port memory. Memory cell MC forms a flip-flop with an inverter formed of a p-type MOS (Metal Oxide Semiconductor) transistor ML1 and an n-type MOS transistor MD1, and an inverter formed of a p-type MOS transistor ML2 and an n-type MOS transistor MD2. One output of the flip-flop is connected to the A port bit line blt_A and the B port bit line blt_B via the n-type MOS transistor MT1a and the n-type MOS transistor MT1b, respectively. The other output of the flip-flop is connected to A port bit line blb_A and B port bit line blb_B via n type MOS transistor MT2a and n type MOS transistor MT2b, respectively.

  In the p-type MOS transistors ML1 and ML2 formed in the n-well region, the sources are connected to the power supply wiring dd, and the n-well region is connected to the power supply wiring bp. The n-type MOS transistors MD1 and MD2 formed in the p-well region have their sources connected to the cell power supply line ssc and their p-wells connected to the power supply line bn. Similarly, the p-type well in which the n-type MOS transistors MT1a, MT2a, MT1b, and MT2b are formed is connected to the power supply line bn.

  The memory cell MC shown in FIG. 3B is a dual port memory cell. Unlike the memory cell MC shown in FIG. 3A, the sources of the p-type MOS transistors ML1 and ML2 are connected to the cell power supply wiring ddc, and the sources of the n-type MOS transistors MD1 and MD2 are connected to the power supply wiring ss.

  A detailed circuit diagram of the dual port memory DP_SRAM according to the first embodiment will be described with reference to FIG.

  The memory cell array MA has a plurality of memory cells MC shown in FIG. 3A arranged in an array in the row direction and the column direction. The A port word line selection circuit A_WX selects any one A port word line wd_A designated by the address ADDA and sets it to the high level. The B port word line selection circuit B_WX selects any one of the B port word lines wd_B specified by the address ADDB and sets it to the high level. AB port word line inactivating circuit AB_WN has a plurality of n-type MOS transistors Mwa and n-type MOS transistors Mwb each having a drain connected to A port word line wd_A and B port word line wd_B. The gate of each transistor is connected to AB port word line suppression signal AB_WC, and the source is connected to power supply line ss.

  The AB port I / O unit AB_PT includes an A port I / O circuit A_IO connected to the A port bit line pair blt_A / blb_A, and a B port I / O circuit B_IO connected to the B port bit line pair blt_B / blb_B. A plurality. The A port I / O circuit A_IO and the B port I / O circuit B_IO are respectively read by the operation control signal CENA, the clock CLKA, and the control signal CTLA, and the operation control signal CENB, the clock CLKB, and the control signal CTLB. Perform an operation or write operation.

  AB port I / O power supply cutoff circuit AB_PWN is a p-type MOS transistor that supplies power supply voltage Vdd to A port I / O circuit A_IO, B port I / O circuit B_IO, A port control circuit A_CTL, and B port control circuit B_CTL Has Mpc. The source of the p-type MOS transistor Mpc is connected to the power supply wiring dd, and the gate thereof is connected to the AB port power supply cutoff signal AB_PC. The drain of the p-type MOS transistor Mpc is connected to the power supply (not shown) of each A port I / O circuit A_IO, B port I / O circuit B_IO, A port control circuit A_CTL, and B port control circuit B_CTL. . Similarly, the supply of the power supply voltage Vdd is controlled through the p-type MOS transistor Mpc whose conduction state is controlled by the AB port power supply cutoff signal AB_PC in the same way as for the A port word line selection circuit A_WX and the B port word line selection circuit B_WX. The

  The data of the memory cell MC read by the A port I / O circuit A_IO is output as the output data QA to the first functional block FB_A. Similarly, the data of the memory cell MC read by the B port I / O circuit B_IO is output as the output data QB to the second functional block FB_B. Input data DA output from the first functional block FB_A is input to the A port I / O circuit A_IO and written to the memory cell MC. Similarly, the input data DB output from the second functional block FB_B is input to the B port I / O circuit B_IO and written to the memory cell MC. The read operation or write operation for the A port and B port of the dual port memory DP_SRAM is performed asynchronously at each port.

  The A port control circuit A_CTL controls operations of the A port word line selection circuit A_WX and the A port I / O circuit A_IO. Similarly, the B port control circuit B_CTL controls the operation of the B port word line selection circuit B_WX and the B port I / O circuit B_IO. As will be described later, the cell power supply voltage control circuit VC_CTLa controls the voltage of the cell power supply wiring ssc of the memory cell MC shown in FIG. 3A in response to the standby signal STB.

  The mode switching control circuit MS_CTL1 includes an AND circuit 10 and a power supply control signal generation circuit 11. The AND circuit 10 outputs a signal RSAB that is a logical product of the input mode setting signal RSA and mode setting signal RSB. Both mode setting signals have binary values, and each port of the dual port memory DP_SRAM is set to the standby mode when it is at a high level, and to the normal operation mode when it is at a low level. When both the A port and the B port of the dual port memory DP_SRAM are set to the standby mode, the signal RSAB outputs a high level. When at least one of the A port and the B port is set to the normal operation mode, the signal RSAB outputs a low level.

  When the signal RSAB changes from the low level to the high level, the power supply control signal generation circuit 11 changes the standby signal STB from the high level to the low level after the elapse of a set delay time, and the AB port word line suppression signals AB_WC and AB The port power supply cutoff signal AB_PC is changed from low level to high level.

  When the AB port power supply cutoff signal AB_PC changes from low level to high level, the p-type MOS transistor Mpc that has supplied the power supply voltage Vdd to the A port I / O circuit A_IO and the B port I / O circuit B_IO is changed from the conductive state to the nonconductive state. Change to state. Similarly, the p-type MOS transistor Mpc that has supplied the power supply voltage Vdd to the A port word line selection circuit A_WX, the B port word line selection circuit B_WX, the A port control circuit A_CTL, and the B port control circuit B_CTL is also turned off. Become. As a result, the current consumption of the dual port memory DP_SRAM in which the A port and the B port are both in the standby mode is significantly reduced as compared with the normal operation mode.

  In the standby mode, when the supply of the power supply voltage Vdd to the A port word line selection circuit A_WX and the B port word line selection circuit B_WX is cut off, the n-type MOS transistors Mwa and Mwb of the AB port word line inactivation circuit AB_WN The voltages of the A port word line wd_A and the B port word line wd_B are set to the power supply voltage Vss.

  A circuit diagram of cell power supply voltage control circuits VC_CTLa, VC_CTLb, and VC_CTLc according to the first embodiment will be described with reference to FIG.

  5A shows a cell power supply voltage control for controlling the voltage of the cell power supply line ssc shown in FIG. 4 when the memory cell array MA according to the first embodiment is constituted by the memory cells MC shown in FIG. This is a specific configuration of the circuit VC_CTLa. The cell power supply voltage control circuit VC_CTLa includes an n-type MOS transistor M41a (power switch) whose conduction state is controlled by a standby signal STB, a resistor Ra, and a diode-connected n-type MOS transistor M42a. The drain of n-type MOS transistor M41a, one end of resistor Ra, and the drain / gate of n-type MOS transistor M42a are connected to cell power supply line ssc of each memory cell MC included in memory cell array MA. The source of n-type MOS transistor M41a, the other end of resistor Ra, and the source of n-type MOS transistor M42a are connected to power supply line ss.

  When the standby signal STB becomes high level, the n-type MOS transistor M41a becomes conductive, and the voltage of the cell power supply wiring ssc becomes equal to the power supply voltage Vss which is the voltage of the power supply wiring ss. When the standby signal STB becomes low level, the n-type MOS transistor M41a becomes non-conductive, and the voltage of the cell power supply line ssc is the relationship between the leak current of the memory cell MC and the current flowing through the diode-connected n-type MOS transistor M42a and the resistor Ra. Determined by As a result, the voltage of the cell power supply wiring ssc during the period when the standby signal STB is at the low level becomes a value increased from the power supply voltage Vss.

  When at least one of the A port and the B port is set to the normal operation mode, the wiring (p-side power supply node) connected to the sources of the p-type MOS transistors ML1 and ML2 of the memory cell MC shown in FIG. ) Is applied with a power supply voltage Vdd. On the other hand, the power supply voltage Vss is applied to the wiring (n-side power supply node) connected to the sources of the n-type MOS transistors MD1 and MD2 of the memory cell MC via the cell power supply wiring ssc. When both the A port and the B port are set to the standby mode, the voltage of the n-side power supply node fluctuates in a direction approaching the voltage of the p-side power supply node to which the power supply voltage Vdd is applied from the power supply voltage Vss, that is, The value is set higher than the power supply voltage Vss.

  As a result, the leakage current of the memory cell array MA included in the dual port memory DP_SRAM is greatly reduced with respect to the current consumption of the memory cell array MA in the normal operation mode when both the A port and the B port are set to the standby mode. . The voltage of the cell power supply line ssc in the standby mode is set to a power supply voltage that can hold the data held in the memory cell MC without destroying it in the normal operation mode.

  In the case where the n-type MOS transistor M41a is non-conductive, if the voltage of the cell power supply line ssc can be set to a desired value only by the n-type MOS transistor M42a, the resistor Ra is omitted, and the n-type MOS transistor M41a and the n-type MOS transistor The cell power supply voltage control circuit VC_CTLa may be configured by M42a.

  FIG. 5B shows the configuration of the cell power supply voltage control circuit VC_CTLb that controls the voltage of the cell power supply wiring ddc when the memory cell array MA according to the first embodiment is configured with the memory cells MC shown in FIG. Indicates. Cell power supply voltage control circuit VC_CTLb has p-type MOS transistor M41b (power switch) whose conduction state is controlled by standby signal / STB, resistor Rb, and diode-connected p-type MOS transistor M42b. The standby signal / STB is a signal having a phase opposite to that of the standby signal STB, and is generated by the power supply control signal generation circuit 11 shown in FIG. The drain of p-type MOS transistor M41b, one end of resistor Rb, and the drain / gate of p-type MOS transistor M42b are connected to cell power supply wiring ddc of each memory cell included in memory cell array MA. The source of the p-type MOS transistor M41b, the other end of the resistor Rb, and the source of the p-type MOS transistor M42b are connected to the power supply line dd.

  When the standby signal / STB becomes low level, the p-type MOS transistor M41b which is a power switch becomes conductive, and the voltage of the cell power supply wiring ddc becomes equal to the power supply voltage Vdd which is the voltage of the power supply wiring dd. When standby signal / STB goes high, the voltage of cell power supply line ddc is determined by the relationship between the leakage current of memory cell MC and the current flowing through diode-connected p-type MOS transistor M42b and resistor Rb. As a result, the voltage of the cell power supply wiring ddc during the period when the standby signal / STB is at the high level is lower than the power supply voltage Vdd, and the leakage current of the memory cell MC is reduced.

  When at least one of the A port and the B port is set to the normal operation mode (standby signal / STB is low level), it is connected to each source of the n-type MOS transistors MD1 and MD2 of the memory cell MC shown in FIG. A power supply voltage Vss is applied to the wiring (n-side power supply node). On the other hand, power supply voltage Vdd is applied to the wiring (p-side power supply node) connected to the sources of p-type MOS transistors ML1 and ML2 of memory cell MC via cell power supply wiring ddc. When both the A port and the B port are set to the standby mode (the standby signal / STB is at the high level), the voltage of the p-side power supply node is that of the n-side power supply node to which the power supply voltage Vss is applied from the power supply voltage Vdd. It is set to a value that fluctuates in the direction approaching the voltage, that is, a value that has decreased from the power supply voltage Vdd.

  As a result, the leakage current of the memory cell array MA included in the dual port memory DP_SRAM is greatly reduced with respect to the current consumption of the memory cell array MA in the normal operation mode when both the A port and the B port are set to the standby mode. . The voltage of the cell power supply wiring ddc in the standby mode is set to a power supply voltage that can be held without destroying the data held in the memory cell MC in the normal operation mode.

  When the p-type MOS transistor M41b is in a non-conductive state, if the voltage of the cell power supply wiring ddc can be set to a desired value only by the p-type MOS transistor M42b, the resistor Rb is omitted, and the p-type MOS transistor M41b and the p-type MOS transistor are omitted. The cell power supply voltage control circuit VC_CTLb may be configured by M42b.

  FIG. 5C shows the configuration of the cell power supply voltage control circuit VC_CTLc that controls the voltage of the cell power supply wiring ssc when the memory cell array MA according to the first embodiment is configured with the memory cells MC shown in FIG. Indicates. Cell power supply voltage control circuit VC_CTLc has p-type MOS transistor M41c and n-type MOS transistor M42c whose conduction state is controlled by standby signal / STB, and n-type MOS transistors M43c and M44c. The drains of n-type MOS transistors M43c and M44c are both connected to cell power supply line ssc, and their sources are connected to power supply line ss. In the n-type MOS transistor M44c, the power supply voltage Vdd is applied to the gate via the power supply wiring dd, and the n-type MOS transistor M44c functions as a resistor having a predetermined impedance.

  An n-type MOS transistor M42c is connected between the drain and gate of the n-type MOS transistor M43c. The source and drain of p-type MOS transistor M41c are connected to power supply line dd and the gate of n-type MOS transistor M43c, respectively. When standby signal / STB is at a low level, n-type MOS transistor M42c is turned off, and power supply voltage Vdd is applied to the gate of n-type transistor M43c through p-type MOS transistor M41c in a turned-on state. On the other hand, when the standby signal / STB is at a high level, the n-type MOS transistor M42c becomes conductive, and the n-type transistor M43c has a diode connection in which the source and the gate are short-circuited.

  That is, when at least one of the A port and the B port is set to the normal operation mode (standby signal / STB is at low level), the n-type MOS transistor M43c becomes conductive, and the n-side power supply node of the memory cell MC has a cell A power supply voltage Vss is applied through the power supply wiring ssc. On the other hand, power supply voltage Vdd is applied to the p-side power supply node of memory cell MC. When both the A port and the B port are set to the standby mode (the standby signal / STB is at the high level), the voltage at the n-side power supply node is the leakage current of the memory cell MC and the diode-connected n-type MOS transistor M43c. It is determined by the relationship with the current flowing through the n-type MOS transistor M44c having a predetermined impedance.

  When both the A port and the B port are set to the standby mode, the cell power supply voltage control circuit VC_CTLc changes the voltage of the n-side power supply node from the power supply voltage Vss to the voltage of the p-side power supply node to which the power supply voltage Vdd is applied. It is set in the direction of approaching, that is, a value higher than the power supply voltage Vss. As a result, the leakage current of the memory cell array MA included in the dual port memory DP_SRAM is greatly reduced with respect to the current consumption of the memory cell array MA in the normal operation mode when both the A port and the B port are set to the standby mode. . The voltage of the cell power supply line ssc in the standby mode is set to a power supply voltage that can hold the data held in the memory cell MC without destroying it in the normal operation mode.

  The cell power supply voltage control circuit VC_CTLc shown in FIG. 5C is a circuit that controls the voltage of the cell power supply wiring ssc of the memory cell array MA configured by the memory cells MC shown in FIG. A cell power supply voltage for controlling the voltage of the cell power supply wiring ddc of the memory cell array MA constituted by the memory cell MC shown in FIG. 3B by switching the conductivity type of each transistor constituting the cell power supply voltage control circuit VC_CTLc. A control circuit can be realized. When the p-type MOS transistor M41c is changed to an n-type MOS transistor, the power supply voltage Vss is applied to its source, and when the n-type MOS transistor M44c is changed to a p-type MOS transistor, the power supply voltage Vss is applied to its gate. To do. Further, the standby signal / STB is replaced with the standby signal STB.

  The operation of the dual port memory DP_SRAM according to the first embodiment will be described with reference to FIG.

  The vertical axis in FIG. 6 schematically shows waveforms of the mode setting signal RSA / RSB, the clock CLKA / CLKB, and the operation control signal CENA / CENB input to the A port and the B port of the dual port memory DP_SRAM. In the case of a signal having a binary value, “0” means a low level and “1” means a high level. The horizontal axis indicates time. In the following description, the state where both the A port and the B port are set or shifted to the standby mode may be described as the dual port memory DP_SRAM being set or shifted to the standby mode.

  In the A port, the normal operation mode is shifted to the transition mode at time t2. At time t5 after time tsrs_r has elapsed from time t1, the first functional block FB_A changes the mode setting signal RSA from the low level (normal operation mode) to the high level (standby mode), and sets the A port of the dual port memory DP_SRAM. Set to standby mode.

  At time t7 after elapse of time thrs_r from time t5, the A port of the dual port memory DP_SRAM shifts to the standby mode. In order to stop the operation of the A port of the dual port memory DP_SRAM from the time t2 to the time t7 when the transition mode ends, the value of the clock CLKA is fixed to, for example, a low level, and the supply of the clock CLKA to the A port is performed. Stop.

  Similarly to the A port, the B port shifts from the normal operation mode to the transition mode at time t4, and shifts from the transition mode to the standby mode at time t8.

The operation of the mode switching control circuit MS_CTL1 will be described.
When mode setting signal RSA and mode setting signal RSB both become high level at time t6, mode switching control circuit MS_CTL1 changes the value of signal RSAB from low level to high level. When the signal RSAB becomes high level at time t6, the mode switching control circuit MS_CTL1 changes the standby signal STB from high level to low level and the AB port word line suppression signals AB_WC and AB by time t8 when the B port shifts to the standby mode. All the port power cutoff signals AB_PC are changed from the low level to the high level.

  When both the A port and the B port are set to the standby mode after the lapse of a delay time appropriately set at time t6 (<time t8), the voltage Vssc of the cell power supply line ssc is set to the power supply voltage in response to the standby signal STB. ΔVssc rises from Vss. This voltage increase ΔVssc is appropriately set to a value capable of maintaining the data before the dual port memory DP_SRAM is set to the standby mode. Further, the AB port power shutoff circuit AB_PWN shuts off the supply of the power supply voltage Vdd to the AB port I / O unit AB_PT, the A port control circuit A_CTL, and the B port control circuit B_CTL in response to the AB port power shutoff signal AB_PC. To do.

  The AB port word line inactivation circuit AB_WN sets the voltages of the A port word line wd_A and the B port word line wd_B to the power supply voltage Vss in response to the AB port word line suppression signal AB_WC. That is, during a period from time t8 to time t9, which will be described later, the dual port memory DP_SRAM in the standby mode holds data in the memory cell MC with low power consumption. Input signals other than the mode setting signal RSA and the mode setting signal RSB allow any signal state including the high impedance High-Z. However, the dual port memory DP_SRAM does not accept input.

  The supply state of the power supply voltage Vdd to the A port and the B port before the dual port memory DP_SRAM shifts to the standby mode at time t8 will be described.

  At time t7, port A transitions from transition mode to standby mode, while port B is still in transition mode. On the other hand, the A port word line selection circuit A_WX and the A port I / O circuit A_IO (hereinafter referred to as A port peripheral circuit), the B port word line selection circuit B_WX and the B port I / O circuit B_IO (hereinafter referred to as “port A peripheral circuit”). The supply voltage Vdd supply to the B port peripheral circuit is cut off after a delay time appropriately set at time t6 (<time t8).

  The mode switching control circuit MS_CTL1 does not shut off the power to the peripheral circuits for each port set to the standby mode, but cuts off the power to the peripheral circuits of all the ports after all the ports are set to the standby mode. As a result, it is possible to avoid the adverse effect of noise caused by the power shutdown of the port previously set to the standby mode on the operation of the port set to the standby mode later.

  At t9, the clock CLKA is set to the low level, and then the mode setting signal RSA changes from the high level to the low level (set to the normal operation mode) at time t11. The A port returns to the normal operation mode through the transition mode from time t9 to time t13. When the clock CLKB changes to low level at time t10 with a delay from time t9, and when the B port mode setting signal RSB changes from high level to low level (set to the normal operation mode) at t12, the B port changes from time t10 to time t14. It returns to the normal operation mode through the mode. In each transition mode period of the A port and B port of the dual port memory DP_SRAM, the clock CLKA / CLKB value is fixed to, for example, a low level, and the clock supply is stopped.

  The mode switching control circuit MS_CTL1 changes the signal RSAB from the high level to the low level in response to the change of the mode setting signal RSA that first sets the A port to the normal operation mode. That is, the signal RSAB is a signal that detects that one of the A port and the B port of the dual port memory DP_SRAM is set to the normal operation mode (becomes a low level). When the signal RSAB changes from the high level to the low level, the standby signal STB changes from the low level to the high level until the A port returns to the normal operation mode at time t13, and the AB port word line suppression signal AB_WC and the AB port power cut-off signal AB_PC. Both change from a high level to a low level.

  As a result, at time t11a at the latest, the power supply voltage Vss is applied to the cell power supply line ssc, and the AB port I / O unit AB_PT, the A port word line selection circuit A_WX, the B port word line selection circuit B_WX, and the A port control circuit The power supply voltage Vdd is supplied to A_CTL and the B port control circuit B_CTL. Further, the maintenance of the power supply voltage Vss of the A port word line wd_A and the B port word line wd_B by the AB port word line inactivation circuit AB_WN is released.

The effect of the semiconductor device LSI according to the first embodiment will be described.
As the capacity of a multi-port memory mounted on a semiconductor device increases, it is important to suppress the leakage current of the memory cell in the standby mode. In the dual port memory DP_SRAM according to the first embodiment, when both the A port and the B port shift to the standby mode, the voltage of the cell power supply wiring ssc rises from the power supply voltage Vss to a voltage at which the memory cell MC can hold data. Leakage current of the transistors constituting the memory cell MC is suppressed. Similar effects can be obtained by the cell power supply voltage control circuit VC_CTLb shown in FIG. 5B or the cell power supply voltage control circuit VC_CTLc shown in FIG.

  Power supply to A port word line selection circuit A_WX, B port word line selection circuit B_WX, AB port I / O unit AB_PT, A port control circuit A_CTL, and B port control circuit B_CTL provided in each port of dual port memory DP_SRAM The supply of the voltage Vdd is stopped based on the signal RSAB. As a result, the current consumption of the dual port memory DP_SRAM shifted to the standby mode is further reduced.

  When the dual port memory DP_SRAM is shifted to the standby mode, the supply voltage Vdd supply to the peripheral circuits of each port such as the A port I / O circuit A_IO is not shut off for each port set to the standby mode, and both ports are in the standby mode. After the mode is set, the supply of the power supply voltage Vdd to the A port and B port peripheral circuits is cut off simultaneously. As a result, it is possible to avoid the adverse effect of noise caused by the power shutdown of the port previously set to the standby mode on the operation of the port set to the standby mode later.

  During the transition mode in which the dual port memory DP_SRAM is shifted from the normal operation mode to the standby mode or from the standby mode to the normal operation mode, the supply of the clock CLKA or the clock CLKB to the A port or the B port in the transition mode is stopped. . Thereby, it is possible to set the mode of each port without considering the access interference of the memory cells MC performed asynchronously and independently at the A port and the B port.

<Embodiment 2>
With reference to FIG. 7, the configuration of the semiconductor device LSI according to the second embodiment will be described.

  The semiconductor device LSI includes a first functional block FB_A, a second functional block FB_B, and a dual port memory DP_SRAM. The functions of the first functional block FB_A and the second functional block FB_B are the same as those of the first embodiment shown in FIG. Further, the control operation and each control signal of the dual port memory DP_SRAM by the first functional block FB_A and the second functional block FB_B are the same as those in FIG.

  The mode switching control circuit MS_CTL2 sets the A port and the B port to the standby mode or the normal operation mode, respectively, based on the mode setting signals RAS and RSB output from the first functional block FB_A and the second functional block FB_B. . Depending on the mode set for the A port and the B port, the mode switching control circuit MS_CTL2 includes a standby signal STB, an A port power cutoff signal A_PC, a B port power cutoff signal B_PC, an A port word line suppression signal A_WC, and The supply voltage to the memory unit MP2 is controlled by the B port word line suppression signal B_WC.

  The configuration of the dual port memory DP_SRAM according to the second embodiment will be described with reference to FIG.

  The configuration of the memory cell array MA included in the dual port memory DP_SRAM is the same as that included in the dual port memory DP_SRAM according to the first embodiment. An A port word line selection circuit A_WX and a B port word line selection circuit B_WX are arranged adjacent to the left and right sides of the memory cell array MA, respectively. An A port I / O unit A_PT and a B port I / O unit B_PT are arranged adjacent to the lower side and the upper side of the memory cell array MA, respectively. A port control unit APT_CTL is arranged at the lower left and lower right of memory cell array MA, and B port control unit BPT_CTL is arranged at the upper left and upper right, respectively.

  Mode switching control circuit MS_CTL2 constitutes part of A port control unit APT_CT and B port control unit BPT_CTL. Therefore, the memory unit MP2 shown in FIG. 7 is a part constituting the dual port memory DP_SRAM other than the mode switching control circuit MS_CTL2.

  The A port I / O unit A_PT includes an A port I / O circuit A_IO connected to the A port bit line pair blt_A / blb_A and a B port bit line precharge circuit B_PG connected to the B port bit line pair blt_B / blb_B. Each has a plurality. The B port I / O unit B_PT includes a B port I / O circuit B_IO connected to the B port bit line pair blt_B / blb_B and an A port bit line precharge circuit A_PG connected to the A port bit line pair blt_A / blb_A. Each has a plurality.

  A detailed circuit diagram of the dual port memory DP_SRAM according to the second exemplary embodiment will be described with reference to FIG.

  The A port word line selection circuit A_WX selects any one A port word line wd_A designated by the address ADDA and sets it to the high level. The B port word line selection circuit B_WX selects any one of the B port word lines wd_B specified by the address ADDB and sets it to the high level.

  The A port word line deactivation circuit A_WN has an n-type MOS transistor Mwa whose drain and source are connected to the A port word line wd_A and the power supply wiring ss, respectively, and whose gate is supplied with the A port word line suppression signal A_WC. Have multiple. The B port word line deactivation circuit B_WN has an n-type MOS transistor Mwb whose drain and source are connected to the B port word line wd_B and the power supply line ss, respectively, and to which the B port word line suppression signal B_WC is applied. Have multiple.

  The p-type MOS transistor Mpca whose source is connected to the power supply wiring dd and whose gate is supplied with the A port power shutoff signal A_PC supplies the power supply voltage Vdd from its drain to the A port word line selection circuit A_WX. The p-type MOS transistor Mpcb whose source is connected to the power supply wiring dd and to which the B port power cutoff signal B_PC is applied at the gate supplies the power supply voltage Vdd from its drain to the B port word line selection circuit B_WX.

  The A-port power cutoff circuit A_PWN has a plurality of p-type MOS transistors Mpca whose source is connected to the power supply wiring dd and whose gate is supplied with the A-port power cutoff signal A_PC. The drain of the p-type MOS transistor Mpca supplies the power supply voltage Vdd to the A port I / O unit A_PT and the A port control circuit A_CTL. The B-port power cutoff circuit B_PWN has a plurality of p-type MOS transistors Mpcb whose source is connected to the power supply wiring dd and whose gate is supplied with the B-port power cutoff signal B_PC. The drain of the p-type MOS transistor Mpcb supplies the power supply voltage Vdd to the B port I / O unit B_PT and the B port control circuit B_CTL.

  The mode switching control circuit MS_CTL2A outputs an A port word line suppression signal A_WC, an A port power supply cutoff signal A_PC, and an A port bit line precharge signal RSAP based on the mode setting signal RSA. The mode switching control circuit MS_CTL2B outputs a B port word line suppression signal B_WC, a B port power supply cutoff signal B_PC, and a B port bit line precharge signal RSBP based on the mode setting signal RSB. Mode switching control circuit MS_CTL2C outputs standby signal STB to cell power supply voltage control circuit VC_CTLa based on mode setting signal RSA and mode setting signal RSB.

  As in the first embodiment, when the memory cell MC has the configuration shown in FIG. 3A, it is shown in FIG. 5C instead of the cell power supply voltage control circuit VC_CTLa shown in FIG. The cell power supply voltage control circuit VC_CTLc may be replaced. Further, when the memory cell MC has the configuration shown in FIG. 3B, the cell power supply voltage control circuit VC_CTLb shown in FIG. 5B may be replaced with the cell power supply voltage control circuit VC_CTLa.

  When the A port is set to the standby mode by the mode setting signal RSA, in response to the A port word line suppression signal A_WC, the A port word line inactivation circuit A_WN inactivates the A port word line wd_A (to low level). Set). Further, in response to the A port power supply cutoff signal A_PC, the A port power supply cutoff circuit A_PWN cuts off the supply of the power supply voltage Vdd to the A port I / O unit A_PT and the A port control circuit A_CTL.

  When the B port is set to the standby mode by the mode setting signal RSB, in response to the B port word line suppression signal B_WC, the B port word line deactivation circuit B_WN deactivates the B port word line wd_B (to low level). Set). Further, in response to the B port power cutoff signal B_PC, the B port power cutoff circuit B_PWN blocks the supply of the power supply voltage Vdd to the B port I / O unit B_PT and the B port control circuit B_CTL.

  Mode switching control circuit MS_CTL2A and mode switching control circuit MS_CTL2B according to the second embodiment further output A port bit line precharge signal RSAP and B port bit line precharge signal RSBP. The B port bit line precharge circuit B_PG disposed adjacent to the A port I / O circuit A_IO and the A port bit line precharge circuit A_PG disposed adjacent to the B port I / O circuit B_IO are respectively B In response to the port bit line precharge signal RSBP and the A port bit line precharge signal RSAP, the B port bit line and the A port bit line are precharged for a predetermined time.

  With reference to FIG. 10, the configuration of A port bit line precharge circuit A_PG and B port bit line precharge circuit B_PG according to the second embodiment will be described.

  The A port bit line precharge circuit A_PG is composed of p-type MOS transistors M1a and M2a. The sources of p-type MOS transistors M1a and M2a are connected in common to node Nb, and their drains are connected to A port bit lines blt_A and blb_A, respectively. The conduction state of p-type MOS transistors M1a and M2a is controlled by A port bit line precharge signal RSAP applied in common to its gates. When the A port is set to the standby mode, the A port bit line precharge signal RSAP maintains the low level, and the p-type MOS transistors M1a and M2b are in the conductive state (the B port bit line precharge circuit B_PG is in the conductive state). maintain. The p-type MOS transistor Mpcb controls the supply of the power supply voltage Vdd to the B port I / O circuit B_IO in response to the B port power supply cutoff signal B_PC.

  B port bit line precharge circuit B_PG is formed of p-type MOS transistors M1b and M2b. The sources of p-type MOS transistors M1b and M2b are connected in common with node Na, and their drains are connected to B port bit lines blt_B and blb_B, respectively. The conduction state of p-type MOS transistors M1b and M2b is controlled by B port bit line precharge signal RSBP applied in common to the gates thereof. When the B port is set to the standby mode, the B port bit line precharge signal RSBP is maintained at the low level, and the p-type MOS transistors M1b and M2b are in the conductive state (the B port bit line precharge circuit B_PG is in the conductive state). maintain. The p-type MOS transistor Mpca controls the supply of the power supply voltage Vdd to the A port I / O circuit A_IO in response to the A port power supply cutoff signal A_PC.

  The A port I / O circuit A_IO and the B port I / O circuit B_IO are arranged at positions facing each other across the memory cell array MA, and each of the A port bit line blt_A / blb_A and the B port bit line blt_B / blb_B. Connected to one end. The A port bit line precharge circuit A_PG and the B port bit line precharge circuit B_PG are connected to the other ends of the A port bit line blt_A / blb_A and the B port bit line blt_B / blb_B, respectively.

  The B port bit line precharge circuit B_PG normally supplies the power supply voltage Vdd that the p-type MOS transistor Mpca supplies to the A port I / O circuit A_IO when the A port is first set from the standby mode to the normal operation mode. This circuit applies a predetermined period to the bit line blt_B / blb_B of the B port in a state before returning to the operation mode. Hereinafter, in order to avoid duplication explanation due to the subjectivity of the circuits of the A port and the B port, only the explanation when the A port first returns from the standby mode to the normal operation mode will be described.

  When both the A port and the B port are in the standby mode, the p-type MOS transistors M1a and M2a are turned on when the A-port bit line precharge signal RSAP is at a low level, but the p-type MOS transistor Mpcb which is a power switch on the source side is turned off. Therefore, no charge is supplied to the bit line pair blt_A / blb_A and no precharge is performed. Similarly, p-type MOS transistors M1b and M2b are turned on when the B port bit line precharge signal RSBP is at a low level, but no charge is supplied to the bit line pair blt_B / blb_B because the p-type MOS transistor Mpca is non-conductive. There is no precharge.

  When the A port is first set to the normal operation mode, supply of the power supply voltage Vdd to the A port I / O circuit A_IO and the like via the p-type MOS transistor Mpca is started. The A port bit line precharge circuit A_PG is turned off, the A port bit lines blt_A and blb_A are precharged (controlled) from the A port I / O circuit, and the A port I / O circuit A_IO, etc. As a result of starting the supply of the power supply voltage Vdd to the A port peripheral circuit, the A port of the memory cell MC becomes accessible.

  On the other hand, since the standby mode is maintained for the B port, the B port bit line precharge signal RSBP is low and M1b and M2b are conductive. Further, since the p-type MOS transistor Mpca, which is the power switch of the A port, becomes conductive, charges are supplied to the bit line pair blt_B / blb_B of the B port and precharged.

  Thereafter, when the B port is also set in the normal operation mode, supply of the power supply voltage Vdd to the B port peripheral circuit such as the B port I / O circuit B_IO via the p-type MOS transistor Mpcb is started. The B port bit line precharge circuit B_PG is turned off, the B port bit line pair blt_B and blb_B are precharged (controlled) from the B port I / O circuit, and further, the B port I / O circuit B_IO, etc. As a result of starting the supply of the power supply voltage Vdd to the peripheral circuit of the B port, the B port of the memory cell MC becomes accessible.

  With reference to FIG. 11, operations of the A port bit line precharge circuit A_PG and the B port bit line precharge circuit B_PG according to the second embodiment will be described.

  The vertical axis in FIG. 11 schematically shows waveforms of signals related to the mode switching control circuit MS_CTL2A and the mode switching control circuit MS_CTL2B. In the case of a signal having a binary value, “0” means a low level and “1” means a high level. The horizontal axis indicates time.

  When the mode setting signal RSA changes from the low level to the high level at time t1a and the A port is set to the standby mode, the A port power cut-off signal A_PC inverts the logic level and supplies the power supply voltage Vdd to the A port peripheral circuit. Shut off the supply. Further, the A port bit line precharge signal RSAP also inverts the logic level, and the A port bit line precharge circuit A_PG becomes conductive. The node Na changes from a state where the power supply voltage Vdd is applied to a floating state.

  When the mode setting signal RSA changes from the high level to the low level at time t2a and the A port is set to the normal operation mode, the A port power cut-off signal A_PC inverts the logic level and supplies the power supply voltage Vdd to the A port peripheral circuit. Supply is started. As a result, the node Na becomes a state where the power supply voltage Vdd is applied from the floating state. At time t4a after the elapse of a delay time appropriately set from time t2a, the A port bit line precharge signal RSAP inverts the logic level, and the A port bit line precharge circuit A_PG is in a non-conduction state (release state). Become.

  When the mode setting signal RSB changes from the low level to the high level at time t1b and the B port is set to the standby mode, the supply of the power supply voltage Vdd to the peripheral circuit of the B port is cut off similarly to the A port, and the node Nb Floating state. Further, the B port bit line precharge circuit B_PG becomes conductive.

  When the mode setting signal RSB changes from the high level to the low level at time t2b and the B port is also set in the normal operation mode, the power shutoff signal B_PC of the B port inverts the logic level, and the power supply voltage to the B port peripheral circuit Vdd supply is started. As a result, the node Nb is in a state where the power supply voltage Vdd is applied from the floating state. At time t4b after the elapse of a delay time appropriately set from time t2b, the B port bit line precharge signal RSBP inverts the logic level, and the B port bit line precharge circuit B_PG becomes non-conductive (released). Become.

  Here, the operation of the B port bit line precharge circuit B_PG will be described. In the A port previously set to the normal state, when the power supply voltage Vdd is applied to the node Na after time t2a, the B port bit line blt_B is turned on by the B port bit line precharge circuit B_PG in the conductive state. And blb_B are precharged to the power supply voltage Vdd. The supply of the A port power supply voltage Vdd to the B port bit line is maintained until the B port bit line precharge circuit B_PG is turned off (time t4b).

  In other words, the B port precharge circuit B_PG is a circuit for eliminating the influence of noise or the like that occurs when the bit line pair of the B port is in a floating state during normal operation in the A port that has been restored from the standby mode. In particular, the influence of noise such as a transient current that occurs during the recovery of the B port that recovers later is also eliminated.

  The operation of the dual port memory DP_SRAM according to the second embodiment will be described with reference to FIG.

  The vertical axis in FIG. 12 represents a mode setting signal RSA and a clock CLKA that are input signals to the mode switching control circuit MS_CTL2A, an A port bit line precharge signal RSAP and an A port word line suppression signal A_WC that are output signals, and The waveform of the A port power cutoff signal A_PC is schematically shown. Similarly, mode setting signal RSB and clock CLKB which are input signals of mode switching control circuit MS_CTL2B, B port bit line precharge signal RSBP, B port word line suppression signal B_WC, and B port power supply cutoff signal which are output signals The waveform of B_PC is shown typically. Furthermore, a signal RSAB that is an input signal of the mode switching control circuit MS_CTL2C, a standby signal STB that is an output signal, and a voltage Vssc waveform of the cell power supply wiring ssc are schematically shown.

  When mode setting signal RSA changes from low level to high level at time t5, A port word line suppression signal A_WC and A port power shutoff signal A_PC change from low level to high level, and A port word line wd_A is inactivated, Supply of the power supply voltage Vdd to the A port peripheral circuit is cut off. Further, the A port bit line precharge signal RSAP changes to the low level. In this case, the potential of the node Na (see FIG. 10) is in a floating state. Thereafter, the port A shifts to the standby mode at time t7.

  When the mode setting signal RSB changes from low level to high level at time t6, the B port word line suppression signal B_WC and the B port power cut-off signal B_PC change from low level to high level, the B port word line wd_B is inactivated, Supply of the power supply voltage Vdd to the B port peripheral circuit is cut off. Further, the B port bit line precharge signal RSBP changes to the low level. In this case, the potential of the node Nb (see FIG. 10) is in a floating state. Thereafter, the port B shifts to the standby mode at time t8.

  Unlike the dual port memory DP_SRAM according to the first embodiment, when the A port and the B port are set to the standby mode by the mode setting signal RSA and the mode setting signal RSB, sequentially to the A port peripheral circuit and the B port peripheral circuit. The supply of the power supply voltage Vdd is cut off. The A port word line wd_A and the B port word line wd_B are also sequentially deactivated. When both the A port and the B port are set to the standby mode at time t6, the signal RSAB changes to a high level, and the standby signal STB changes to a low level based on the change. As a result, the voltage of the cell power supply wiring ssc rises by ΔVssc from the power supply voltage Vss, and the leakage current of the dual port memory DP_SRAM that has shifted to the standby mode is suppressed.

  When the A port is set to the normal operation mode at the time t11, the supply of the power supply voltage to the A port peripheral circuit is resumed, and the word line wd_A of the A port is released from the inactive state. Further, at time t11a, the A port bit line precharge signal RSAP becomes high level. When the B port is set to the normal operation mode at time t12, the supply of the power supply voltage to the B port peripheral circuit is resumed, and the word line wd_B of the B port is released from the inactive state. Further, at time t12a, the B port bit line precharge signal RSBP becomes high level.

  When both the A port and the B port are set to the standby mode at time t6, the voltage Vssc of the cell power supply wiring ssc rises by ΔVssc from the power supply voltage Vss based on the signal RSAB. When the A port is first set to the normal operation mode at time t11, the voltage Vssc of the cell power supply wiring ssc returns to the power supply voltage Vss based on the signal RSAB.

The effect of the semiconductor device LSI according to the second embodiment will be described.
In the dual port memory DP_SRAM, an A port I / O unit A_PT and a B port I / O unit B_PT are respectively arranged on two opposite sides of the memory cell array MA, and power supply wiring for supplying a power supply voltage to peripheral circuits of each port Are separated for each port. By separating the power supply wiring, even if the supply of the power supply voltage Vdd to the A port and B port set to the standby mode is sequentially cut off, it is possible to minimize the influence of noise caused by the power cut on each other port. It becomes possible. Furthermore, the power consumption caused by the peripheral circuits of each port is further reduced by cutting off the power supply voltage supply to each port in the order set in the standby mode without waiting until the time when both ports are set to the standby mode. It becomes possible.

  The A port I / O circuit A_IO and the B port I / O circuit B_IO each include a precharge circuit B_PG and a precharge circuit A_PG. With this circuit, the power supply voltage Vdd of the other port previously set to the normal operation mode is applied to the bit line of one port that is returning from the standby mode to the normal operation mode. As a result, it is possible to prevent malfunction due to the influence of noise received by the other port that has previously shifted from the standby mode to the normal operation mode.

<Modification of Embodiment 2>
With reference to FIG. 13, the configuration of a dual port memory DP_SRAM according to a modification of the second embodiment will be described.

The difference from the dual port memory DP_SRAM according to the second embodiment shown in FIG. 8 is the arrangement of the A port word line selection circuit A_WX and the B port word line selection circuit B_WX. As shown in FIG. 13, the A port word line selection circuit A_WX and the B port word line selection circuit B_WX are arranged so as to be offset toward one side of the memory cell array MA. With this arrangement, the A port I / O unit A_PT and the A port word line selection circuit A_WX can be arranged adjacent to the A port control unit APT_CTL. Similarly, B port I / O unit B_PT
In addition, the B port word line selection circuit B_WX can be arranged adjacent to the B port control unit BPT_CTL.

  The configuration and operation of each circuit block shown in FIG. 13 are the same as the configuration and operation of the circuit block given the same symbol shown in FIG. According to the dual port memory DP_SRAM according to the modification of the second embodiment, the control unit PT_CTL can be arranged for each port, and the circuit layout and circuit operation of each port can be optimized. It becomes possible.

<Embodiment 3>
The configuration of the semiconductor device LSI according to the third embodiment will be described with reference to FIG.

  The semiconductor device LSI includes a first functional block FB_A, a second functional block FB_B, an inter-port operation determination circuit 40, a first clock control circuit 41, a second clock control circuit 42, and a dual port memory DP_SRAM. The functions of the first functional block FB_A, the second functional block FB_B, and the dual port memory DP_SRAM are the same as those in the first embodiment. The dual port memory DP_SRAM includes a memory unit MP4 and a mode switching control circuit MS_CTL4.

  The first functional block FB_A and the second functional block FB_B output the mode setting signal RSA and the mode setting signal RSB for the dual port memory DP_SRAM to the inter-port operation determination circuit 40. The mode setting signals RSA and RSB respectively request the normal operation mode or standby mode setting for the A port and B port of the dual port memory DP_SRAM. The first clock control circuit 41 and the second clock control circuit 42 supply the clock CLKA and the clock CLKB to the A port and B port circuits of the dual port memory DP_SRAM, respectively, based on the clock S_CLKA and the clock S_CLKB.

  When the inter-port operation determination circuit 40 detects that both the first functional block FB_A and the second functional block FB_B request the standby mode based on the mode setting signals RSA and RSB, the mode of the signal RS is switched. Output to the control circuit MS_CTL4. The inter-port operation determination circuit 40 further controls the operation of the first clock control circuit 41 and the second clock control circuit 42, and the first functional block FB_A and the second functional block FB_B are the A port and the B port. The generation of the clock CLKA and the clock CLKB is controlled according to the operation mode requested.

The operation of the semiconductor device LSI according to the third embodiment will be described with reference to FIG.
The vertical axis in FIG. 15 schematically shows the waveforms of the clock CLKA / CLKB and the operation control signals CENA / CENB input to the A port and the B port of the dual port memory DP_SRAM. Furthermore, the waveforms of the output signals of the signal RS input to the mode switching control circuit MS_CTL4, the standby signal STB, the cell power supply voltage Vssc, and the AB port power supply cutoff signal AB_PC are schematically shown.

  When the A port is set to the standby mode by the mode setting signal RSA after the B port, the inter-port operation determination circuit 40 shifts both ports to the standby mode via the transition mode. While the A port and the B port are in the transition mode, the first clock control circuit 41 and the second clock control circuit 42 fix the clock CLKA and the clock CLKB to low level, respectively. Stopping the supply of the clock CLKA and the clock CLKB prevents the dual port memory DP_SRAM from malfunctioning during the transitional period from the normal operation mode to the standby mode. In the transition mode, the clock CLKA and the clock CLKB may be fixed at a high level.

  When both the A port and the B port are set to the standby mode, the signal RS changes from the low level to the high level at time t3. Based on this change, the standby signal STB changes to the low level, the cell power supply voltage Vssc rises by ΔVssc from the power supply voltage Vss, and the leakage current of the memory cell array MA included in the memory unit MP4 is suppressed. Further, the AB port power supply cutoff signal AB_PC changes to high level, the supply of the power supply voltage Vdd to the peripheral circuits of the A port and B port of the memory unit MP4 is cut off, and the power supply current in the standby mode is suppressed. At time t4, the dual port memory DP_SRAM shifts to the standby mode.

  When at least one of the A port and the B port is set to the normal operation mode, the signal RS changes from the high level to the low level at time t6. Based on this change, the standby signal STB changes to high level, and the cell power supply voltage Vssc returns to the power supply voltage Vss. Further, the AB port power supply cutoff signal AB_PC changes to the low level, and the supply of the power supply voltage Vdd to the peripheral circuits of the A port and B port of the memory unit MP4 is resumed.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  STB, / STB standby signal, A_PC A port power shutdown signal, A_PG A port bit line precharge circuit, AB_PC AB port power shutdown signal, AB_WC AB port word line suppression signal, ADDA, ADDB address, B_PC B port power shutdown signal, B_PG B port bit line precharge circuit, B_WC B port word line suppression signal, blt_A, blb_A A port bit line, blt_B, blb_B B port bit line, bn, bp power supply wiring, CENA, CENB operation control signal, S_CLKA, S_CLKB, CLKA, CLKB clock, CTLA, CTLB control signal, DA, DB input data, dd power supply wiring, ddc cell power supply wiring, DP_SRAM dual port memory, LSI multiport memory Semiconductor device including memory, MA memory cell array, MC memory cell, MP1, MP2, MP4 memory part, MSA mode setting signal, Na, Nb node, QA, QB output data, RS, RSAB signal, RSAP A port bit line precharge Signal, RSB mode setting signal, RSBP B port bit line precharge signal, ss power supply wiring, ssc cell power supply wiring, Vdd, Vss power supply voltage, Vssc voltage, wd_A A port word line, wd_B B port word line.

Claims (14)

A memory cell array having a plurality of memory cells each having a first and a second power supply node;
A cell power supply line connected to the first power supply node of each of the plurality of memory cells;
A first port and a second port for selecting the memory cell based on a first address and a second address respectively supplied;
A cell power supply voltage control circuit that is connected to the first power supply wiring and the cell power supply wiring and controls the voltage of the cell power supply wiring;
A mode switching control circuit that generates a first control signal based on a first operation mode setting signal and a second operation mode setting signal that respectively set an operation mode of the first port and the second port;
The cell power supply voltage control circuit sets the voltage of the cell power supply wiring to the first voltage level when at least one of the first port and the second port is in a normal operation mode based on the first control signal. When both the first port and the second port are in the standby mode, the voltage of the cell power supply line is changed from the first voltage level in a direction approaching the voltage of the second power supply node. A semiconductor device including a multiport memory that is set to a voltage level. The first port and the second port each have a selection circuit that selects the memory cell based on the first address and the second address,
When the first port and the second port are both set to a standby mode, the mode switching control circuit cuts off the power supply voltage supply to the selection circuit that each of the first port and the second port has In other cases, the semiconductor device having a multi-port memory according to claim 1, wherein the power supply voltage supply to the selection circuit included in each of the first port and the second port is maintained. The mode switching control circuit controls power supply voltage supply to the selection circuit of the first port and the selection circuit of the second port based on the first operation mode setting signal and the second operation mode setting signal. Further generating a second control signal;
When the first port and the second port are sequentially set to a standby mode based on the first operation mode setting signal and the second operation mode setting signal, the mode switching control circuit is configured so that the second port is in a standby mode. 3. The semiconductor device comprising a multi-port memory according to claim 2, wherein power supply voltage supply to the selection circuits included in each of the first port and the second port is simultaneously cut off after the mode is set. The first port and the second port each have a selection circuit that selects the memory cell based on the first address and the second address,
The mode switching control circuit cuts off supply of power supply voltage to the selection circuit of each of the first port and the second port when both the first port and the second port are set to the standby mode. When one of the first port and the second port is set to the standby mode and the other is set to the normal operation mode, the power supply voltage is supplied to the selection circuit of the port on the side set to the standby mode. The semiconductor device comprising a multi-port memory according to claim 1, wherein power supply voltage supply to the selection circuit of the port on the side where the normal operation mode is set is maintained. The mode switching control circuit is configured to control a power supply voltage supply to the selection circuit of the first port based on the first operation mode setting signal and the second operation mode setting signal based on the second operation mode setting signal. Further generating a fourth control signal for controlling supply of a power supply voltage to the selection circuit having two ports;
When the first port and the second port are sequentially set to a standby mode based on the third control signal and the fourth control signal, the mode switching control circuit includes the selection circuit included in the first port, and 5. The semiconductor device including a multi-port memory according to claim 4, wherein power supply voltage supply to the selection circuit included in the second port is cut off in that order. The memory cell is connected to a first port word line, a first port bit line pair, a second port word line, and a second port bit line pair;
The selection circuit of the first port includes a first word line selection circuit and a first bit line pair access circuit;
The selection circuit of the second port includes a second word line selection circuit and a second bit line pair access circuit;
The first bit line pair access circuit and the second bit line pair access circuit are arranged on two opposite sides of the memory cell array, and each of one end of the bit line pair of the first port and the second port 5. A semiconductor device comprising a multi-port memory according to claim 4, connected to one end of a bit line pair.   The first word line selection circuit and the second word line selection circuit are opposite to the other two sides intersecting the two sides on which the first bit line pair access circuit and the second bit line pair access circuit are arranged. 7. A semiconductor device comprising a multi-port memory according to claim 6, wherein the semiconductor devices are arranged in the same manner and are respectively connected to one end of the first port word line and one end of the second port word line. A first port bit line pair precharge circuit connected to the other end of the first port bit line pair; and a second port bit line pair precharge circuit connected to the other end of the bit line pair of the second port; With
The mode switching control circuit is configured to control a second control mode based on the second operation mode setting signal and a fifth control signal for controlling a conduction state of the first port bit line pair precharge circuit based on the first operation mode setting signal. 7. A semiconductor device comprising a multi-port memory according to claim 6, wherein a sixth control signal for controlling a conduction state of the port bit line pair precharge circuit is generated. The first port and the second port operate based on a first clock and a second clock, respectively;
2. The semiconductor device comprising a multi-port memory according to claim 1, wherein the supply of the first clock or the second clock to the first port or the second port set in a standby mode is stopped.   In the cell power supply voltage control circuit, when both the first port and the second port are in a normal operation mode, one of the first port and the second port is in a normal operation mode, and the other is in a standby mode. 2. The semiconductor device comprising a multi-port memory according to claim 1, wherein in the mode, the voltage of the cell power supply wiring is set to the first voltage level. A memory cell array having a plurality of memory cells each having first and second power supply nodes;
A cell power supply line connected to the first power supply node of each of the plurality of memory cells;
A first port and a second port for selecting the memory cell based on a first address and a second address respectively supplied;
A cell power supply voltage control circuit having a power switch connected to the first power supply wiring and the cell power supply wiring;
A mode switching control circuit that generates a first control signal based on a first operation mode setting signal and a second operation mode setting signal that respectively set an operation mode of the first port and the second port;
Based on the first control signal, the power switch is in a conductive state when at least one of the first port and the second port is in a normal operation mode, and both the first port and the second port are in a standby mode. In some cases, a semiconductor device including a multi-port memory is turned off. The first port and the second port each have a selection circuit that selects the memory cell based on the first address and the second address,
When the first port and the second port are both set to a standby mode, the mode switching control circuit cuts off the power supply voltage supply to the selection circuit that each of the first port and the second port has In other cases, the semiconductor device having a multi-port memory according to claim 11, wherein the power supply voltage supply to the selection circuit included in each of the first port and the second port is maintained. The first port and the second port each have a selection circuit that selects the memory cell based on the first address and the second address,
The mode switching control circuit cuts off supply of power supply voltage to the selection circuit of each of the first port and the second port when both the first port and the second port are set to the standby mode. When one of the first port and the second port is set to the standby mode and the other is set to the normal operation mode, the power supply voltage is supplied to the selection circuit of the port on the side set to the standby mode. 12. The semiconductor device comprising a multi-port memory according to claim 11, wherein the power supply voltage supply to the selection circuit of the port on the side where the normal operation mode is set is maintained.   In the cell power supply voltage control circuit, when both the first port and the second port are in a normal operation mode, one of the first port and the second port is in a normal operation mode, and the other is in a standby mode. 12. The semiconductor device comprising a multiport memory according to claim 11, wherein in the mode, the voltage of the cell power supply wiring is set to the first voltage level.

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