JP2019087300A - Semiconductor storage device - Google Patents

Abstract

To provide a semiconductor storage device including a plurality of low power consumption modes.SOLUTION: A semiconductor storage device comprises a plurality of memory modules which can set and cancel a plurality of low power consumption modes on the basis of a first and a second control signal. At least some memory modules among the plurality of memory modules include a propagation path for propagating the first control signal to be input to subsequent memory modules. The second control signal is parallelly input to each of the plurality of memory modules. Each memory module sets and cancels a first low power consumption mode on the basis of a combination of the first and second control signals propagated through the propagation path. Each memory module subsequently sets and cancels a first low power consumption mode and a second low power consumption mode having a power supply shutdown region different from the first lower power consumption mode according to the first control signal propagated through the propagation path.SELECTED DRAWING: Figure 1

Description

  The present disclosure relates to a semiconductor memory device in which a plurality of memory modules having a low power consumption mode are formed.

  When the low power consumption mode set in the semiconductor memory device is released, the supply of power to the circuit whose power supply has been stopped is started, and the operation of the circuit whose operation is stopped is resumed. The ground level may rise undesirably. This may cause a failure due to electromigration or may cause a malfunction due to a change in logic threshold level. In particular, when the storage capacity of a memory module mounted in a semiconductor memory device increases, a particularly large inrush current occurs when the low power consumption state of many memory modules is released. Various techniques have been proposed for reducing the occurrence of inrush current when the low power consumption mode is released.

  In this respect, Patent Document 1 proposes a method of releasing the low power consumption mode by delaying the control signal and propagating it to the memory module in the subsequent stage.

JP 2013-25843 A

  On the other hand, in recent years, by providing a plurality of low power consumption modes, it has become possible to operate the semiconductor storage device efficiently according to the situation.

  However, providing a wire for delaying the control signal for each low power consumption mode complicates the circuit design and places an excessive burden on the product design.

  Other problems and novel features will be apparent from the description of the present specification and the accompanying drawings.

  According to one embodiment, the semiconductor memory device includes a plurality of memory modules capable of setting and releasing a plurality of low power consumption modes based on the first and second control signals. At least a part of the plurality of memory modules has a propagation path for propagating the input first control signal to the subsequent memory module. The second control signal is input in parallel to each of the plurality of memory modules. Each memory module performs setting and cancellation of the first low power consumption mode based on the combination of the first control signal and the second control signal propagated by the propagation path. In each memory module, setting and cancellation of the second low power consumption mode different from the first low power consumption mode and the second low power consumption mode are sequentially performed according to the first control signal propagated through the propagation path.

  According to one embodiment, it is possible to perform the setting and cancellation of a plurality of low power consumption modes according to the combination of the propagating first control signal and the second control signal.

FIG. 1 is a diagram for describing an outline of a semiconductor memory device based on Embodiment 1. It is a figure explaining a plurality of low power consumption modes. 5 is a diagram for explaining functional blocks of a memory module MM based on Embodiment 1. FIG. FIG. 5 is a diagram for explaining a circuit configuration related to power supply of a memory module MM based on Embodiment 1. FIG. 7 is a diagram for describing a timing chart for explaining a low power consumption mode of the memory module MM based on the first embodiment. FIG. 7 is a diagram for explaining functional blocks of a memory module MMA based on Embodiment 2. FIG. 7 is a diagram for explaining a circuit configuration related to power supply of a memory module MMA based on Embodiment 2. FIG. 18 is a diagram for describing a timing chart for explaining a low power consumption mode of the memory module MMA based on the second embodiment. FIG. 18 is a diagram for explaining functional blocks of a memory module MMB based on Embodiment 3. FIG. 17 is a diagram for explaining a circuit configuration related to power supply of a memory module MMB based on the third embodiment. FIG. 18 is a diagram for describing a timing chart for explaining a low power consumption mode of the memory module MMB based on the third embodiment. FIG. 18 is a diagram for explaining a circuit configuration related to power supply of the memory module MMC based on the fourth embodiment. FIG. 16 is a diagram for describing a configuration of a latch LT based on Embodiment 4. FIG. 7 is a diagram for explaining a timing chart for explaining the operation of the latch LT. FIG. 18 is a diagram for explaining a circuit configuration related to power supply of a memory module MMD based on the fifth embodiment. It is a figure explaining the timing chart of control signal RSO adjusted by switching of selector SL. FIG. 18 is a diagram for describing an outline of a configuration of a memory array based on Embodiment 6. FIG. 18 is a diagram for explaining a circuit configuration related to power supply of the memory module MME based on the sixth embodiment. FIG. 18 is a diagram for explaining a timing chart of control signals according to the sixth embodiment. FIG. 21 is a diagram for explaining a circuit configuration related to power supply of a memory module MMF based on the seventh embodiment. FIG. 21 is a diagram for explaining functional blocks of a memory module MMG based on Embodiment 8. FIG. 35 is a diagram for explaining functional blocks of a memory module MMG # based on another mode of the eighth embodiment. FIG. 21 is a diagram for explaining functional blocks of a memory array and peripheral circuits according to a ninth embodiment. FIG. 21 is a diagram for explaining timing charts of various control signals based on the ninth embodiment.

  Embodiments will be described in detail with reference to the drawings. In the drawings, the same or corresponding portions are denoted by the same reference characters, and the description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a diagram for explaining the outline of a semiconductor memory device based on the first embodiment.

  As shown in FIG. 1, the semiconductor memory device TP is provided with a plurality of memory modules MM1 to MM6 (hereinafter, also collectively referred to as memory modules MM).

  In this example, each memory module MM is configured to be able to set and release a plurality of low power consumption modes.

  Specifically, each memory module MM is provided with inputs 1 to 3 and setting of a plurality of low power consumption modes according to control signals of first to third inputs respectively given to the inputs 1 to 3 , Is configured to be able to release.

  As an example, the control signal of the first input is input to the input 1 of the memory module MM1, and output from the output 1 through the propagation path in the memory module. The control signal of the first input becomes a delayed signal due to the propagation path. The output 1 is connected to the input 1 of the subsequent memory module MM2. The control signal input to the input 1 of the memory module MM2 is output from the output 1 via the propagation path in the memory module. Similarly, the output 1 is connected to the input 1 of the subsequent memory module MM3. Thereafter, similarly, the delayed control signal is propagated and input to the memory module MM in the subsequent stage.

  The memory modules MM4 to MM6 have the same connection as to the control signal of the first input inputted to the input 1.

  The control signal of the second input is input in parallel to the input 2 of each memory module.

  The control signal of the third input is input in parallel to the input 3 of each memory module.

  In this example, a method of executing setting and cancellation of a plurality of low power consumption modes based on a plurality of control signals for a plurality of memory modules MM included in a semiconductor memory device TP will be described.

FIG. 2 is a diagram for explaining a plurality of low power consumption modes.
FIG. 2A shows a memory module MM in the normal mode.

  Memory module MM mainly includes a memory array and peripheral circuits for driving the memory array.

  In the normal mode, normal power is supplied to each of the memory array and the peripheral circuits.

In the case of the low power consumption mode, the area and / or the amount to which power is supplied are different.
FIG. 2B shows the memory module MM in the first low power consumption mode.

  The first low power consumption mode shuts off power supply between the memory array and the peripheral circuits. In this case, since the power supply is cut off, the information in the memory array is lost.

FIG. 2C shows the memory module MM in the second low power consumption mode.
The second low power consumption mode shuts off the power supply of the peripheral circuits. Lower the power supply for the memory array. In this case, the power supply to the memory array is maintained, and thus information can be retained.

FIG. 2D shows the memory module MM in the third low power consumption mode.
The third low power consumption mode shuts off the power supply of the peripheral circuits. It is assumed that normal power is supplied to the memory array. Normal power supply is maintained for the memory array as compared to the second low power supply mode. Therefore, when returning to the normal mode, it is possible to shorten the recovery time because only the peripheral circuit recovers the power supply.

FIG. 2E shows the memory module MM in the fourth low power consumption mode.
The fourth low power consumption mode is a normal power supply for peripheral circuits. Power supply to the memory array is cut off. Normal power supply is maintained for peripheral circuits as compared to the second low power consumption mode. Therefore, when returning to the normal mode, it is possible to shorten the recovery time because only the memory array recovers the power supply.

In the fourth low power consumption mode, information in the memory array is not held.
FIG. 3 is a diagram for explaining functional blocks of the memory module MM based on the first embodiment.

  As shown in FIG. 3, memory module MM controls power supply of memory array MA, peripheral circuit PC, memory power control circuit VC for controlling power supply of memory array MA, and peripheral circuit PC. And a peripheral power control circuit PVC.

  Memory power supply control circuit VC is connected to power supply voltage VDD and ground voltage VSS, and controls voltages of memory power supply line ARVDD and memory ground line ARVSS according to control signal RS of the first input and control signal SDM of the second input. Do.

  Peripheral power control circuit PVC is connected to power supply voltage VDD and ground voltage VSS, and controls voltages of peripheral power supply line LCVDD and peripheral ground line LCVSS according to control signal RS of the first input and control signal FRS of the third input. Do. Specifically, peripheral power control circuit PVC receives an output from NOR circuit NR with respect to the input of control signal RS and control signal FRS, and controls the voltages of peripheral power supply line LCVDD and peripheral ground line LCVSS.

  In the memory module MM, a propagation path for propagating the control signal RS of the first input is provided, and the control signal RS is output to the outside as the control signal RSO. Specifically, an OR circuit R is provided which receives an input of control signal RS and an input of control signal RS via delay element DL, and control signal RSO is output from OR circuit R. The control signal RSO is input as the control signal RS of the first input of the memory module MM in the subsequent stage as described above. Here, although an example in which a delay element DL configured by two inverters is provided in the propagation path will be described, the delay element is not limited to this, and a delay element for adjusting the delay amount may be further provided. It is possible. The control signal RSO rises in the same manner as the rising of the control signal RS from the “L” level to the “H” level, and the falling of the “H” level to the “L” level is delayed according to the delay amount of the delay element DL. become.

  In the present embodiment, the memory module MM performs setting and cancellation of the first low power consumption mode based on a combination of the control signal RS of the first input and the control signal SDM of the second input.

  The memory module MM performs setting and cancellation of the second low power consumption mode based on the input of the control signal RS of the first input.

  The memory module MM performs setting and cancellation of the third low power consumption mode based on the input of the control signal FRS of the third input.

  FIG. 4 is a diagram for explaining a circuit configuration related to power supply of the memory module MM based on the first embodiment.

  As shown in FIG. 4, peripheral circuit PC is connected to peripheral power supply line LCVDD and peripheral ground line LCVSS. As peripheral power supply control circuit PVC, an N channel MOS transistor SW1 is provided between peripheral ground line LCVSS and ground voltage VSS, and N channel MOS transistor SW1 receives an output signal of NOR circuit NR.

  NOR circuit NR receives the input of control signal RS and control signal FRS, and outputs the result of the NOR logical operation to N channel MOS transistor SW1.

Control signal RS and control signal FRS are at the "L" level in the initial state.
Therefore, NOR circuit NR outputs a signal of "H" level to N channel MOS transistor SW1. Therefore, in the initial state, N channel MOS transistor SW1 is in the on state, and peripheral ground line LCVSS is connected to ground voltage VSS.

  On the other hand, when either control signal RS or control signal FRS is activated to "H" level, NOR circuit NR outputs a signal of "L" level to N channel MOS transistor SW1. Therefore, N channel MOS transistor SW1 is turned off, and peripheral ground line LCVSS is connected to and separated from ground voltage VSS.

  Memory array MA includes a plurality of memory cells MC. In this example, one memory cell MC is shown.

  Each memory cell MC is connected to a memory power supply line ARVDD and a memory ground line ARVSS. The memory cell MC is a six transistor static random access memory (SRAM) cell. Specifically, P channel MOS transistor PT1 and N channel MOS transistor NT1 are connected between memory power supply line ARVDD and memory ground line ARVSS. P channel MOS transistor PT2 and N channel MOS transistor NT2 are connected between memory power supply line ARVDD and memory ground line ARVSS.

  The gates of P channel MOS transistor PT1 and N channel MOS transistor NT1 are connected to the connection node of P channel MOS transistor PT2 and N channel MOS transistor NT2. Further, the connection node is connected to the access transistor AT2.

  The gates of P channel MOS transistor PT2 and N channel MOS transistor NT2 are connected to the connection node of P channel MOS transistor PT1 and N channel MOS transistor NT1. Further, the connection node is connected to the access transistor AT1.

It is a normal SRAM cell, and the detailed description of its operation etc. is omitted.
As the memory power supply control circuit VC, AND circuits AD1 and AD2, P channel MOS transistors SW2 and SW3, and N channel MOS transistors SW4 to SW6 are provided.

  P-channel MOS transistor SW2 is provided between power supply voltage VDD and memory power supply line ARVDD, and its gate receives the output of AND circuit AD1. The AND circuit AD1 receives the control signal SDM and the control signal RS, and outputs the result of the AND logic operation to the gates of the P channel MOS transistor SW2 and the N channel MOS transistor SW6.

  N channel MOS transistor SW4 is provided between memory ground line ARVSS and ground voltage VSS, and its gate is connected to node N1.

  N channel MOS transistor SW5 is provided between memory ground line ARVSS and node N1, and its gate receives the output of AND circuit AD2.

  N channel MOS transistor SW6 is provided between ground voltage VSS and node N1, and its gate receives the output of AND circuit AD1.

  P-channel MOS transistor SW3 is provided between power supply voltage VDD and node N1, and its gate receives an input of control signal RS.

  AND circuit AD2 receives the input of the inverted signal of control signal SDM and the input of control signal RS, and outputs the result of the AND logic operation to the gate of N channel MOS transistor SW5.

Control signal RS and control signal SDM are at the "L" level in the initial state.
Therefore, the AND circuit AD1 outputs a signal at the "L" level to the P-channel MOS transistor SW2. Therefore, in the initial state, P channel MOS transistor SW2 is in the on state, and peripheral power supply line LCVDD is connected to power supply voltage VDD.

  The P-channel MOS transistor SW3 is in the on state, and the node N1 is connected to the power supply voltage VDD and is set to the "H" level.

  Therefore, N channel MOS transistor SW4 is in the on state, and peripheral ground line LCVSS is connected to ground voltage VSS.

  On the other hand, since the outputs of AND circuits AD1 and AD2 are at the "L" level, N channel MOS transistors SW5 and SW6 are both off.

  Next, when control signal SDM is at "L" level and control signal RS is activated to "H" level, P channel MOS transistor SW3 is turned off. AND circuit AD1 maintains the "L" level, and P channel MOS transistor SW2 is in the on state. N channel MOS transistor SW6 is in the off state.

  The AND circuit AD2 is set to the "H" level, and the N-channel MOS transistor SW5 is turned on. Therefore, node N1 is connected to memory ground line ARVSS. N-channel MOS transistor SW4 is in a diode-connected state in which the source and gate are connected, and the potential of memory ground line ARVSS is set to a state slightly raised from ground voltage VSS (the state is high). . As a result, it is possible to reduce the leakage current of the memory cell MC and reduce the power consumption.

  Next, when control signal SDM is at "H" level and control signal RS is activated to "H" level, P channel MOS transistor SW3 is turned off. AND circuit AD1 is set to "H" level, and P channel MOS transistor SW2 is turned off. Also, the N channel MOS transistor SW6 is turned on. Therefore, node N1 is connected to ground voltage VSS. Therefore, N channel MOS transistor SW4 is turned off. AND circuit AD2 is set to "L" level, and N channel MOS transistor SW5 is turned off.

  Thereby, P channel MOS transistor SW2 and N channel MOS transistor SW4 are turned off, and the power supply of memory array MA is cut off.

  FIG. 5 is a diagram for explaining a timing chart for explaining the low power consumption mode of the memory module MM based on the first embodiment.

  As shown in FIG. 5, the case where control signal FRS is activated to "H" level at time T1 is shown. Accordingly, it is shown that peripheral ground line LCVSS is in contact with ground voltage VSS and the potential of peripheral ground line LCVSS is in a high impedance (Hi-Z) state.

  On the other hand, memory ground line ARVSS is kept connected to ground voltage VSS.

  As a result, the power supply of the peripheral circuits is cut off, and the memory array can be set to the third low power consumption mode maintaining the normal power supply.

  A case where control signal FRS is deactivated at time T1 # is shown. A case where peripheral ground line LCVSS is connected to ground voltage VSS is shown.

  The return operation from the third low power consumption mode to the normal mode restores the power supply to the peripheral circuits, and the power to be restored is small, so the return operation is performed at high speed without considering the inrush current. Is possible.

  It is shown that control signal RS is activated to "H" level at time T2. Accordingly, it is shown that peripheral ground line LCVSS is in contact with ground voltage VSS and the potential of peripheral ground line LCVSS is in a high impedance (Hi-Z) state.

  The memory ground line ARVSS is in a state in which the N-channel MOS transistor SW4 is diode-connected, and is set to a state slightly higher than the ground voltage VSS (a state in which the potential is high).

  Thereby, the power supply of the peripheral circuit is shut off, and the memory array can be set to the second low power consumption mode in which the power supply is reduced compared to the normal power supply.

  The case where the control signal RS is inactivated at time T3 is shown. A case where peripheral ground line LCVSS is connected to ground voltage VSS is shown. Further, a case is shown in which memory ground line ARVSS is connected to ground voltage VSS.

  Further, the control signal RSO is a signal obtained by delaying the control signal RS, and it is shown that the control signal RSO is deactivated at time T4. Since the control signal RSO is output to the subsequent memory module, the return operation from the second low power consumption mode to the normal mode is performed stepwise from the previous memory module to the subsequent memory module. Therefore, it is possible to alleviate the occurrence of inrush current when the low power consumption mode is released.

  It is shown that control signal SDM is activated to "H" level at time T5. In this case, the control signal SDM alone does not shift to the low power consumption mode.

  The case where the control signal RS is activated at time T6 is shown. Accordingly, it is shown that peripheral ground line LCVSS is in contact with ground voltage VSS and the potential of peripheral ground line LCVSS is in a high impedance (Hi-Z) state.

  In the memory ground line ARVSS, the N channel MOS transistor SW6 is turned on, and the N channel MOS transistor SW4 is turned off. Therefore, it is shown that memory ground line ARVSS is in contact with and separated from ground voltage VSS, and the potential of memory ground line ARVSS is in a high impedance (Hi-Z) state.

  Thus, the power supply of the peripheral circuits and the memory array is shut off, and the first low power consumption mode can be set.

  At time T7, the case where the control signal RS is inactivated is shown. A case where peripheral ground line LCVSS is connected to ground voltage VSS is shown. Further, a case is shown in which memory ground line ARVSS is connected to ground voltage VSS.

  Further, the control signal RSO is a signal obtained by delaying the control signal RS, and the case where the control signal RSO is deactivated at time T8 is shown. Since the control signal RSO is output to the memory module in the subsequent stage, the recovery operation from the first low power consumption mode to the normal mode is performed stepwise from the memory module in the former stage to the memory module in the subsequent stage. Therefore, it is possible to alleviate the occurrence of inrush current when the low power consumption mode is released.

  As described above, the memory module MM performs setting and cancellation of the first low power consumption mode based on the combination of the control signal RS of the first input and the control signal SDM of the second input. In addition, the memory module MM executes setting and cancellation of the second low power consumption mode based on the input of the control signal RS of the first input. Also, the memory module MM executes setting and cancellation of the third low power consumption mode based on the input of the control signal FRS of the third input.

  The return operation from the first and second low power consumption modes to the normal mode is performed in accordance with the control signal RS and the control signal RSO which is a delay signal thereof. That is, the recovery operation is performed stepwise from the memory module of the former stage to the memory module of the latter stage.

  That is, it is not necessary to generate a delay signal obtained by delaying the control signal for each of the plurality of low power consumption modes, but by setting and canceling the low power consumption mode based on a combination with one delay signal, It is possible to mitigate the occurrence of inrush current when each of the plurality of low power consumption modes is released.

  As a result, it is not necessary to provide a wire for delaying the control signal for each low power consumption mode, and it is possible to design a circuit with a simple configuration, and it is possible to reduce the burden of product design.

Second Embodiment
FIG. 6 is a diagram for explaining functional blocks of the memory module MMA based on the second embodiment.

  As shown in FIG. 6, the memory module MMA is different from the memory module MM described in FIG. 3 in that a Q latch QL is further provided.

  The Q latch QL has a function of holding data output from the memory array MA.

  In this example, peripheral power supply control circuit PVC1 for controlling power supply of peripheral circuits PC other than Q latch QL, and peripheral power supply control circuit PVC2 for controlling power supply of Q latch QL are provided. .

  Peripheral power control circuit PVC1 is connected to power supply voltage VDD and ground voltage VSS, and controls voltages of peripheral power supply line LCVDD1 and peripheral ground line LCVSS1 according to control signal RS of the first input and control signal FRS of the third input. Do. Specifically, peripheral power control circuit PVC1 receives an output from circuit NR # in response to the input of control signal RS and control signal FRS, and controls the voltages of peripheral power supply line LCVDD1 and peripheral ground line LCVSS1.

  Peripheral power control circuit PVC2 is connected to power supply voltage VDD and ground voltage VSS, and controls the voltages of peripheral power supply line LCVDD2 and peripheral ground line LCVSS2 according to control signal RS of the first input.

  The other configuration is the same as that of the memory module described in FIG. 3, and therefore, detailed description thereof will not be repeated.

  FIG. 7 is a diagram for explaining a circuit configuration related to power supply of the memory module MMA based on the second embodiment.

  As shown in FIG. 7, in the memory module MMA, the configurations of the memory array MA and the memory power control circuit VC are the same as those of the circuit configuration described in FIG. 4 and the other configurations are different.

Specifically, circuit NR # is provided instead of NOR circuit NR.
Further, the configurations of the Q latch QL and the peripheral power control circuit PVC2 are newly provided.

  Peripheral power supply lines and peripheral ground lines are provided with peripheral power supply line LCVDD1 and peripheral ground line LCVSS1 corresponding to peripheral circuit PC. Further, peripheral power supply line LCVDD2 and peripheral ground line LCVSS2 are provided corresponding to Q latch QL.

  N-channel MOS transistor SW1 is provided between peripheral ground line LCVSS1 and ground voltage VSS, and the gate of N-channel MOS transistor SW1 is connected to node N2 of circuit NR #.

  Circuit NR # includes a P channel MOS transistor 10 and N channel MOS transistors 11 and 12.

  P channel MOS transistor 10 is provided between power supply voltage VDD and node N2, and has its gate receiving an input of control signal FRS.

  N channel MOS transistor 11 is provided between peripheral ground line LCVSS1 and node N2, and its gate receives an input of control signal FRS.

  N channel MOS transistor 12 is provided between ground voltage VSS and node N2, and its gate receives an input of control signal RS.

Control signal RS and control signal FRS are at the "L" level in the initial state.
Therefore, circuit NR # outputs a signal of "H" level to N channel MOS transistor SW1. Therefore, in the initial state, N channel MOS transistor SW1 is in the on state, and peripheral ground line LCVSS is connected to ground voltage VSS.

  When control signal RS is activated to "H" level, N channel MOS transistor 12 is turned on, N channel MOS transistor SW1 is turned off, and peripheral ground line LCVSS1 is connected to and separated from ground voltage VSS. .

  When control signal FRS is activated to "H" level, N channel MOS transistor 11 is turned on. Thus, node N2 and peripheral ground line LCVSS1 are connected. N-channel MOS transistor SW1 is in a diode-connected state in which the source and gate are connected, and the potential of peripheral ground line LCVSS1 is set to a state slightly raised from ground voltage VSS (the state is high). .

  FIG. 8 is a diagram for explaining a timing chart for explaining the low power consumption mode of the memory module MMA based on the second embodiment.

  As shown in FIG. 8, the case where control signal FRS is activated to "H" level at time T10 is shown. Along with this, the N channel MOS transistor 11 is turned on. Therefore, N-channel MOS transistor SW1 is in a diode-connected state in which the source and gate are connected, and the potential of peripheral ground line LCVSS1 is set to a state slightly higher than ground voltage VSS (the state is high). Be done.

Peripheral ground line LCVSS2 maintains a state connected to ground voltage VSS.
Thereby, the power supply of peripheral circuit PC is reduced. A third low power mode can be set that maintains normal power supply for the Q latch and the memory array.

  At time T11, there is shown a case where control signal FRS is inactivated. A case where peripheral ground line LCVSS1 is connected to ground voltage VSS is shown.

  The return operation from the third low power consumption mode to the normal mode restores the power supply to the peripheral circuits, and since the power to be restored is small and the inrush current is small, it is possible to execute the recovery operation at high speed. is there.

  In the third low power consumption mode in this example, the power supply is reduced only in a partial region of the peripheral circuit, and in the other, the normal power supply is maintained.

  It is shown that control signal RS is activated to "H" level at time T12. Along with this, it is shown that peripheral ground line LCVSS1 is in contact with and separated from ground voltage VSS, and the potential of peripheral ground line LCVSS1 is in a high impedance (Hi-Z) state.

  Further, it is shown that peripheral ground line LCVSS2 is disconnected from ground voltage VSS, and the potential of peripheral ground line LCVSS2 is in a high impedance (Hi-Z) state.

  The memory ground line ARVSS is in a state in which the N-channel MOS transistor SW4 is diode-connected, and is set to a state slightly higher than the ground voltage VSS (a state in which the potential is high).

  Thereby, the power supply of the peripheral circuits and the Q latch is cut off, and the memory array can be set to the second low power consumption mode in which the power supply is reduced compared to the normal power supply.

  The case where the control signal RS is deactivated at time T13 is shown. Along with this, it is shown that peripheral ground lines LCVSS1 and LCVSS2 are connected to ground voltage VSS. Further, a case is shown in which memory ground line ARVSS is connected to ground voltage VSS.

  The control signal RSO is a signal obtained by delaying the control signal RS, and the case where the control signal RSO is inactivated at time T14 is shown. Since the control signal RSO is output to the subsequent memory module, the return operation from the second low power consumption mode to the normal mode is performed stepwise from the previous memory module to the subsequent memory module. Therefore, it is possible to alleviate the occurrence of inrush current when the low power consumption mode is released.

  It is shown that control signal SDM is activated to "H" level at time T15. In this case, the control signal SDM alone does not shift to the low power consumption mode.

  At time T16, the case where the control signal RS is activated is shown. Accordingly, it is shown that peripheral ground lines LCVSS1 and LCVSS2 are connected to and separated from ground voltage VSS, and the potentials of peripheral ground lines LCVSS1 and LCVSS2 are in a high impedance (Hi-Z) state.

  In the memory ground line ARVSS, the N channel MOS transistor SW6 is turned on, and the N channel MOS transistor SW4 is turned off. Therefore, it is shown that memory ground line ARVSS is in contact with and separated from ground voltage VSS, and the potential of memory ground line ARVSS is in a high impedance (Hi-Z) state.

  As a result, the power supply of the peripheral circuits, the Q latch and the memory array is cut off, and the first low power consumption mode can be set.

  The case where the control signal RS is inactivated at time T17 is shown. Along with this, it is shown that peripheral ground lines LCVSS1 and LCVSS2 are connected to ground voltage VSS. Further, a case is shown in which memory ground line ARVSS is connected to ground voltage VSS.

  The control signal RSO is a signal obtained by delaying the control signal RS, and the case where the control signal RSO is inactivated at time T18 is shown. Since the control signal RSO is output to the memory module in the subsequent stage, the recovery operation from the first low power consumption mode to the normal mode is performed stepwise from the memory module in the former stage to the memory module in the subsequent stage. Therefore, it is possible to alleviate the occurrence of inrush current when the low power consumption mode is released.

  As described above, the memory module MMA performs setting and cancellation of the first low power consumption mode based on the combination of the control signal RS of the first input and the control signal SDM of the second input. Also, the memory module MMA executes setting and cancellation of the second low power consumption mode based on the input of the control signal RS of the first input. Further, the memory module MMA executes setting and cancellation of the third low power consumption mode based on the input of the control signal FRS of the third input.

  The return operation from the first and second low power consumption modes to the normal mode is performed in accordance with the control signal RS and the control signal RSO which is a delay signal thereof. That is, the recovery operation is performed stepwise from the memory module of the former stage to the memory module of the latter stage.

  That is, it is not necessary to generate a delay signal obtained by delaying the control signal for each of the plurality of low power consumption modes, but by setting and canceling the low power consumption mode based on a combination with one delay signal, It is possible to mitigate the occurrence of inrush current when each of the plurality of low power consumption modes is released.

  As a result, it is not necessary to provide a wire for delaying the control signal for each low power consumption mode, and it is possible to design a circuit with a simple configuration, and it is possible to reduce the burden of product design.

(Embodiment 3)
FIG. 9 is a diagram for explaining functional blocks of the memory module MMB based on the third embodiment.

  As shown in FIG. 9, the memory module MMB is different from the memory module MM described in FIG. 3 in that the OR circuit OR is provided instead of the NOR circuit NR, and the control signal input is different.

Specifically, the control signal RS is input to the peripheral power control circuit PVC.
The memory power control circuit VC receives an output signal of an OR circuit OR of the control signal FRS and the control signal RS.

  In this example, peripheral power supply control circuit PVC1 is connected to power supply voltage VDD and ground voltage VSS, and controls the voltages of peripheral power supply line LCVDD1 and peripheral ground line LCVSS1 according to control signal RS of the first input.

  The memory power supply control circuit VC receives an output from the OR circuit OR in response to the input of the control signal RS and the control signal FRS, and controls the voltages of the memory power supply line ARVDD and the memory ground line ARVSS. The other configuration is the same as that of the memory module described in FIG. 3, and therefore, detailed description thereof will not be repeated.

  FIG. 10 is a diagram for explaining a circuit configuration related to power supply of the memory module MMB based on the third embodiment.

  As shown in FIG. 10, the memory module MMB differs from the circuit configuration described in FIG. 4 in the inputs of the memory power control circuit VC and the peripheral power control circuit PVC.

  Specifically, N channel MOS transistor SW1 of peripheral power supply control circuit PVC receives an input of a signal of control signal RS via inverter 15. Memory power supply control circuit VC receives an output of an OR logic operation result of OR circuit OR receiving the input of control signal FRS and control signal RS.

Control signal RS and control signal FRS are at the "L" level in the initial state.
Therefore, N channel MOS transistor SW1 is on, and peripheral ground line LCVSS is connected to ground voltage VSS.

  Next, when control signal SDM is at "L" level and control signal RS is activated to "H" level, N channel MOS transistor SW1 is turned off, and peripheral ground line LCVSS is at ground voltage VSS. And separated.

  When control signal RS is activated to "H" level, P channel MOS transistor SW3 is turned off. AND circuit AD1 maintains the "L" level, and P channel MOS transistor SW2 is in the on state. N channel MOS transistor SW6 is in the off state. The AND circuit AD2 is set to the "H" level, and the N-channel MOS transistor SW5 is turned on. Therefore, node N1 is connected to memory ground line ARVSS. N-channel MOS transistor SW4 is in a diode-connected state in which the source and gate are connected, and the potential of memory ground line ARVSS is set to a state slightly raised from ground voltage VSS (the state is high). . As a result, it is possible to reduce the leakage current of the memory cell MC and reduce the power consumption.

  Next, when control signal SDM is at "H" level and control signal RS is activated to "H" level, P channel MOS transistor SW3 is turned off. AND circuit AD1 is set to "H" level, and P channel MOS transistor SW2 is turned off. Also, the N channel MOS transistor SW6 is turned on. Therefore, node N1 is connected to ground voltage VSS. Therefore, N channel MOS transistor SW4 is turned off. AND circuit AD2 is set to "L" level, and N channel MOS transistor SW5 is turned off. Thereby, P channel MOS transistor SW2 and N channel MOS transistor SW4 are turned off, and the power supply of memory array MA is cut off.

  FIG. 11 is a diagram for explaining a timing chart for explaining the low power consumption mode of the memory module MMB based on the third embodiment.

  As shown in FIG. 11, the case where control signal FRS is activated to "H" level at time T20 is shown. Along with this, P channel MOS transistor SW3 is turned off. N-channel MOS transistor SW4 is in a diode-connected state in which the source and gate are connected, and the potential of memory ground line ARVSS is set to a state slightly raised from ground voltage VSS (the state is high). .

Peripheral ground line LCVSS maintains a state connected to ground voltage VSS.
Thereby, the power supply of memory array MA is reduced. The peripheral circuit PC can be set to a fourth low power consumption mode for reducing power supply.

  At time T21, there is shown a case where control signal FRS is inactivated. A case where memory ground line ARVSS is connected to ground voltage VSS is shown.

  The return operation from the fourth low power consumption mode to the normal mode restores the power supply to the memory array, and the return power is small and the inrush current is small, so that the return operation can be performed at high speed. .

  It is shown that control signal RS is activated to "H" level at time T22. Accordingly, it is shown that peripheral ground line LCVSS is in contact with ground voltage VSS and the potential of peripheral ground line LCVSS is in a high impedance (Hi-Z) state.

  The memory ground line ARVSS is in a state in which the N-channel MOS transistor SW4 is diode-connected, and is set to a state slightly higher than the ground voltage VSS (a state in which the potential is high).

  Thereby, the power supply of the peripheral circuit is shut off, and the memory array can be set to the second low power consumption mode in which the power supply is reduced compared to the normal power supply.

  The case where the control signal RS is deactivated at time T23 is shown. Along with this, it is shown that peripheral ground line LCVSS and memory power supply line ARVDD are connected to ground voltage VSS. Further, a case is shown in which memory ground line ARVSS is connected to ground voltage VSS.

  Further, the control signal RSO is a signal obtained by delaying the control signal RS, and the case where the control signal RSO is inactivated at time T24 is shown. Since the control signal RSO is output to the subsequent memory module, the return operation from the second low power consumption mode to the normal mode is performed stepwise from the previous memory module to the subsequent memory module. Therefore, it is possible to alleviate the occurrence of inrush current when the low power consumption mode is released.

  It is shown that control signal SDM is activated to "H" level at time T25. In this case, the control signal SDM alone does not shift to the low power consumption mode.

  At time T26, the case where control signal RS is activated to "H" level is shown. Accordingly, it is shown that peripheral ground line LCVSS is in contact with ground voltage VSS and the potential of peripheral ground line LCVSS is in a high impedance (Hi-Z) state.

  In the memory ground line ARVSS, the N channel MOS transistor SW6 is turned on, and the N channel MOS transistor SW4 is turned off. Therefore, it is shown that memory ground line ARVSS is in contact with and separated from ground voltage VSS, and the potential of memory ground line ARVSS is in a high impedance (Hi-Z) state.

  Thus, the power supply of the peripheral circuits and the memory array is shut off, and the first low power consumption mode can be set.

  The case where the control signal RS is inactivated at time T27 is shown. Along with this, it is shown that peripheral ground lines LCVSS1 and LCVSS2 are connected to ground voltage VSS. Further, a case is shown in which memory ground line ARVSS is connected to ground voltage VSS.

  Further, the control signal RSO is a signal obtained by delaying the control signal RS, and the case where the control signal RSO is inactivated at time T28 is shown. Since the control signal RSO is output to the memory module in the subsequent stage, the recovery operation from the first low power consumption mode to the normal mode is performed stepwise from the memory module in the former stage to the memory module in the subsequent stage. Therefore, it is possible to alleviate the occurrence of inrush current when the low power consumption mode is released.

  As described above, the memory module MMA performs setting and cancellation of the first low power consumption mode based on the combination of the control signal RS of the first input and the control signal SDM of the second input. Also, the memory module MMA executes setting and cancellation of the second low power consumption mode based on the input of the control signal RS of the first input. Further, the memory module MMA executes setting and cancellation of the fourth low power consumption mode based on the input of the control signal FRS of the third input.

  The return operation from the first and second low power consumption modes to the normal mode is performed in accordance with the control signal RS and the control signal RSO which is a delay signal thereof. That is, the recovery operation is performed stepwise from the memory module of the former stage to the memory module of the latter stage.

  That is, it is not necessary to generate a delay signal obtained by delaying the control signal for each of the plurality of low power consumption modes, but by setting and canceling the low power consumption mode based on a combination with one delay signal, It is possible to mitigate the occurrence of inrush current when each of the plurality of low power consumption modes is released.

  As a result, it is not necessary to provide a wire for delaying the control signal for each low power consumption mode, and it is possible to design a circuit with a simple configuration, and it is possible to reduce the burden of product design.

(Embodiment 4)
FIG. 12 is a diagram for explaining a circuit configuration related to power supply of the memory module MMC based on the fourth embodiment.

  As shown in FIG. 12, the memory module MMC differs from the circuit configuration described in FIG. 4 in that a latch LT is further provided. The other configuration is the same as that described with reference to FIG. 4 and thus the detailed description thereof will not be repeated.

  Specifically, memory power control circuit VC further includes a latch LT. Latch LT receives an input of control signal SDM and control signal RS.

  The latch LT outputs a latched control signal SDMI. The control signal SDMI is output to the AND circuits AD1 and AD2.

FIG. 13 is a diagram for explaining the configuration of the latch LT based on the fourth embodiment.
As shown in FIG. 13, latch LT includes P channel MOS transistors 20, 21, 23 and 24, N channel MOS transistors 22, 25 and 26, and an inverter 27.

  P-channel MOS transistors 20 and 21 are connected in series between power supply voltage VDD and node N3. The gate of P channel MOS transistor 20 receives an input of control signal RS. N channel MOS transistor 22 is provided between node N3 and ground voltage VSS, and has its gate receiving an input of control signal SDM.

  P channel MOS transistors 23 and 24 are connected in series between power supply voltage VDD and node N3.

  N channel MOS transistors 25 and 26 are connected in series between node N3 and ground voltage VSS.

  The gate of P channel MOS transistor 23 and the gate of N channel MOS transistor 26 receive the input of the output signal of inverter 27.

  The gate of P channel MOS transistor 24 receives an input of control signal SDM. The gate of N channel MOS transistor 25 receives an input of control signal RS.

  Inverter 27 is connected to node N3 and outputs control signal SDMI obtained by inverting the potential level of node N3.

The latch LT operates as a so-called single latch circuit.
FIG. 14 is a diagram for explaining a timing chart for explaining the operation of the latch LT.

  As shown in FIG. 14, the case where control signal SDM is activated to "H" level at time T30 is shown. Along with this, the N channel MOS transistor 22 is turned on. Therefore, node N 3 is set to “L” level, and control signal SDMI is set to “H” level. Also, along with this, the N channel MOS transistor 26 is turned on.

  Next, at time T30 #, the case where control signal RS is activated to "H" level is shown.

Along with this, the N channel MOS transistor 25 is turned on.
Therefore, since N channel MOS transistors 25 and 26 are turned on, the voltage level of node N3 is fixed at ground voltage VSS.

  Next, at time T31, the case where the control signal SDM is inactivated is shown. Along with this, the N channel MOS transistor 22 is turned off. P channel MOS transistor 21 is turned on. On the other hand, since node N3 is fixed at ground voltage VSS by N channel MOS transistors 25 and 26, control signal SDMI maintains the "H" level.

  Next, at time T32, the case where the control signal RS is inactivated is shown. Along with this, N channel MOS transistor 25 is turned off. P channel MOS transistor 20 is turned on. Therefore, node N3 is connected to power supply voltage VDD and set to "H" level. Control signal SDMI is set to "L" level.

  According to this configuration, after the control signal SDM is activated, the control signal SDMI maintains the activated state until the control signal RS is deactivated even if the control signal SDM is deactivated. Therefore, the first low power consumption mode will be continued.

  If control signal SDMI is inactivated along with inactivation of control signal SDM, control signal RS is set to "H" level, and therefore the possibility of transition to the second low power consumption mode is possible. However, this method makes it possible to prohibit the transition from the first low power consumption mode to the second low power consumption mode.

  This makes it possible to stably execute the setting and cancellation of the first low power consumption mode based on the combination of the control signal RS of the first input and the control signal SDM of the second input.

Embodiment 5
FIG. 15 is a diagram for explaining a circuit configuration related to power supply of the memory module MMD according to the fifth embodiment.

  As shown in FIG. 15, the memory module MMD differs from the circuit configuration described in FIG. 4 in that the propagation path for outputting the control signal RSO is changed. The other configurations are the same as those described above, and therefore the detailed description thereof will not be repeated.

Specifically, delay elements DL1 and DL2 and a selector SL are further provided.
Selector SL receives an input of control signal RS and control signal RS via delay element DL2. Then, the selector SL switches and outputs the input signal according to the control signal SDM.

  As an example, selector SL outputs control signal RS via delay element DL2 to delay element DL1 in accordance with control signal SDM at "H" level.

  On the other hand, selector SL outputs control signal RS to delay element DL1 according to control signal SDM at "L" level.

  Therefore, when the control signal SDM is at the “H” level, the control signal RSO delayed by the two stages of the delay elements DL1 and DL2 is output for the control signal RS.

  FIG. 16 is a diagram for explaining the timing chart of the control signal RSO adjusted by switching of the selector SL.

  As shown in FIG. 16, the case where control signal RS is activated to "H" level at time T40 is shown. In this case, it is assumed that control signal SDM is deactivated. Therefore, the selector SL outputs the control signal RS to the delay element DL1.

  The case where the control signal RS is inactivated at time T41 is shown. Then, at time T42, there is shown a case where the control signal RSO obtained by delaying the control signal RS via the delay element DL1 is inactivated.

  Next, at time T43, a case where control signal SDM is activated to "H" level is shown. Therefore, the selector SL switches the path so as to output the control signal RS delayed by the delay element DL2 to the delay element DL1.

  It is shown that control signal RS is activated to "H" level at time T44.

  It is shown that the control signal RS is deactivated at time T45. Then, at time T46, there is shown a case where the control signal RSO obtained by delaying the control signal RS via the delay elements DL1 and DL2 is inactivated.

It becomes possible to adjust the delay amount of the control signal RS by the method.
In the second low power consumption mode, the amount of power restored from the return operation of the first low power consumption mode is smaller. Therefore, since the second low power consumption mode can be restored at a higher speed, the delay amount is reduced, and the return time is longer when the first low power consumption mode is considering the inrush current. Therefore, it is possible to increase the delay amount.

Embodiment 6
FIG. 17 is a diagram for explaining an outline of a configuration of a memory array based on the sixth embodiment.

  As shown in FIG. 17, memory array MA is shown divided into a plurality of memory units.

  Specifically, a case where memory units MU1 to MU4 (hereinafter collectively referred to as memory unit MU) are divided is shown.

  The memory power control circuit VC is also divided into memory units.

  More specifically, memory power control units VCU1 to VCU4 (hereinafter collectively referred to as memory power control unit VCU) are provided corresponding to memory units MU1 to MU4, respectively.

  The OR circuit 42 receives the control signal RS and the delay signal of the control signal RS via the inverters 40 and 41, and outputs the OR logical operation result as a control signal RSO. A control line ARYSW for controlling the memory ground line ARVSS is provided between the inverters 40 and 41.

  FIG. 18 is a diagram for explaining a circuit configuration related to power supply of the memory module MME based on the sixth embodiment.

  As shown in FIG. 18, the memory module MME differs from the circuit configuration described in FIG. 4 in that the memory array MA is divided into a plurality of memory units MU as described above. Also, a memory power control unit VCU is provided corresponding to each memory unit MU.

  Each memory power supply control unit VCU differs from the configuration of FIG. 4 in that an N channel MOS transistor SW4 # is further provided. N channel MOS transistor SW4 # is provided between memory ground line ARVSS and ground voltage VSS, and its gate receives an input of an inverted signal of control signal RS via inverter 40. The other configurations are similar. A control line ARYSW which propagates the output signal of the inverter 40 is provided commonly to each memory power control unit VCU. Each N-channel MOS transistor SW4 # is assumed to be a large sized transistor.

FIG. 19 is a diagram for explaining a timing chart of control signals according to the sixth embodiment.
As shown in FIG. 19, it is shown that control signal RS is activated to "H" level at time T50. In this case, the potential of control line ARYSW is lowered gradually from the "H" level to the "L" level by the capacitive load of N channel MOS transistor SW4 # through inverter 40.

  Control signal RSO is activated to "H" level at substantially the same timing as the rise of control signal RS.

  The control signal RSD is a delay signal that delays the control signal RS in accordance with the capacitive load of the inverters 40 and 41 and the control line ARYSW.

  Control signal RSO is inactivated due to the fall ("L" level) of control signal RSD.

  With this configuration, since the capacitive load of the control line ARYSW affects the delay amount, it is possible to adjust the delay amount in accordance with the characteristics (capacitive load) of the memory module. For example, when the number of memory units MU is large, the amount of delay is large, and when the number of memory units MU is small, the amount of delay is small.

Seventh Embodiment
FIG. 20 is a diagram for explaining a circuit configuration related to power supply of the memory module MMF based on the seventh embodiment.

  As shown in FIG. 20, the memory module MMF differs from the memory module MM described in FIG. 4 in that an AND circuit 50 is further provided. The other configuration is the same as that described with reference to FIG. 4 and thus the detailed description thereof will not be repeated.

  The AND circuit 50 receives the test mode signal STM and the control signal FRS via the inverter 51, and outputs the result of the AND logic operation to the NOR circuit NR.

  The test mode signal STM is a signal input when executing a predetermined test mode. In the initial state, it is set to the "L" level, and in the case of the test mode, it is set to the "H" level.

  Therefore, when test mode signal STM is set to the “H” level, the output of AND circuit 50 is maintained at the “L” level even when control signal FRS is activated. . Therefore, when executing the predetermined test mode, transition to the third low power consumption mode in accordance with control signal FRS is prohibited.

By this method, processing in a predetermined test mode can be performed reliably.
(Embodiment 8)
FIG. 21 is a diagram for explaining functional blocks of a memory module MMG based on the eighth embodiment.

  As shown in FIG. 21, the memory module MMG is provided with a peripheral circuit for an independent two-port (A port and B port) memory array as compared with the memory module MM described in FIG. The case is shown.

  In this example, peripheral circuits PCA of port A and peripheral circuits PCB of port B are provided, and peripheral power control circuits are independently provided corresponding to the respective peripheral circuits.

  Specifically, an A-port peripheral power control circuit PVCA for controlling power supply to the A-port peripheral circuit PCA and a B-port peripheral power control circuit PVCB are provided. The configuration of each peripheral power control circuit is the same as that described in the first embodiment and the like.

  A NOR circuit NRA is provided corresponding to A port peripheral power supply control circuit PVCA of A port, and A port peripheral power supply control circuit PVCA is a NOR logic operation result of control signal FRSA for A port and control signal RS. It is controlled based on.

  In addition, NOR circuit NRB is provided corresponding to A port peripheral power supply control circuit PVCA of B port, and B port peripheral power supply control circuit PVCB is a NOR logic operation result of control signal FRSB for B port and control signal RS. It is controlled based on.

  According to the configuration, the low power consumption mode can be set and canceled independently for the multiport memory array.

  FIG. 22 is a diagram for explaining functional blocks of a memory module MMG # based on another mode of the eighth embodiment.

  As shown in FIG. 22, the memory module MMG is provided with a peripheral circuit for an independent two-port (A port and B port) memory array as compared with the memory module MM described in FIG. The case is shown.

  In this example, peripheral circuits PCA of port A and peripheral circuits PCB of port B are provided, and a common peripheral power control circuit PVC is provided corresponding to each peripheral circuit.

  Specifically, the configuration of the peripheral power control circuit is the same as that described in the first embodiment and the like.

  When the peripheral power supply control circuit is common, the control signal FRSA and the control signal FRSB are input to the AND circuit ADD, and the AND logic operation result is output to the NOR circuit NR.

  Peripheral power supply control circuit PVC is controlled based on the result of the NOR logic operation of NOR circuit NR receiving the output of AND circuit ADD and the input of control signal RS.

  According to this configuration, setting and cancellation of the third low power consumption mode can be performed when control signals FRSA and FRSB are both activated for the multiport memory array.

(Embodiment 9)
FIG. 23 is a diagram for explaining functional blocks of a memory array and peripheral circuits based on the ninth embodiment.

Referring to FIG. 23, functional blocks of memory array MA and peripheral circuits are shown.
As peripheral circuits, a word driver WD for driving the word lines WL of the memory array MA, a clock driver CD for driving a clock signal, and a power switch VSW for controlling supply of power to the peripheral circuits are provided.

  Clock driver CD receives an input of clock signal CLK and drives internal clock intCLK in accordance with control signal FRSE. When control signal FRSE is activated ("H" level), internal clock intCLK is driven.

  Word driver WD drives word line WL in accordance with an instruction when control signal FRSE is activated ("H" level).

  Power supply switch VSW controls power supply of peripheral circuits based on control signal FRS and internal clock intCLK. As an example, the voltage level of peripheral ground line LCVSS is set. Specifically, peripheral ground line LCVSS is connected to ground voltage GND when control signal FRS is at "L" level, and peripheral ground line LCVSS is connected to or separated from the ground voltage when control signal FRS is at "H" level. .

  NOR circuit NR # receives control signal FRS and control signal FRSDLY delayed by control signal FRS, and outputs the NOR logical operation result to word driver WD and clock driver CD as control signal FRSE.

  FIG. 24 is a diagram for explaining the timing chart of various control signals based on the ninth embodiment.

  As shown in FIG. 24, at time T60, when control signal FRSE is at "H" level, internal clock intCLK and word line WL are driven in synchronization with clock signal CLK.

  Similarly, at time T61, internal clock intCLK and word line WL are driven in synchronization with clock signal CLK.

  At time T62, when control signal FRS is activated to "H" level, control signal FRSE is set to "L" level. Along with this, at time T63, the driving of the word line WL and the internal clock intCLK is stopped.

  Then, at time T64, the peripheral ground line LCVSS is connected to and separated from the ground voltage VSS, and is set to the high impedance state (Hi-Z). The power supply switch VSW is controlled by the control signal FRS and the internal clock intCLK to control the connection between the peripheral ground line LCVSS and the ground voltage VSS, so that it is possible to prevent data destruction due to the unstable power supply.

Further, at time T65, the case where the control signal FRS is inactivated is shown.
Along with this, the peripheral ground line LCVSS is connected to the ground voltage VSS and returns from the low power consumption mode.

  The word driver WD and the clock driver CD are driven after the control signal FRSE is activated. Control signal FRSE is set to "H" level by inactivating control signal FRSDLY to "L" level. Since the control signal FRSDLY is a delay signal of the control signal FRS, the word driver WD and the clock driver CD are activated after the recovery operation is completed. Then, word line WL and internal clock intCLK are driven. Therefore, it is possible to prevent data corruption due to unstable power supply.

  As mentioned above, although this indication was concretely explained based on an embodiment, this indication is not limited to an embodiment, it can not be overemphasized that it can change variously in the range which does not deviate from the gist.

  FRS, RS, SDM control signal, MM, MMA, MMC, MMD, MME, MMF memory module, PC, PCA, PCB peripheral circuit, PVC, PVC1, PVC2 peripheral power control circuit, PVCA, PVCB port peripheral power control circuit, TP Semiconductor memory device, VC memory power control circuit.

Claims (10)

Have multiple memory modules,
Each of the memory modules receives first and second control signals via first and second inputs, and a plurality of low power consumption modes based on the first and second control signals. Can be set
At least a part of the memory modules of the plurality of memory modules have a propagation path for transmitting the input first control signal to another memory module,
The second control signal is input in parallel to each of the plurality of memory modules,
Each of the memory modules is set to a first low power consumption mode based on a combination of the first control signal propagating the propagation path and the second control signal.
Each of the memory modules is sequentially set to a second low power consumption mode according to the first control signal propagated through the propagation path;
The semiconductor memory device, wherein a region of the memory module whose power is shut off in the second low power consumption mode is different from a region of the memory module whose power is shut off in the first low power consumption mode.   Each of the plurality of memory modules receives an input of a third control signal for setting each of the memory modules to a third low power consumption mode different from the first and second low power consumption modes. The semiconductor memory device according to claim 1. Each of the memory modules includes a memory area and a peripheral area
3. The semiconductor memory device according to claim 2, wherein in the second low power consumption mode, power supply to a partial region of the peripheral region of each of the memory modules is shut off in accordance with the first control signal. Each of the memory modules includes a memory area and a peripheral area
In the second low power consumption mode, power in the peripheral area is shut off, and power in the memory area is reduced.
In the third low power consumption mode, only the power of the memory area is reduced.
The semiconductor memory device according to claim 1.   The first low power consumption mode is set according to the activation of the second control signal, and thereafter, inactivation of the first control signal independently of the second control signal. The semiconductor memory device according to claim 1, which is released accordingly.   The semiconductor memory device according to claim 1, wherein each of the memory modules further includes an adjustment circuit adjusting an amount of delay of a first control signal passing through a propagation path.   7. The semiconductor memory device according to claim 6, wherein said adjustment circuit adjusts a delay amount of said first control signal via said propagation path based on a control signal of a switch controlling a power supply line of each of said memory modules.   3. The semiconductor memory device according to claim 2, wherein each of said memory modules includes a prohibition circuit which prohibits reception of said third control signal during a test mode. Each of the memory modules includes a memory area and a peripheral area
The memory area includes a plurality of independently controllable ports,
The peripheral area is divided corresponding to each port,
The third control signal is provided to each port,
3. The semiconductor memory device according to claim 2, wherein in said third low power consumption mode, power is shut off for each of said peripheral regions divided into each of said ports. Have multiple memory modules,
Each of the memory modules is configured to receive first and second control signals via first and second inputs, and a plurality of low on the basis of the first and second control signals. Power consumption mode is set
Each memory module includes a memory area and a peripheral area
Some memory modules of the plurality of memory modules have a propagation path for transferring the input first control signal to another memory module,
The second control signal is input in parallel to each of the plurality of memory modules,
Each of the memory modules is configured to reduce power consumption of the memory area and the peripheral area based on a combination of the first control signal and the second control signal propagating through the propagation path. Set to power mode,
Each of the memory modules is sequentially set to a second low power consumption mode in which the power of the peripheral area is cut off and the power of the memory area is reduced according to the first control signal propagated through the propagation path. Semiconductor memory device.

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