JP6780041B2 - Semiconductor storage device - Google Patents

Description

The present disclosure relates to a semiconductor storage device in which a plurality of memory modules having a low power consumption mode are formed.

When the low power consumption mode set in the semiconductor storage device is released, the power supply to the circuit in which the power supply has been stopped is started, and the operation of the circuit in which the operation has been stopped is restarted. Inrush current is generated in the ground level, and the ground level rises undesirably. This may cause a failure due to electromigration, or cause a malfunction due to a fluctuation in the logical threshold level. In particular, when the storage capacity of the memory modules mounted on the semiconductor storage device increases, a particularly large inrush current is generated when the low power consumption state of many memory modules is released. Various techniques have been proposed for alleviating the generation of inrush current when the low power consumption mode is released.

In this respect, Patent Document 1 proposes a method of releasing the low power consumption mode by delaying a control signal and sequentially propagating it to a memory module in a subsequent stage.

Japanese Unexamined Patent Publication No. 2013-25843

On the other hand, in recent years, it has become possible to efficiently operate the semiconductor storage device according to the situation by providing a plurality of low power consumption modes.

However, providing wiring for delaying the control signal in each low power consumption mode complicates the circuit design and makes the burden of product design excessive.

Other challenges and novel features will become apparent from the description and accompanying drawings herein.

According to one embodiment, the semiconductor storage device includes a plurality of memory modules capable of setting and canceling a plurality of low power consumption modes based on the first and second control signals. At least a part of the memory modules has a propagation path for propagating the input first control signal to the subsequent memory module. The second control signal is input to the plurality of memory modules in parallel. Each memory module sets and cancels the first low power consumption mode based on the combination of the first control signal and the second control signal propagated by the propagation path. Each memory module sequentially sets and cancels the first low power consumption mode and the second low power consumption mode in which the area for shutting off the power supply is different according to the first control signal propagated by the propagation path.

According to one embodiment, it is possible to set and cancel a plurality of low power consumption modes according to the combination of the propagating first control signal and the second control signal.

It is a figure explaining the outline of the semiconductor storage device based on Embodiment 1. It is a figure explaining a plurality of low power consumption modes. It is a figure explaining the functional block of the memory module MM based on Embodiment 1. It is a figure explaining the circuit structure concerning the power supply of the memory module MM based on Embodiment 1. FIG. It is a figure explaining the timing chart explaining the low power consumption mode of the memory module MM based on Embodiment 1. FIG. It is a figure explaining the functional block of the memory module MMA based on Embodiment 2. It is a figure explaining the circuit structure concerning the power supply of the memory module MMA based on Embodiment 2. FIG. It is a figure explaining the timing chart explaining the low power consumption mode of the memory module MMA based on Embodiment 2. It is a figure explaining the functional block of the memory module MMB based on Embodiment 3. It is a figure explaining the circuit structure concerning the power supply of the memory module MMB based on Embodiment 3. It is a figure explaining the timing chart explaining the low power consumption mode of the memory module MMB based on Embodiment 3. It is a figure explaining the circuit structure concerning the power supply of the memory module MMC based on Embodiment 4. It is a figure explaining the structure of the latch LT based on Embodiment 4. It is a figure explaining the timing chart explaining the operation of the latch LT. It is a figure explaining the circuit structure which concerns on the power supply of the memory module MMD based on Embodiment 5. It is a figure explaining the timing chart of the control signal RSO adjusted by switching of a selector SL. It is a figure explaining the outline of the structure of the memory array based on Embodiment 6. It is a figure explaining the circuit structure which concerns on the power supply of the memory module MME based on Embodiment 6. It is a figure explaining the timing chart of the control signal based on Embodiment 6. It is a figure explaining the circuit structure which concerns on the power supply of the memory module MMF based on Embodiment 7. It is a figure explaining the functional block of the memory module MMG based on Embodiment 8. It is a figure explaining the functional block of the memory module MMG # based on another embodiment of Embodiment 8. It is a figure explaining the functional block of the memory array and the peripheral circuit based on Embodiment 9. It is a figure explaining the timing chart of various control signals based on Embodiment 9.

The embodiment will be described in detail with reference to the drawings. The same or corresponding parts in the drawings are designated by the same reference numerals, and the description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a diagram illustrating an outline of a semiconductor storage device based on the first embodiment.

As shown in FIG. 1, the semiconductor storage device TP is provided with a plurality of memory modules MM1 to MM6 (hereinafter, also collectively referred to as memory modules MM).

In this example, each memory module MM is configured so that a plurality of low power consumption modes can be set and canceled.

Specifically, each memory module MM is provided with inputs 1 to 3, and a plurality of low power consumption modes are set according to the control signals of the first input to the third input given to the inputs 1 to 3, respectively. , It is configured so that it can be released.

As an example, the control signal of the first input is input to the input 1 of the memory module MM1 and is output from the output 1 via the propagation path in the memory module. The control signal of the first input becomes a delayed signal due to the propagation path. The output 1 is connected to the input 1 of the memory module MM2 in the subsequent stage. The control signal input to the input 1 of the memory module MM2 is output from the output 1 via the propagation path in the memory module. Similarly, the output 1 is connected to the input 1 of the memory module MM3 in the subsequent stage. After that, the delayed control signal is propagated and input to the memory module MM in the subsequent stage in the same manner.

Regarding the control signal of the first input input to the input 1, the memory modules MM4 to MM6 have the same connection relationship.

Further, the control signals of the second input are input to the input 2 of each memory module in parallel.

Further, the control signals of the third input are input to the input 3 of each memory module in parallel.

In this example, a method of setting and canceling a plurality of low power consumption modes based on a plurality of control signals for a plurality of memory modules MM included in the semiconductor storage device TP will be described.

FIG. 2 is a diagram illustrating a plurality of low power consumption modes.
FIG. 2A shows the memory module MM in the normal mode.

The memory module MM mainly includes a memory array and peripheral circuits for driving the memory array.

In the normal mode, normal power is supplied to each of the memory array and peripheral circuits.

In the low power mode, the area and / or amount of power supplied is different.
FIG. 2B shows the memory module MM in the first low power consumption mode.

The first low power consumption mode cuts off the power supply of the memory array and the peripheral circuits, respectively. In this case, the power supply is cut off and the memory array information is lost.

FIG. 2C shows the memory module MM in the second low power consumption mode.
The second low power consumption mode cuts off the power supply of peripheral circuits. Lower the power supply for the memory array. In this case, the power supply to the memory array is maintained, so that the information can be retained.

FIG. 2D shows the memory module MM in the third low power consumption mode.
The third low power consumption mode cuts off the power supply of peripheral circuits. Normal power supply is used for the memory array. Compared with the second low power consumption mode, the normal power supply is maintained for the memory array. Therefore, when returning to the normal mode, the power supply is restored only to the peripheral circuit, so that the restoration time can be shortened.

FIG. 2E shows a fourth low power consumption mode memory module MM.
In the fourth low power consumption mode, the peripheral circuits are supplied with normal power. The power supply is cut off for the memory array. Compared with the second low power consumption supply mode, the normal power supply is maintained for the peripheral circuits. Therefore, when returning to the normal mode, the power supply is restored only to the memory array, so that the restoration time can be shortened.

In the fourth low power consumption mode, the memory array information is not retained.
FIG. 3 is a diagram illustrating a functional block of the memory module MM based on the first embodiment.

As shown in FIG. 3, the memory module MM controls the memory array MA, the peripheral circuit PC, the memory power supply control circuit VC for controlling the power supply of the memory array MA, and the power supply of the peripheral circuit PC. Includes peripheral power control circuit PVC for.

The memory power control circuit VC is connected to the power supply voltage VDD and the ground voltage VSS, and controls the voltages of the memory power supply line AR VDD and the memory ground line ARVSS according to the input control signal RS of the first input and the control signal SDM of the second input. To do.

The peripheral power supply control circuit PVC is connected to the power supply voltage VDD and the ground voltage VSS, and controls the voltages of the peripheral power supply line LC VDD and the peripheral ground line LCVSS according to the input control signal RS of the first input and the control signal FRS of the third input. To do. Specifically, the peripheral power supply control circuit PVC receives the output from the NOR circuit NR with respect to the input of the control signal RS and the control signal FRS, and controls the voltages of the peripheral power supply line LC VDD and the peripheral ground line LCVSS.

Further, a propagation path for propagating the control signal RS of the first input is provided in the memory module MM, and the control signal RS is output to the outside as a control signal RSO. Specifically, an OR circuit R that receives the input of the control signal RS and the input of the control signal RS via the delay element DL is provided, and the control signal RSO is output from the OR circuit R. As described above, the control signal RSO is input as the control signal RS of the first input of the memory module MM in the subsequent stage. Here, an example in which a delay element DL composed of two inverters is provided in the propagation path will be described, but the delay element is not limited to this, and a delay element for adjusting the delay amount may be further provided. It is possible. The control signal RSO rises in the same manner as the rise of the control signal RS from the “L” level to the “H” level, and the fall of the “H” level to the “L” level is delayed according to the delay amount of the delay element DL. become.

In this example, the memory module MM sets and cancels the first low power consumption mode based on the combination of the control signal RS of the first input and the control signal SDM of the second input.

The memory module MM sets and cancels the second low power consumption mode based on the input of the control signal RS of the first input.

The memory module MM sets and cancels the third low power consumption mode based on the input of the control signal FRS of the third input.

FIG. 4 is a diagram illustrating a circuit configuration related to power supply of the memory module MM based on the first embodiment.

As shown in FIG. 4, the peripheral circuit PC is connected to the peripheral power line LC VDD and the peripheral ground line LCVSS. As the peripheral power supply control circuit PVC, an N-channel MOS transistor SW1 is provided between the peripheral grounding line LCVSS and the grounding voltage VSS, and the N-channel MOS transistor SW1 receives an output signal of the NOR circuit NR.

The NOR circuit NR receives the input of the control signal RS and the control signal FRS, and outputs the NOR logic operation result to the N channel MOS transistor SW1.

The control signal RS and the control signal FRS are at the "L" level in the initial state.
Therefore, the NOR circuit NR outputs an “H” level signal to the N-channel MOS transistor SW1. Therefore, in the initial state, the N-channel MOS transistor SW1 is in the ON state, and the peripheral ground line LCVSS is connected to the ground voltage VSS.

On the other hand, when either the control signal RS or the control signal FRS is activated to the "H" level, the NOR circuit NR outputs the "L" level signal to the N-channel MOS transistor SW1. Therefore, the N-channel MOS transistor SW1 is turned off, and the peripheral ground line LCVSS is connected to and separated from the ground voltage VSS.

The memory array MA includes a plurality of memory cells MC. In this example, one memory cell MC is shown.

Each memory cell MC is connected to the memory power line AR VDD and the memory ground line ARVSS. As the memory cell MC, a 6-transistor SRAM (Static Random Access Memory) cell is shown. Specifically, the P-channel MOS transistor PT1 and the N-channel MOS transistor NT1 are connected between the memory power supply line AR VDD and the memory ground line ARVSS. The P-channel MOS transistor PT2 and the N-channel MOS transistor NT2 are connected between the memory power supply line AR VDD and the memory ground line ARVSS.

The gates of the P-channel MOS transistor PT1 and the N-channel MOS transistor NT1 are connected to the connection nodes of the P-channel MOS transistor PT2 and the N-channel MOS transistor NT2. Further, the connection node and the access transistor AT2 are connected.

The gates of the P-channel MOS transistor PT2 and the N-channel MOS transistor NT2 are connected to the connection nodes of the P-channel MOS transistor PT1 and the N-channel MOS transistor NT1. Further, the connection node and the access transistor AT1 are connected.

It is a normal SRAM cell, and detailed description of its operation and the like will be omitted.
AND circuits AD1 and AD2, P-channel MOS transistors SW2 and SW3, and N-channel MOS transistors SW4 to SW6 are provided as the memory power supply control circuit VC.

The P-channel MOS transistor SW2 is provided between the power supply voltage VDD and the memory power supply line AR VDD, and its gate receives the output of the AND circuit AD1. The AND circuit AD1 receives the inputs of the control signal SDM and the control signal RS, and outputs the AND logic operation result to the gates of the P-channel MOS transistor SW2 and the N-channel MOS transistor SW6.

The N-channel MOS transistor SW4 is provided between the memory ground line ARVSS and the ground voltage VSS, and its gate is connected to the node N1.

The N-channel MOS transistor SW5 is provided between the memory ground line ARVSS and the node N1, and its gate receives the output of the AND circuit AD2.

The N-channel MOS transistor SW6 is provided between the ground voltage VSS and the node N1, and its gate receives the output of the AND circuit AD1.

The P-channel MOS transistor SW3 is provided between the power supply voltage VDD and the node N1, and its gate receives the input of the control signal RS.

The AND circuit AD2 receives the input of the inverted signal of the control signal SDM and the input of the control signal RS, and outputs the AND logical operation result to the gate of the N-channel MOS transistor SW5.

The control signal RS and the control signal SDM are at the "L" level in the initial state.
Therefore, the AND circuit AD1 outputs an “L” level signal to the P-channel MOS transistor SW2. Therefore, in the initial state, the P-channel MOS transistor SW2 is in the ON state, and the peripheral power supply line LC VDD is connected to the power supply voltage VDD.

Further, the P-channel MOS transistor SW3 is in the ON state, and the node N1 is connected to the power supply voltage VDD and set to the “H” level.

Therefore, the N-channel MOS transistor SW4 is in the ON state, and the peripheral ground line LCVSS is connected to the ground voltage VSS.

On the other hand, since the outputs of the AND circuits AD1 and AD2 are at the “L” level, both the N-channel MOS transistors SW5 and SW6 are in the off state.

Next, when the control signal SDM is at the “L” level and the control signal RS is activated at the “H” level, the P-channel MOS transistor SW3 is turned off. The AND circuit AD1 maintains the “L” level, and the P-channel MOS transistor SW2 is in the ON state. The N-channel MOS transistor SW6 is in the off state.

The AND circuit AD2 is set to the “H” level, and the N-channel MOS transistor SW5 is turned on. Therefore, the node N1 and the memory ground line ARVSS are connected. The N-channel MOS transistor SW4 is in a diode-connected state in which the source and the gate are connected, and the potential of the memory ground line ARVSS is set to a state in which the potential is slightly raised from the ground voltage VSS (a state in which the potential is high). .. This makes it possible to reduce the leakage current of the memory cell MC and reduce the power consumption.

Next, when the control signal SDM is at the “H” level and the control signal RS is activated at the “H” level, the P-channel MOS transistor SW3 is turned off. The AND circuit AD1 is set to the "H" level, and the P-channel MOS transistor SW2 is turned off. Further, the N-channel MOS transistor SW6 is turned on. Therefore, the node N1 and the ground voltage VSS are connected. Therefore, the N-channel MOS transistor SW4 is turned off. The AND circuit AD2 is set to the “L” level, and the N-channel MOS transistor SW5 is turned off.

As a result, the P-channel MOS transistor SW2 and the N-channel MOS transistor SW4 are turned off, and the power supply of the memory array MA is cut off.

FIG. 5 is a diagram illustrating a timing chart for explaining the low power consumption mode of the memory module MM based on the first embodiment.

As shown in FIG. 5, the case where the control signal FRS is activated to the “H” level at time T1 is shown. Along with this, the case where the peripheral ground line LCVSS is separated from the ground voltage VSS and the potential of the peripheral ground line LCVSS is in a high impedance (Hi-Z) state is shown.

On the other hand, the memory ground wire ARVSS is maintained in a state of being connected to the ground voltage VSS.

As a result, the power supply of the peripheral circuit is cut off, and the memory array can be set to the third low power consumption mode in which the normal power supply is maintained.

The case where the control signal FRS is deactivated at time T1 # is shown. Along with this, the case where the peripheral ground line LCVSS is connected to the ground voltage VSS is shown.

The return operation from the third low power consumption mode to the normal mode restores the power supply to the peripheral circuits, and since the power to be restored is small, the return operation should be executed at high speed without considering the inrush current. Is possible.

At time T2, the case where the control signal RS is activated to the "H" level is shown. Along with this, the case where the peripheral ground line LCVSS is separated from the ground voltage VSS and the potential of the peripheral ground line LCVSS is in a high impedance (Hi-Z) state is shown.

Further, the memory ground wire ARVSS is set in a state in which the N-channel MOS transistor SW4 is connected by a diode and is slightly raised above the ground voltage VSS (a state in which the potential is high).

As a result, the power supply of the peripheral circuit is cut off, and the memory array can be set to the second low power consumption mode in which the power supply is reduced as compared with the normal power supply.

The case where the control signal RS is deactivated at time T3 is shown. Along with this, the case where the peripheral ground line LCVSS is connected to the ground voltage VSS is shown. Further, the case where the memory ground wire ARVSS is connected to the ground voltage VSS is shown.

Further, the control signal RSO is a signal in which the control signal RS is delayed, and the case where the control signal RS is deactivated at time T4 is shown. Since the control signal RSO is output to the memory module in the subsequent stage, the return operation from the second low power consumption mode to the normal mode is performed stepwise from the memory module in the previous stage to the memory module in the subsequent stage. Therefore, it is possible to mitigate the generation of inrush current when the low power consumption mode is released.

At time T5, the case where the control signal SDM is activated to the "H" level is shown. In this case, the control signal SDM alone does not shift to the low power consumption mode.

The case where the control signal RS is activated at time T6 is shown. Along with this, the case where the peripheral ground line LCVSS is separated from the ground voltage VSS and the potential of the peripheral ground line LCVSS is in a high impedance (Hi-Z) state is shown.

Further, in the memory ground line ARVSS, the N-channel MOS transistor SW6 is turned on and the N-channel MOS transistor SW4 is turned off. Therefore, the case where the memory ground line ARVSS is separated from the ground voltage VSS and the potential of the memory ground line ARVSS is in a high impedance (Hi-Z) state is shown.

As a result, the power supply of the peripheral circuits and the memory array is cut off, and it is possible to set the first low power consumption mode.

The case where the control signal RS is deactivated at time T7 is shown. Along with this, the case where the peripheral ground line LCVSS is connected to the ground voltage VSS is shown. Further, the case where the memory ground wire ARVSS is connected to the ground voltage VSS is shown.

Further, the control signal RSO is a signal in which the control signal RS is delayed, and the case where the control signal RS is deactivated at time T8 is shown. Since the control signal RSO is output to the memory module in the subsequent stage, the return operation from the first low power consumption mode to the normal mode is performed stepwise from the memory module in the previous stage to the memory module in the subsequent stage. Therefore, it is possible to mitigate the generation of inrush current when the low power consumption mode is released.

As described above, the memory module MM sets and cancels the first low power consumption mode based on the combination of the control signal RS of the first input and the control signal SDM of the second input. Further, the memory module MM sets and cancels the second low power consumption mode based on the input of the control signal RS of the first input. Further, the memory module MM sets and cancels the third low power consumption mode based on the input of the control signal FRS of the third input.

Then, the return operation from the first and second low power consumption modes to the normal mode is performed according to the control signal RS and the control signal RSO which is a delay signal thereof. That is, the return operation is performed stepwise from the memory module in the front stage to the memory module in the rear stage.

That is, it is not necessary to generate a delay signal in which the control signal is delayed for each of the plurality of low power consumption modes, and the low power consumption mode is set and canceled based on the combination with one delay signal. It is possible to mitigate the generation of inrush current when each of the plurality of low power consumption modes is canceled.

As a result, it is not necessary to provide wiring for delaying the control signal for each low power consumption mode, circuit design with a simple configuration is possible, and the burden of product design can be reduced.

(Embodiment 2)
FIG. 6 is a diagram illustrating a functional block of the memory module MMA based on the second embodiment.

As shown in FIG. 6, the memory module MMA is different from the memory module MM described with reference to FIG. 3 in that a Q latch QL is further provided.

The Q-latch QL has a function of holding the data output from the memory array MA.

In this example, a peripheral power supply control circuit PVC1 for controlling the power supply of the peripheral circuit PC other than the Q-latch QL and a peripheral power supply control circuit PVC2 for controlling the power supply of the Q-latch QL are provided. ..

The peripheral power supply control circuit PVC1 is connected to the power supply voltage VDD and the ground voltage VSS, and controls the voltages of the peripheral power supply line LC VDD1 and the peripheral ground line LCVSS1 according to the input control signal RS of the first input and the control signal FRS of the third input. To do. Specifically, the peripheral power supply control circuit PVC1 receives the output from the circuit NR # with respect to the input of the control signal RS and the control signal FRS, and controls the voltages of the peripheral power supply line LC VDD1 and the peripheral ground line LCVSS1.

The peripheral power supply control circuit PVC2 is connected to the power supply voltage VDD and the ground voltage VSS, and controls the voltages of the peripheral power supply line LC VDD2 and the peripheral ground line LCVSS2 according to the input control signal RS of the first input.

Since the other configurations are the same as the configurations of the memory modules described with reference to FIG. 3, no detailed description thereof will be repeated.

FIG. 7 is a diagram illustrating a circuit configuration related to power supply of the memory module MMA based on the second embodiment.

As shown in FIG. 7, the memory module MMA has the same configuration of the memory array MA and the memory power supply control circuit VC as compared with the circuit configuration described in FIG. 4, and other configurations are different.

Specifically, a circuit NR # is provided instead of the NOR circuit NR.
In addition, a new configuration of the Q latch QL and the peripheral power supply control circuit PVC2 is provided.

As for the peripheral power supply line and the peripheral grounding line, the peripheral power supply line LC VDD1 and the peripheral grounding line LCVSS1 are provided corresponding to the peripheral circuit PC. Further, a peripheral power supply line LC VDD2 and a peripheral ground line LCVSS2 are provided corresponding to the Q latch QL.

An N-channel MOS transistor SW1 is provided between the peripheral ground line LCVSS1 and the ground voltage VSS, and the gate of the N-channel MOS transistor SW1 is connected to the node N2 of the circuit NR #.

The circuit NR # includes a P-channel MOS transistor 10 and N-channel MOS transistors 11 and 12.

The P-channel MOS transistor 10 is provided between the power supply voltage VDD and the node N2, and its gate receives the input of the control signal FRS.

The N-channel MOS transistor 11 is provided between the peripheral ground line LCVSS1 and the node N2, and its gate receives the input of the control signal FRS.

The N-channel MOS transistor 12 is provided between the ground voltage VSS and the node N2, and its gate receives the input of the control signal RS.

The control signal RS and the control signal FRS are at the "L" level in the initial state.
Therefore, the circuit NR # outputs an “H” level signal to the N-channel MOS transistor SW1. Therefore, in the initial state, the N-channel MOS transistor SW1 is in the ON state, and the peripheral ground line LCVSS is connected to the ground voltage VSS.

When the control signal RS is activated to the "H" level, the N-channel MOS transistor 12 is turned on, the N-channel MOS transistor SW1 is turned off, and the peripheral ground line LCVSS1 is connected to and separated from the ground voltage VSS. ..

When the control signal FRS is activated to the "H" level, the N-channel MOS transistor 11 is turned on. As a result, the node N2 and the peripheral ground line LCVSS1 are connected. The N-channel MOS transistor SW1 is connected to a diode in which the source and the gate are connected, and the potential of the peripheral ground line LCVSS1 is set to a state in which the potential is slightly raised from the ground voltage VSS (a state in which the potential is high). ..

FIG. 8 is a diagram illustrating a timing chart for explaining a low power consumption mode of the memory module MMA based on the second embodiment.

As shown in FIG. 8, at time T10, the case where the control signal FRS is activated to the “H” level is shown. Along with this, the N-channel MOS transistor 11 is turned on. Therefore, the N-channel MOS transistor SW1 is in a diode-connected state in which the source and the gate are connected, and the potential of the peripheral ground line LCVSS1 is set to a state in which the potential is slightly raised from the ground voltage VSS (high potential). Will be done.

The peripheral ground line LCVSS2 maintains a state of being connected to the ground voltage VSS.
As a result, the power supply of the peripheral circuit PC is reduced. The Q-latch and memory array can be set to a third low power mode that maintains normal power supply.

The case where the control signal FRS is deactivated at time T11 is shown. Along with this, the case where the peripheral ground line LCVSS1 is connected to the ground voltage VSS is shown.

The return operation from the third low power consumption mode to the normal mode restores the power supply to the peripheral circuits, and since the power to be restored is small, the inrush current is small, so that the return operation can be executed at high speed. is there.

The third low power consumption mode in this example reduces the power supply only in a part of the peripheral circuit, and maintains the normal power supply in other areas.

At time T12, the case where the control signal RS is activated to the "H" level is shown. Along with this, the case where the peripheral ground line LCVSS1 is separated from the ground voltage VSS and the potential of the peripheral ground line LCVSS1 is in a high impedance (Hi-Z) state is shown.

Further, a case is shown in which the peripheral ground line LCVSS2 is separated from the ground voltage VSS and the potential of the peripheral ground line LCVSS2 is in a high impedance (Hi-Z) state.

Further, the memory ground wire ARVSS is set in a state in which the N-channel MOS transistor SW4 is connected by a diode and is slightly raised above the ground voltage VSS (a state in which the potential is high).

As a result, the power supply of the peripheral circuit and the Q latch is cut off, and the memory array can be set to the second low power consumption mode in which the power supply is reduced as compared with the normal power supply.

The case where the control signal RS is deactivated at time T13 is shown. Along with this, the case where the peripheral ground wires LCVSS1 and LCVSS2 are connected to the ground voltage VSS is shown. Further, the case where the memory ground wire ARVSS is connected to the ground voltage VSS is shown.

Further, the control signal RSO is a signal in which the control signal RS is delayed, and the case where the control signal RS is deactivated at time T14 is shown. Since the control signal RSO is output to the memory module in the subsequent stage, the return operation from the second low power consumption mode to the normal mode is performed stepwise from the memory module in the previous stage to the memory module in the subsequent stage. Therefore, it is possible to mitigate the generation of the inrush current when the low power consumption mode is released.

At time T15, the case where the control signal SDM is activated to the "H" level is shown. In this case, the control signal SDM alone does not shift to the low power consumption mode.

The case where the control signal RS is activated at time T16 is shown. Along with this, a case is shown in which the peripheral ground lines LCVSS1 and LCVSS2 are separated from the ground voltage VSS, and the potentials of the peripheral ground lines LCVSS1 and LCVSS2 are in a high impedance (Hi-Z) state.

Further, in the memory ground line ARVSS, the N-channel MOS transistor SW6 is turned on and the N-channel MOS transistor SW4 is turned off. Therefore, the case where the memory ground line ARVSS is separated from the ground voltage VSS and the potential of the memory ground line ARVSS is in a high impedance (Hi-Z) state is shown.

As a result, the power supply of the peripheral circuit, the Q latch and the memory array is cut off, and it is possible to set the first low power consumption mode.

The case where the control signal RS is deactivated at time T17 is shown. Along with this, the case where the peripheral ground wires LCVSS1 and LCVSS2 are connected to the ground voltage VSS is shown. Further, the case where the memory ground wire ARVSS is connected to the ground voltage VSS is shown.

Further, the control signal RSO is a signal in which the control signal RS is delayed, and the case where the control signal RS is deactivated at time T18 is shown. Since the control signal RSO is output to the memory module in the subsequent stage, the return operation from the first low power consumption mode to the normal mode is performed stepwise from the memory module in the previous stage to the memory module in the subsequent stage. Therefore, it is possible to mitigate the generation of inrush current when the low power consumption mode is released.

As described above, the memory module MMA sets and cancels the first low power consumption mode based on the combination of the control signal RS of the first input and the control signal SDM of the second input. Further, the memory module MMA sets and cancels the second low power consumption mode based on the input of the control signal RS of the first input. Further, the memory module MMA sets and cancels the third low power consumption mode based on the input of the control signal FRS of the third input.

Then, the return operation from the first and second low power consumption modes to the normal mode is performed according to the control signal RS and the control signal RSO which is a delay signal thereof. That is, the return operation is performed stepwise from the memory module in the front stage to the memory module in the rear stage.

That is, it is not necessary to generate a delay signal in which the control signal is delayed for each of the plurality of low power consumption modes, and the low power consumption mode is set and canceled based on the combination with one delay signal. It is possible to mitigate the generation of inrush current when each of the plurality of low power consumption modes is canceled.

As a result, it is not necessary to provide wiring for delaying the control signal for each low power consumption mode, circuit design with a simple configuration is possible, and the burden of product design can be reduced.

(Embodiment 3)
FIG. 9 is a diagram illustrating a functional block of the memory module MMB based on the third embodiment.

As shown in FIG. 9, the memory module MMB is provided with the OR circuit OR instead of the NOR circuit NR as compared with the memory module MM described with reference to FIG. 3, and the input of the control signal is different.

Specifically, the control signal RS is input to the peripheral power supply control circuit PVC.
The output signal of the OR circuit OR of the control signal FRS and the control signal RS is input to the memory power supply control circuit VC.

In this example, the peripheral power supply control circuit PVC1 is connected to the power supply voltage VDD and the grounding voltage VSS, and controls the voltages of the peripheral power supply line LC VDD1 and the peripheral grounding line LCVSS1 according to the input control signal RS of the first input.

The memory power supply control circuit VC receives the output from the OR circuit OR with respect to the input of the control signal RS and the control signal FRS, and controls the voltages of the memory power supply line AR VDD and the memory ground line ARVSS. Since the other configurations are the same as the configurations of the memory modules described with reference to FIG. 3, no detailed description thereof will be repeated.

FIG. 10 is a diagram illustrating a circuit configuration related to power supply of the memory module MMB based on the third embodiment.

As shown in FIG. 10, the memory module MMB has different inputs of the memory power supply control circuit VC and the peripheral power supply control circuit PVC as compared with the circuit configuration described with reference to FIG.

Specifically, the N-channel MOS transistor SW1 of the peripheral power supply control circuit PVC receives the input of the control signal RS via the inverter 15. The memory power supply control circuit VC receives the output of the OR logical operation result of the OR circuit OR that has received the input of the control signal FRS and the control signal RS.

The control signal RS and the control signal FRS are at the "L" level in the initial state.
Therefore, the N-channel MOS transistor SW1 is on, and the peripheral ground line LCVSS is connected to the ground voltage VSS.

Next, when the control signal SDM is at the "L" level and the control signal RS is activated at the "H" level, the N-channel MOS transistor SW1 is turned off, and the peripheral ground line LCVSS is the ground voltage VSS. Is separated from.

When the control signal RS is activated to the “H” level, the P-channel MOS transistor SW3 is turned off. The AND circuit AD1 maintains the “L” level, and the P-channel MOS transistor SW2 is in the ON state. The N-channel MOS transistor SW6 is in the off state. The AND circuit AD2 is set to the “H” level, and the N-channel MOS transistor SW5 is turned on. Therefore, the node N1 and the memory ground line ARVSS are connected. The N-channel MOS transistor SW4 is in a diode-connected state in which the source and the gate are connected, and the potential of the memory ground line ARVSS is set to a state in which the potential is slightly raised from the ground voltage VSS (a state in which the potential is high). .. This makes it possible to reduce the leakage current of the memory cell MC and reduce the power consumption.

Next, when the control signal SDM is at the “H” level and the control signal RS is activated at the “H” level, the P-channel MOS transistor SW3 is turned off. The AND circuit AD1 is set to the "H" level, and the P-channel MOS transistor SW2 is turned off. Further, the N-channel MOS transistor SW6 is turned on. Therefore, the node N1 and the ground voltage VSS are connected. Therefore, the N-channel MOS transistor SW4 is turned off. The AND circuit AD2 is set to the “L” level, and the N-channel MOS transistor SW5 is turned off. As a result, the P-channel MOS transistor SW2 and the N-channel MOS transistor SW4 are turned off, and the power supply of the memory array MA is cut off.

FIG. 11 is a diagram illustrating a timing chart for explaining a low power consumption mode of the memory module MMB based on the third embodiment.

As shown in FIG. 11, at time T20, the case where the control signal FRS is activated to the “H” level is shown. Along with this, the P-channel MOS transistor SW3 is turned off. The N-channel MOS transistor SW4 is in a diode-connected state in which the source and the gate are connected, and the potential of the memory ground line ARVSS is set to a state in which the potential is slightly raised from the ground voltage VSS (a state in which the potential is high). ..

The peripheral ground line LCVSS remains connected to the ground voltage VSS.
As a result, the power supply of the memory array MA is reduced. It is possible to set the peripheral circuit PC to the fourth low power consumption mode that reduces the power supply.

The case where the control signal FRS is deactivated at time T21 is shown. Along with this, the case where the memory ground wire ARVSS is connected to the ground voltage VSS is shown.

The return operation from the fourth low power consumption mode to the normal mode restores the power supply to the memory array, and since the power to be restored is small and the inrush current is small, it is possible to execute the return operation at high speed. ..

At time T22, the case where the control signal RS is activated to the "H" level is shown. Along with this, the case where the peripheral ground line LCVSS is separated from the ground voltage VSS and the potential of the peripheral ground line LCVSS is in a high impedance (Hi-Z) state is shown.

Further, the memory ground wire ARVSS is set in a state in which the N-channel MOS transistor SW4 is connected by a diode and is slightly raised above the ground voltage VSS (a state in which the potential is high).

As a result, the power supply of the peripheral circuit is cut off, and the memory array can be set to the second low power consumption mode in which the power supply is reduced as compared with the normal power supply.

At time T23, the case where the control signal RS is deactivated is shown. Along with this, the case where the peripheral ground line LCVSS and the memory power supply line AR VDD are connected to the ground voltage VSS is shown. Further, the case where the memory ground wire ARVSS is connected to the ground voltage VSS is shown.

Further, the control signal RSO is a signal in which the control signal RS is delayed, and the case where the control signal RS is deactivated at time T24 is shown. Since the control signal RSO is output to the memory module in the subsequent stage, the return operation from the second low power consumption mode to the normal mode is performed stepwise from the memory module in the previous stage to the memory module in the subsequent stage. Therefore, it is possible to mitigate the generation of the inrush current when the low power consumption mode is released.

At time T25, the case where the control signal SDM is activated to the "H" level is shown. In this case, the control signal SDM alone does not shift to the low power consumption mode.

At time T26, the case where the control signal RS is activated to the "H" level is shown. Along with this, the case where the peripheral ground line LCVSS is separated from the ground voltage VSS and the potential of the peripheral ground line LCVSS is in a high impedance (Hi-Z) state is shown.

Further, in the memory ground line ARVSS, the N-channel MOS transistor SW6 is turned on and the N-channel MOS transistor SW4 is turned off. Therefore, the case where the memory ground line ARVSS is separated from the ground voltage VSS and the potential of the memory ground line ARVSS is in a high impedance (Hi-Z) state is shown.

As a result, the power supply of the peripheral circuits and the memory array is cut off, and it is possible to set the first low power consumption mode.

The case where the control signal RS is deactivated at time T27 is shown. Along with this, the case where the peripheral ground wires LCVSS1 and LCVSS2 are connected to the ground voltage VSS is shown. Further, the case where the memory ground wire ARVSS is connected to the ground voltage VSS is shown.

Further, the control signal RSO is a signal in which the control signal RS is delayed, and the case where the control signal RS is deactivated at time T28 is shown. Since the control signal RSO is output to the memory module in the subsequent stage, the return operation from the first low power consumption mode to the normal mode is performed stepwise from the memory module in the previous stage to the memory module in the subsequent stage. Therefore, it is possible to mitigate the generation of the inrush current when the low power consumption mode is released.

As described above, the memory module MMA sets and cancels the first low power consumption mode based on the combination of the control signal RS of the first input and the control signal SDM of the second input. Further, the memory module MMA sets and cancels the second low power consumption mode based on the input of the control signal RS of the first input. Further, the memory module MMA sets and cancels the fourth low power consumption mode based on the input of the control signal FRS of the third input.

Then, the return operation from the first and second low power consumption modes to the normal mode is performed according to the control signal RS and the control signal RSO which is a delay signal thereof. That is, the return operation is performed stepwise from the memory module in the front stage to the memory module in the rear stage.

That is, it is not necessary to generate a delay signal in which the control signal is delayed for each of the plurality of low power consumption modes, and the low power consumption mode is set and canceled based on the combination with one delay signal. It is possible to mitigate the generation of inrush current when each of the plurality of low power consumption modes is canceled.

As a result, it is not necessary to provide wiring for delaying the control signal for each low power consumption mode, circuit design with a simple configuration is possible, and the burden of product design can be reduced.

(Embodiment 4)
FIG. 12 is a diagram illustrating a circuit configuration related to power supply of the memory module MMC based on the fourth embodiment.

As shown in FIG. 12, the memory module MMC differs from the circuit configuration described in FIG. 4 in that a latch LT is further provided. Since the other configurations are the same as those described in FIG. 4, the detailed description thereof will not be repeated.

Specifically, the memory power control circuit VC further includes a latch LT. The latch LT receives the input of the control signal SDM and the control signal RS.

The latch LT outputs the latched control signal SDMI. The control signal SDMI is output to the AND circuits AD1 and AD2.

FIG. 13 is a diagram illustrating a configuration of a latch LT based on the fourth embodiment.
As shown in FIG. 13, the latch LT includes P-channel MOS transistors 20, 21, 23, 24, N-channel MOS transistors 22, 25, 26, and an inverter 27.

The P-channel MOS transistors 20 and 21 are connected in series between the power supply voltage VDD and the node N3. The gate of the P-channel MOS transistor 20 receives the input of the control signal RS. The N-channel MOS transistor 22 is provided between the node N3 and the ground voltage VSS, and its gate receives the input of the control signal SDM.

The P-channel MOS transistors 23 and 24 are connected in series between the power supply voltage VDD and the node N3.

The N-channel MOS transistors 25 and 26 are connected in series between the node N3 and the ground voltage VSS.

The gate of the P-channel MOS transistor 23 and the gate of the N-channel MOS transistor 26 receive the input of the output signal of the inverter 27.

The gate of the P-channel MOS transistor 24 receives the input of the control signal SDM. The gate of the N-channel MOS transistor 25 receives the input of the control signal RS.

The inverter 27 is connected to the node N3 and outputs a control signal SDMI in which the potential level of the node N3 is inverted.

The latch LT operates as a so-called single-latch circuit.
FIG. 14 is a diagram illustrating a timing chart for explaining the operation of the latch LT.

As shown in FIG. 14, at time T30, the case where the control signal SDM is activated to the “H” level is shown. Along with this, the N-channel MOS transistor 22 is turned on. Therefore, node N3 is set to the "L" level and the control signal SDMI is set to the "H" level. Along with this, the N-channel MOS transistor 26 is turned on.

Next, at time T30 #, the case where the control signal RS is activated to the "H" level is shown.

Along with this, the N-channel MOS transistor 25 is turned on.
Therefore, since the N-channel MOS transistors 25 and 26 are turned on, the voltage level of the node N3 is fixed to the ground voltage VSS.

Next, at time T31, the case where the control signal SDM is deactivated is shown. Along with this, the N-channel MOS transistor 22 is turned off. The P-channel MOS transistor 21 is turned on. On the other hand, since the node N3 is fixed to the ground voltage VSS by the N channel MOS transistors 25 and 26, the control signal SDMI maintains the “H” level.

Next, the case where the control signal RS is deactivated at time T32 is shown. Along with this, the N-channel MOS transistor 25 is turned off. The P-channel MOS transistor 20 is turned on. Therefore, the node N3 is connected to the power supply voltage VDD and set to the "H" level. The control signal SDMI is set to the "L" level.

With this configuration, after the control signal SDM is activated, the control signal SDMI maintains the activated state until the control signal RS is deactivated even if it is deactivated. Therefore, the first low power consumption mode will be continued.

If the control signal SDMI is deactivated due to the deactivation of the control signal SDM, there is a possibility of shifting to the second low power consumption mode because the control signal RS is set to the "H" level. However, according to this method, it is possible to prohibit the transition from the first low power consumption mode to the second low power consumption mode.

As a result, it is possible to stably set and cancel the first low power consumption mode based on the combination of the control signal RS of the first input and the control signal SDM of the second input.

(Embodiment 5)
FIG. 15 is a diagram illustrating a circuit configuration related to power supply of the memory module MMD based on the fifth embodiment.

As shown in FIG. 15, the memory module MMD is different from the circuit configuration described in FIG. 4 in that the propagation path for outputting the control signal RSO is changed. Since the other configurations are the same as those described above, the detailed description thereof will not be repeated.

Specifically, delay elements DL1 and DL2 and a selector SL are further provided.
The selector SL receives the input of the control signal RS and the control signal RS via the delay element DL2. Then, the selector SL switches and outputs the input signal according to the control signal SDM.

As an example, the selector SL outputs the control signal RS via the delay element DL2 to the delay element DL1 according to the “H” level of the control signal SDM.

On the other hand, the selector SL outputs the control signal RS to the delay element DL1 according to the "L" level of the control signal SDM.

Therefore, when the control signal SDM is at the “H” level, the control signal RSO delayed by the two-stage delay elements DL1 and DL2 is output for the control signal RS.

FIG. 16 is a diagram illustrating a timing chart of the control signal RSO adjusted by switching the selector SL.

As shown in FIG. 16, at time T40, the case where the control signal RS is activated to the “H” level is shown. In this case, it is assumed that the control signal SDM is inactivated. Therefore, the selector SL outputs the control signal RS to the delay element DL1.

At time T41, the case where the control signal RS is deactivated is shown. Then, at time T42, the case where the control signal RSO in which the control signal RS is delayed via the delay element DL1 is deactivated is shown.

Next, at time T43, the case where the control signal SDM is activated to the "H" level is shown. Therefore, the selector SL switches the path so as to output the control signal RS delayed by the delay element DL2 to the delay element DL1.

At time T44, the case where the control signal RS is activated to the "H" level is shown.

The case where the control signal RS is deactivated at time T45 is shown. Then, at time T46, the case where the control signal RSO in which the control signal RS is delayed via the delay elements DL1 and DL2 is deactivated is shown.

The delay amount of the control signal RS can be adjusted by this method.
In the second low power consumption mode, the amount of power to be restored by the return operation of the first low power consumption mode is smaller. Therefore, since the second low power consumption mode can recover at a higher speed, the delay amount is reduced, and the first low power consumption mode takes longer to recover when the inrush current is taken into consideration. Therefore, it is possible to increase the amount of delay.

(Embodiment 6)
FIG. 17 is a diagram illustrating an outline of a configuration of a memory array based on the sixth embodiment.

As shown in FIG. 17, a case where the memory array MA is divided into a plurality of memory units is shown.

Specifically, the case where the memory units MU1 to MU4 (hereinafter, also collectively referred to as memory units MU) are divided is shown.

Further, the case where the memory power supply control circuit VC is also divided for each memory unit is shown.

Specifically, a case is shown in which memory power supply control units VCU1 to VCU4 (hereinafter, collectively referred to as memory power supply control unit VCU) are provided corresponding to the memory units MU1 to MU4, respectively.

The OR circuit 42 receives the control signal RS and the delay signal of the control signal RS via the inverters 40 and 41, and outputs the OR logical operation result as the control signal RSO. A control line ARYSW for controlling the memory ground line ARVSS is provided between the inverters 40 and 41.

FIG. 18 is a diagram illustrating a circuit configuration related to power supply of the memory module MME based on the sixth embodiment.

As shown in FIG. 18, the memory module MME is different from the circuit configuration described with reference to FIG. 4 in that the memory array MA is divided into a plurality of memory units MU as described above. Further, a memory power supply control unit VCU is provided corresponding to each memory unit MU.

Each memory power supply control unit VCU is different from the configuration shown in FIG. 4 in that an N-channel MOS transistor SW4 # is further provided. The N-channel MOS transistor SW4 # is provided between the memory ground line ARVSS and the ground voltage VSS, and its gate receives an input of an inverted signal of the control signal RS via the inverter 40. The same applies to other configurations. The control line ARYSW that propagates the output signal of the inverter 40 is commonly provided in each memory power supply control unit VCU. Further, it is assumed that each N-channel MOS transistor SW4 # is a transistor having a large size.

FIG. 19 is a diagram illustrating a timing chart of a control signal based on the sixth embodiment.
As shown in FIG. 19, at time T50, the case where the control signal RS is activated to the “H” level is shown. In this case, the potential of the control line ARYSW via the inverter 40 gradually decreases from the “H” level to the “L” level due to the capacitive load of the N-channel MOS transistor SW4 #.

The control signal RSO is activated to the "H" level at substantially the same timing as the rise of the control signal RS.

The control signal RSD is a delay signal that delays the control signal RS according to the capacitive load of the inverters 40 and 41 and the control line ARYSW.

The control signal RSO is deactivated due to the fall of the control signal RSD (“L” level).

With this configuration, since the capacitive load of the control line ARYSW affects the delay amount, the delay amount can be adjusted according to the characteristics (capacitive load) of the memory module. For example, when the memory unit MU is large, the delay amount is large, and when the memory unit MU is small, the delay amount is small.

(Embodiment 7)
FIG. 20 is a diagram illustrating a circuit configuration related to power supply of the memory module MMF based on the seventh embodiment.

As shown in FIG. 20, the memory module MMF is different from the memory module MM described with reference to FIG. 4 in that the AND circuit 50 is further provided. Since the other configurations are the same as those described in FIG. 4, the detailed description thereof will not be repeated.

The AND circuit 50 receives the input of the test mode signal STM via the inverter 51 and the control signal FRS, and outputs the AND logic operation result to the NOR circuit NR.

The test mode signal STM is a signal input when executing a predetermined test mode. In the initial state, it is set to the "L" level, and in the test mode, it is set to the "H" level.

Therefore, when the test mode signal STM is set to the "H" level, the output of the AND circuit 50 maintains the state set to the "L" level even when the control signal FRS is activated. .. Therefore, when the predetermined test mode is executed, the transition to the third low power consumption mode according to the control signal FRS is prohibited.

This method makes it possible to reliably execute the process in the predetermined test mode.
(Embodiment 8)
FIG. 21 is a diagram illustrating a functional block of the memory module MMG based on the eighth embodiment.

As shown in FIG. 21, the memory module MMG is provided with peripheral circuits for a memory array of two independent ports (port A and port B) as compared with the memory module MM described with reference to FIG. The case is shown.

In this example, the peripheral circuit PCA of the A port and the peripheral circuit PCB of the B port are provided, and the peripheral power supply control circuit is independently provided corresponding to each peripheral circuit.

Specifically, the A port peripheral power supply control circuit PVCA that controls the power supply of the A port peripheral circuit PCA and the B port peripheral power supply control circuit PVCB are provided. The configuration of each peripheral power supply control circuit is the same as that described in the first embodiment and the like.

Further, a NOR circuit NRA is provided corresponding to the A port peripheral power supply control circuit PVCA of the A port, and the A port peripheral power supply control circuit PVCA is a NOR logical operation result of the control signal FRSA for the A port and the control signal RS. It is controlled based on.

Further, a NOR circuit NRB is provided corresponding to the A port peripheral power supply control circuit PVCA of the B port, and the B port peripheral power supply control circuit PVCB is a NOR logical operation result of the control signal FRSB for the B port and the control signal RS. It is controlled based on.

With this configuration, it is possible to set and cancel the low power consumption mode independently for the memory array of a plurality of ports.

FIG. 22 is a diagram illustrating a functional block of the memory module MMG # based on another embodiment of the eighth embodiment.

As shown in FIG. 22, the memory module MMG is provided with peripheral circuits for a memory array of two independent ports (port A and port B) as compared with the memory module MM described with reference to FIG. The case is shown.

In this example, the peripheral circuit PCA of the A port and the peripheral circuit PCB of the B port are provided, and a common peripheral power supply control circuit PVC is provided corresponding to each peripheral circuit.

Specifically, the configuration of the peripheral power supply control circuit is the same as that described in the first embodiment and the like.

When the peripheral power supply control circuit is common, the control signal FRSA and the control signal FRSB are input to the AND circuit ADD, and the AND logic calculation result is output to the NOR circuit NR.

The peripheral power supply control circuit PVC is controlled based on the NOR logical operation result of the NOR circuit NR that has received the output of the AND circuit ADD and the input of the control signal RS.

With this configuration, it is possible to set and cancel the third low power consumption mode when both the control signals FRSA and FRSB are activated for the memory array of a plurality of ports.

(Embodiment 9)
FIG. 23 is a diagram illustrating functional blocks of the memory array and peripheral circuits based on the ninth embodiment.

With reference to FIG. 23, the functional blocks of the memory array MA and peripheral circuits are shown.
As peripheral circuits, a word driver WD that drives the word line WL of the memory array MA, a clock driver CD that drives a clock signal, and a power switch VSW that controls the supply of power to the peripheral circuits are provided.

The clock driver CD receives the input of the clock signal CLK and drives the internal clock intCLK according to the control signal FRSE. The internal clock intCLK is driven when the control signal FRSE is activated (“H” level).

The word driver WD drives the word line WL according to the instructions when the control signal FRSE is activated (“H” level).

The power switch VSW controls the power supply of peripheral circuits based on the control signal FRS and the internal clock intCLK. As an example, the voltage level of the peripheral ground line LCVSS is set. Specifically, when the control signal FRS is at the "L" level, the peripheral ground wire LCVSS is connected to the ground voltage GND, and when the control signal FRS is at the "H" level, the peripheral ground wire LCVSS is connected to and separated from the ground voltage. ..

The NOR circuit NR # receives the input of the control signal FRS and the control signal FRSDLY in which the control signal FRS is delayed, and outputs the NOR logical operation result as the control signal FRSE to the word driver WD and the clock driver CD.

FIG. 24 is a diagram illustrating timing charts of various control signals based on the ninth embodiment.

As shown in FIG. 24, at time T60, when the control signal FRSE is at the “H” level, the internal clock intCLK and the word line WL are driven in synchronization with the clock signal CLK.

Similarly, at the time T61, the internal clock intCLK and the word line WL are driven in synchronization with the clock signal CLK.

If the control signal FRS is activated to the "H" level at time T62, the control signal FRSE is set to the "L" level. Along with this, at time T63, the drive of the word line WL and the internal clock intCLK is stopped.

Then, at time T64, the peripheral ground line LCVSS is separated from the ground voltage VSS and set to a high impedance state (Hi-Z). Since the power switch VSW is controlled by the control signal FRS and the internal clock intCLK and controls the connection between the peripheral ground line LCVSS and the ground voltage VSS, it is possible to prevent data corruption due to an unstable power supply.

Further, at time T65, the case where the control signal FRS is deactivated is shown.
Along with this, the peripheral ground line LCVSS is connected to the ground voltage VSS and returns from the low power consumption mode.

The word driver WD and the clock driver CD are driven after the control signal FRSE is activated. The control signal FRSE is set to the "H" level by deactivating the control signal FRSDLY to the "L" level. Since the control signal FRSDLY is a delay signal of the control signal FRS, the word driver WD and the clock driver CD are activated after the return operation is completed. Then, the word line WL and the internal clock intCLK are driven. Therefore, it is possible to prevent data corruption due to an unstable power supply.

Although the present disclosure has been specifically described above based on the embodiments, it goes without saying that the present disclosure is not limited to the embodiments and can be variously modified without departing from the gist thereof.

FRS, RS, SDM control signal, MM, MMA, MMC, MMD, MME, MMF memory module, PC, PCA, PCB peripheral circuit, PVC, PVC1, PVC2 peripheral power supply control circuit, PVCA, PVCB port peripheral power supply control circuit, TP Semiconductor storage device, VC memory power supply control circuit.

Claims (10)

Has multiple memory modules
Each of the memory modules receives the first and second control signals via the first and second input units, and is set into a plurality of low power consumption modes based on the first and second control signals. Can be set,
At least a part of the plurality of memory modules has a propagation path for transmitting the input first control signal to other memory modules.
The second control signal is input in parallel to each of the plurality of memory modules.
Each of the memory modules is set to the first low power consumption mode based on the combination of the first control signal propagating in the propagation path and the second control signal.
Each of the memory modules is sequentially set to the second low power consumption mode according to the first control signal propagated through the propagation path.
A semiconductor storage device in which the area of the memory module whose power supply is cut off in the second low power consumption mode is different from the area of the memory module whose power supply is cut off in the first low power consumption mode. Each of the plurality of memory modules receives an input of a third control signal for setting each of the memory modules to a third low power consumption mode different from the first and second low power consumption modes. The semiconductor storage device according to claim 1. Each said memory module includes a memory area and a peripheral area.
The semiconductor storage device according to claim 2, wherein in the second low power consumption mode, the power supply of a part of the peripheral region of each memory module is cut off according to the first control signal. Each said memory module includes a memory area and a peripheral area.
In the second low power consumption mode, the power in the peripheral area is cut off and the power in the memory area is reduced.
The semiconductor storage device according to claim 2 , wherein in the third low power consumption mode, only the power in the memory area is reduced. The first low power consumption mode is set according to the activation of the second control signal, and then, without depending on the second control signal, the deactivation of the first control signal. The semiconductor storage device according to claim 1, which is released accordingly. The semiconductor storage device according to claim 1, wherein each memory module further includes an adjustment circuit for adjusting a delay amount of a first control signal passing through a propagation path. The semiconductor storage device according to claim 6, wherein the adjustment circuit adjusts a delay amount of the first control signal via the propagation path based on a control signal of a switch that controls a power line of each memory module. The semiconductor storage device according to claim 2, wherein each memory module includes a prohibition circuit that prohibits reception of the third control signal during the test mode. Each said memory module includes a memory area and a peripheral area.
The memory area includes a plurality of ports that can be controlled independently.
The peripheral area is divided according to each port.
The third control signal is provided to each port.
The semiconductor storage device according to claim 2, wherein in the third low power consumption mode, the power supply is cut off for each of the peripheral regions divided into the ports. Has multiple memory modules
Each of the memory modules is configured to receive first and second control signals via first and second inputs, and a plurality of lowers based on the first and second control signals. Set to power consumption mode,
Each memory module contains a memory area and a peripheral area.
Some memory modules among the plurality of memory modules have a propagation path for propagating the input first control signal to other memory modules.
The second control signal is input to each of the plurality of memory modules in parallel.
Each memory module has a first low power consumption in which the power supply of the memory area and the peripheral area is cut off based on the combination of the first control signal propagating in the propagation path and the second control signal. Set to power mode,
Each of the memory modules is sequentially set to a second low power consumption mode in which the power of the peripheral region is cut off according to the first control signal propagated through the propagation path and the power of the memory region is reduced. Semiconductor storage device.

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