JPH06101551B2 - CMOS integrated circuit device - Google Patents

Description

The present invention relates to a high density and high speed CMOS integrated circuit.

[Conventional technology]

Integrated circuits (LSIs) are roughly classified into logic LSIs and memory LSIs. A logic LSI with different functions and characteristics for each user can be
In order to achieve this efficiently, a semiconductor substrate (master substrate) on which circuit elements such as transistors and resistors are regularly formed in advance is used, and the wiring between circuit elements is changed to realize the functions and characteristics that meet user requirements. The so-called master slice method has been adopted. In the master slice LSI, the layout and shape of the circuit elements formed in advance have a great influence on the integration density. As a circuit configuration for realizing a conventional highly integrated master slice LSI, two sets of an N-channel MOS transistor and a P-channel MOS transistor having a common diffusion layer shown in the equivalent circuit of FIG. 6 and the plane pattern diagram of FIG. 7 are used. A structure called Sea of Gates, which is spread over the entire predetermined area of the chip, or P-type and N-type MOS transistors as shown in the equivalent circuit of FIG. 8 and the plane pattern diagram of FIG. , In the case where it is necessary to separate the elements by arranging the source and drain in common with no isolation region and separating them continuously, a fixed voltage is applied to the gate of each MOS transistor (N-channel MOS transistor Is the substrate voltage, P channel MOS
The transistor has a power supply voltage), and there is a gate separation structure that electrically cuts off between the left and right MOS transistors.

In FIG. 6, 1, 2 and 3, 4 are the gates of the P-channel and N-channel MOS transistors, 6 is the source of the P-channel MOS transistor, and 5 and 7 are the P-channel M.
The drain of the OS transistor, 9 indicates the source of the N channel MOS transistor, and 8 and 10 indicate the drain of the N channel MOS transistor. In FIG. 7, 11 is an N well region, 12 is an N ⁺ region for fixing the potential of the N well region,
Reference numeral 13 denotes a P ⁺ region for fixing the substrate potential. Further, in FIG. 8, 14 to 25 are gates of MOS transistors, and 26 to 35 are sources or drains.

[Problems to be solved by the invention]

Since these conventional configurations use P-type and N-type transistors of the same size, there is a problem that the operation stability is low when an information storage circuit such as a memory circuit or a register circuit is configured. That is, as shown in the circuit diagram of FIG. 10, the memory circuit conventionally used in the CMOS master slice is composed of a total of 6 transistors, 36 is a power supply line (V _DD ), and 37 is a ground line (V _DD ). _SS ), 38 is word line, 39,40
Is a pair of bit lines, 41, 42 are nodes in the memory cell, 43,
44 is a transfer gate serving as a switch between the bit line and the memory cell, 45 and 46 are N-channel transistors forming the memory cell, and 47 and 48 are P-channel transistors forming the memory cell. P channel transistors 47 and 48
The size of N is constant, N-channel transistors 45 and 46,
And the transfer gates 43 and 44 have the same size, and the N-channel transistor 45 and the transfer gate 43
When the information of the memory cell is read out on the bit line 39 by changing the ratio Q ₂ / Q ₁ (which is also the ratio of the N channel transistor 46 and the transfer gate 44), as shown in FIG. 45 and transfer gate
When the transistor size ratio Q ₂ / Q _{1 of} 43 is 2 or less, the potential difference between the nodes 41 and 42 in the memory cell is almost eliminated, and the information in the memory cell is destroyed. Therefore, in order to operate the memory cell stably, it is necessary to configure the circuit by using transistors whose size is twice or more different. Also the 12th
In a latch circuit suitable for high integration as shown in the figure, 49 P-type transistors that feed back the inverted signal of the output signal to the input side to latch the data are usually less than half the size of other transistors. Is used. When the P-type transistor 49 is large, when the transfer gate of 50 is turned on and information is rewritten from "1" to "0", the potential change of the node 51 is slow and it takes time to rewrite data, or The potential of node 51 is inverter
There is a problem that the data cannot be rewritten without lowering below the logical threshold level of 58, and in the circuit of FIG.
It was necessary to reduce the number of shaped transistors to less than half that of other transistors. Further, in the conventional master slice, in order to improve the integration density, the structure shown in FIGS. 13 and 14 in which the basic cells shown in FIGS. 7 and 9 are spread over the entire predetermined area of the chip is used. In any of the configurations, the diffusion layer regions necessary for fixing the substrate potential are the N well region fixing N ⁺ region 12, the substrate potential fixing P ⁺ region 13, and the first diffusion region shown in FIG.
As shown by the N well region fixing N ⁺ region 12 and the substrate potential fixing P ⁺ region 13 in FIG.
There was a problem in increasing the integration density.

In FIG. 13, reference numeral 59 denotes a cell pattern that is a unit of the structure to be spread, 60 in FIGS. 13 and 14 denotes a core area where basic cells are arranged, and 61 denotes a peripheral area where input / output circuits are arranged. The gate separation structure shown in FIG. 14 is a high-density structure in which elements can be separated at arbitrary positions by applying a voltage to the gates of transistors, but a diffusion layer for fixing the substrate potential is provided between transistor columns. Must be provided, about
The area increased by 17%, which was a problem for higher density.

Further, in the gate separation structure, since the power supply line is connected to the gate electrode of the transistor and the diffusion layer for fixing the substrate potential, the power supply line is passed over one gate electrode of the transistor.
Of the individual signal terminals, the outer one terminal cannot be used for signals and there is a problem in that the flexibility of the signal line connection is impaired.

[Means for solving problems]

In order to solve the conventional problems, the present invention has a P-channel MOS transistor and an N-channel MOS transistor as a transistor arrangement of a CMOS master slice type LSI, which are arranged in a horizontal row with their gate electrodes facing each other, and adjacent P-channel MOS transistors. Common diffusion layer and adjacent N-channel MOS transistor diffusion layers, and all P-channel MOS transistors of the same type and all N-channel MOS transistors of the same type are electrically connected in series. In the CMOS integrated circuit device having the structure, the source diffusion layer and the drain diffusion layer of the adjacent P-channel MOS transistors and the source diffusion layer and the drain diffusion layer of the adjacent N-channel MOS transistors are common to each other and arranged in the horizontal row. In the row of P channel MOS transistors, the P A P-channel MOS transistor having a channel width shorter than that of the channel MOS transistor is arranged, and an N-channel MOS transistor having a channel width shorter than that of the N-channel MOS transistor is arranged in the row of N-channel MOS transistors arranged side by side. It is characterized in that a diffusion layer for fixing the substrate potential is provided in a marginal area generated by arranging the P channel MOS transistor and the N channel MOS transistor having a short width.

That is, the present invention is summarized as follows. In a gate isolation structure, small-sized MOS transistors are arranged at a constant rate in a MOS transistor array, and a substrate potential is fixed in a margin area generated by the arrangement of small-sized MOS transistors. Of the diffusion layer is arranged, and the purpose thereof is to provide a master slice configuration which performs stable circuit operation with high density.

[Work]

According to the present invention, in the CMOS master slice, the MOS transistors having a narrow width necessary for configuring the memory circuit and the data latch circuit with a sufficient circuit operation allowance are arranged at a fixed ratio. By using MOS transistors in the circuit, it is possible to construct a completely asynchronous memory circuit that could not be realized by the conventional master slice.

In addition, by providing a diffusion layer for fixing the substrate potential (including well potential) in a marginal area generated by arranging transistors with a narrow channel width at a constant rate, it is possible to reduce the total area between conventional transistor rows. By eliminating the diffusion layer that occupies about 17% of the area, the integration density of the master slice can be increased. Embodiments will be described below with reference to the drawings.

〔Example〕

Figure 1 an alien in the embodiment of the present invention, 11 N-well, 12 for fixing the well potential N ⁺ well due to the diffusion layer potential fixing N ⁺
Region 13, 13 is a P ⁺ region for fixing the substrate potential by the P ⁺ diffusion layer, 62-67 is a P channel MOS transistor with a wide channel width, 68-70 is a P channel MOS with a narrow channel width
Transistors, 71-76 are N-channel MOS with wide channel width
Transistors, 77 to 79 are N channels with narrow channel MO
S-transistor, 80 is a P-type diffusion layer serving as the source or drain of a P-channel MOS transistor, and 81 is an N-channel MO.
It is an N-type diffusion layer that serves as the source or drain of the S transistor. In this way, MO with a narrow channel width at regular intervals
By arranging the S transistor, it is possible to use transistors having different sizes corresponding to the circuit operation, and it is possible to achieve stable circuit operation. FIG. 2 shows a layout pattern diagram when a memory cell is constituted by wiring under the transistor arrangement of FIG. In FIG. 2, the shaded area to the right indicates the first metal wiring layer, and the shaded area to the left indicates the second metal wiring layer. Further, the solid black portion indicates a connection point between the first layer metal and the gate and the source / drain of the transistor, and the region of the point is a connection through hole of the first layer metal and the second layer metal. FIG. 2 shows the circuit of FIG.
Is a power supply line, 37 is a ground line, 38 is a word line, 39 and 40 are left and right bit lines, 41 and 42 are nodes in a memory cell, 43 and 44 are transfer gates using narrow transistors, and 45 and 46 are
Is an N channel MOS transistor in the memory cell, and 47 and 48 are P channel MOS transistors. 47,48 P channel
In order to separate the MOS transistors from others and use them in the memory circuit, a positive voltage is applied to the gates of the P-channel MOS transistors 63, 64, 65, 66 having a wide channel width to separate each transistor from the non-conducting state. Also transfer gate
Similarly, 43 and 44 also apply the ground potential to the gates of the adjacent N-channel MOS transistors having a wide channel width of 72 and 75, which are separated from each other by making them non-conductive. In the case of configuring the memory cell circuit in this way, stable circuit operation can be realized by using transistors having different sizes. Further, one memory cell can be realized with six gates of N-channel MOS transistors (referred to as 6 pitches), and can be realized with a high density as compared with 7 pitches of the sea of gates.

Further, as shown in FIG. 1, the well potential fixing N ⁺ regions forming the diffusion regions for 12 N well contacts, which are conventionally placed between the transistor columns, are replaced by the P channel MOS of 68 or 69 having a short channel width. In the margin area created by reducing the size of the transistor, and the P ⁺ area for fixing the substrate potential that forms the diffusion layer for the substrate contact in 13 is the margin area of the N channel MOS transistor with a narrow channel width of 77 or 78. In this case, the MOS transistor rows of the P-channel and the N-channel can be arranged with a small space between them, and high density can be achieved.

FIGS. 3A and 3B show a comparison between the configuration of the present invention and the conventional configuration in which diffusion layers for well contacts and substrate contacts are arranged between MOS transistor columns. FIG. 3A shows a conventional configuration, third
FIG. B shows the configuration of the present invention. According to the present invention, the diffusion layer between cell columns can be absorbed in the MOS transistor array,
Area can be reduced by 15% to 15%.

FIG. 4 shows a plane pattern diagram of another embodiment of the present invention. The same reference numerals as those in FIG. 1 indicate the same parts. By placing a diffusion layer for substrate contact above and below a narrow MOS transistor, the MOS transistor array is targeted, and the power supply line and the ground line can be located above and below the MOS transistor array. FIG. 5A shows a diagram in which the pattern of the embodiment shown in FIG. 4 is spread all over the chip. Due to this structure, as shown in FIG. 5A, in a spread type configuration in which P-channel MOS transistor rows and N-channel MOS transistor rows are alternately arranged, P-N or N
Gate rows can be placed in the order -P. For this reason,
The wiring track can be set by a multiple of the number of tracks for one MOS transistor row, and there is an advantage that efficient wiring can be performed.

FIG. 5B shows a part of another embodiment of the present invention. The same reference numerals as those in FIG. 1 indicate the same parts.

In FIG. 5B, the N-type diffusion layer 81 is completely separated from the P-type diffusion layer and partially present, and the N-type diffusion layer is surrounded by 12 N well potential fixing N ⁺ regions. It is the same except that it is different from Fig. 1. It goes without saying that the role of fixing the potential of 12 does not change even in this case, and the characteristics of the master slice are the same as those described above.

This idea can be applied to the case where there are potential fixing portions above and below the p well and the n well as shown in FIG.

〔The invention's effect〕

As described above, according to the present invention, the P channel and N
In a structure in which one row of channel MOS transistors are connected in series, a MOS transistor having a narrow channel width is repeatedly repeated (for example, every 2 to 3 MOS transistors are 1
This arrangement has the advantage that it can be used as a gate for element isolation or as a transfer gate with a narrow channel width in a memory cell, flip-flop, or latch circuit, and can realize stable circuit operation.

[Brief description of drawings]

FIG. 1 is a plane pattern diagram of an embodiment of the present invention, FIG. 2 is a pattern diagram in which memory cells are laid out under the basic cell configuration of the present invention, and FIGS. 3A and 3B are conventional examples and the present invention. FIG. 4 shows a comparison with an embodiment, FIG. 4 is a plane pattern view of another embodiment of the present invention, and FIGS. 5A and 5B are views in which the pattern of FIG. 4 is spread over a chip, FIG. 6 and FIG. FIG. 8 is an equivalent circuit diagram of the basic configuration unit of the conventional master slice LSI, FIGS. 7 and 9 are plane pattern diagrams of the conventional configuration of FIGS. 6 and 8, and FIG. 10 is a static memory. Memory cell circuit, Fig. 11 is a diagram showing stable operation conditions of the memory cell circuit, Fig. 12 is a latch circuit diagram suitable for high integration, and Fig. 13 is a configuration in which the basic cells of Fig. 7 are spread all over the chip. Figure, first
FIG. 14 is a configuration diagram in which the basic cells of FIG. 9 are spread over the entire surface of the chip. 1 to 4,14 to 25 …… MOS transistor gate, 5 to 10,26
~ 35 …… Source or drain of MOS transistor, 11
…… N well, 12 …… N well potential fixing N ⁺ region, 13 ・ ・ ・
... P ⁺ area for fixing the substrate potential, 36 ... power supply line, 37 is a ground line,
38 ... Word line, 39,40 ... bit line, 41,42 ... Node in memory cell, 43,44 ... Transfer gate as switch between bit line and memory cell, 45,46 ... N channel MOS Transistors, 47, 48 ... P-channel MOS transistors, 49 ... Latch P-channel MOS transistors, 50
...... Transfer gates, 51 to 55 ...... nodes in the latch, 56 ...... power supply, 57,58 ...... inverter, 59 …… cell pattern that is the unit of spreading, 60 …… core area, 61 …… peripheral area, 62 ~ 67 …… P channel MO with long channel width
S-transistor, 68-70 ... P-channel MOS transistor with short channel width, 71-76 ... N-channel MOS transistor with long channel width, 77-79 ... N-channel MOS transistor with short channel width, 80 ... … P type diffusion layer, 81 …… N type diffusion layer

Claims (1)

[Claims] 1. A P-channel MOS transistor and an N-channel M as a transistor arrangement of a CMOS master slice type LSI.
The OS transistors are arranged in a horizontal row with their gate electrodes facing each other, and the diffusion layers of the adjacent P-channel MOS transistors and the diffusion layers of the adjacent N-channel MOS transistors are respectively common, and all of the P-channel MOS transistors of the same type, And a CMOS integrated circuit device in which all N-channel MOS transistors of the same type are electrically connected in series in an electrical circuit, the source diffusion layer and the drain diffusion layer of the adjacent P-channel MOS transistors, and the adjacent N Channel MO
The source diffusion layer and the drain diffusion layer of the S transistor are common to each other, and a P channel MOS transistor having a channel width shorter than the P channel MOS transistor is arranged in the row of P channel MOS transistors arranged in the horizontal row. An N channel MOS transistor having a channel width shorter than that of the N channel MOS transistor is arranged in the column of N channel MOS transistors arranged in line, and a margin caused by arranging the P channel MOS transistor and the N channel MOS transistor having the short channel width is arranged. A CMOS integrated circuit device characterized in that a diffusion layer for fixing the substrate potential is provided in the region.