JPH08213575A - Cmos integrated circuit device - Google Patents

Abstract

PURPOSE: To form regular circuits at a high density by allotting adequate interconnection regions according to logic circuits. CONSTITUTION: A basic cell 13d has four sets of complementary MOS transistors composed of P- and N-channel MOS transistors. The central adjacent P-channel transistors have a common source or drain 24. These have a common source or drain 32 to the right and left complementary P-channel transistors. The central adjacent N-channel transistors have a common source or drain 24' and these have a common source or drain 32' to the right and left N-channel transistors. The gates 23, 23', 25, 25', 31 and 31' of the transistors are formed separately.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a high density and high speed C
It relates to a MOS LSI.

[0002]

2. Description of the Related Art LSIs are becoming more highly integrated and operating at higher speeds, and the number of logic gates per chip is increasing. Development of such an LSI in a short design and manufacturing period
A so-called master slice method has been adopted as a method for producing and reducing the cost. At the same time, in order to reduce power consumption, CMOS integrated circuits have been widely used.
The most common master slice type CMOS LSI is
The basic cells of the equivalent circuit shown in FIG. 20 are formed in the circuit pattern shown in the plan view of FIG. 21, and the basic cells are arranged one-dimensionally as shown in FIG. It After that, a predetermined wiring pattern is laminated corresponding to the product type to complete the LSI chip.

20 and 21, 1 is an N-type semiconductor substrate (hereinafter abbreviated as "N substrate"), 1'is an island-shaped P-type region formed in the N substrate 1 (hereinafter referred to as "P well"). ),
2 and 2'make resistive contact (ohmic contact) with the N substrate and P well, respectively, to form the power line VDD and the ground line V.
Regions connected to SS (hereinafter referred to as “substrate contact region” and “well contact region”) 3, 4,
Reference numeral 5 denotes a P-channel metal oxide semiconductor transistor (hereinafter abbreviated as “PMOS transistor”) 8, 9 which is a source or drain region, 3 ′, 4 ′ and 5 ′ are also N-channel metal oxide semiconductor transistors (hereinafter “NMOS transistor”). Sources or drain regions of 8'and 9 ', 6 is a common gate of the PMOS transistor 8 and the NMOS transistor 8', and 7 is a common gate of the PMOS transistor 9 and the NMOS transistor 9 '.

This basic cell is characterized in that the source or drain regions 3 and 3'are common source or drain regions for the two transistors, which contributes to miniaturization of the basic cell. As the basic cell, the common gates 6 and 7 may be separated at the central portion, and the PMOS transistors 8 and 9 and the NMOS transistors 8'and 9'may be provided with individual gates. The specific logical function is
This is realized by appropriately connecting both ends of the source, the drain, and the gate or the extended portions at the center with metal wiring.
That is, as the first step, as a logic function that can be used universally for various LSIs, a logic cell having a scale of about 20 or less basic cells is extracted, and each of them is performed in a basic cell area in which predetermined connections are arranged in one row. Hereinafter, this is called a "logic cell", and usually has several dozen types.

Next, as a second step, a large number of logic cells are arranged on the array of the basic cells 13 in FIG. 22, and wiring is performed using the wiring area 14 in which areas are fixedly distributed between them. . The final configuration is shown in FIG. In addition,
In FIG. 22, 10 is an LSI chip, 11 is a logic circuit area formed by the above-mentioned logic cells and connections between the cells, and 12 is a peripheral circuit area that provides a physical / electrical interface between the outside of the chip and the logic circuit.

[0006]

In the above-mentioned prior art,
Since the layout area and the connection area of the logic cell are separately and fixedly allocated, it is not always possible to take the optimum configuration for the situation where the wiring amount is greatly increased or decreased by the logic function. For example, in the case of an LSI having a small amount of wiring, an empty area is generated in the wiring area 14. On the contrary, LS with a large amount of wiring
In the case of I, since it can be accommodated in the wiring region, it is necessary to take a method such as reducing the wiring density by making some of the basic cells unused. In any case, there is a drawback that the degree of integration is reduced. RAM / ROM
In the case of forming a regular circuit such as a multiplier, the wiring area 14 is not necessary at all, and not only the performance is deteriorated but also an extremely large empty area is generated. That is, the above-mentioned conventional technique has a serious drawback that it is virtually impossible to embed a regular circuit such as a RAM / ROM / multiplier and a general logic circuit.

The present invention has been made in view of the above circumstances, and an object of the present invention is to always allocate an appropriate wiring area corresponding to a change in the wiring amount of a logic circuit, and to make a regular circuit. It is to obtain a CMOS integrated circuit device that can be configured with high density.

[0008]

To achieve this object, the present invention has four sets of complementary MOS transistors each including one P-channel MOS transistor and one N-channel MOS transistor. 4 sets of complementary M
A basic cell in which OS transistors are arranged in parallel to each other is spread over a predetermined area. In the basic cell, two sets of complementary MOS transistors arranged in the center among the four sets are complementary to each other. Or N channel MO
Complementary MOS transistors formed so as to share a source or drain region for each S transistor and arranged on the left and right sides thereof and a P or N channel MO, respectively.
Two sets of complementary MOSs are formed to share the source or drain region for each S transistor, the gates of the transistors are formed separately, and are arranged in the center.
A difference is provided between the channel width of the transistor and the channel widths of complementary MOS transistors arranged on the left and right of the transistor, and the four P-channel MOS in the basic cell are provided.
The patterns that make up the transistors are symmetrical with respect to the centerline common to the channels of these four transistors,
The patterns forming the four N-channel MOS transistors are symmetrical with respect to the center line common to the channels of these four transistors. Thus, in the CMOS integrated circuit device according to the present invention, R
It is possible to mix a circuit having a regularity such as AM / ROM / multiplier and a logic circuit.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION According to the present invention, as shown in FIG. 1, basic cells can be arranged in a two-dimensional manner without a gap, and logic cells can be arranged in arbitrary columns, and at the same time, the height of half the basic cells can be reduced. The feature is that the wiring area can be increased as a unit. Further, it is characterized in that a logic cell and a regular circuit such as a RAM / ROM / multiplier can be configured with high area efficiency. The equivalent circuit of the basic cell, the circuit pattern, the arrangement condition on the chip, and the method of use are different from those of the conventional technique, and will be described in detail below with reference to the drawings.

2 and 3 are examples of the basic explanation of the present invention.
2 is a circuit diagram showing the equivalent circuit, and FIG. 3 is a plan view of the circuit pattern. 2 and 3, the same numbers are given to the same components. In these figures, 13a is a basic cell, 20, 20 ', 22, 22',
24, 24 ', 26, 26' are PMOS transistors,
Source or drain of NMOS transistor, 2
2, 22 'and 24, 24' are shared by adjacent transistors.

Also, 21, 23, 25 and 21 ', 2
3'and 25 'are the gates of the PMOS and NMOS transistors, and the gates 23 and 23', 2
5 and 25 'are common to each other and to the corresponding gates of the upper and lower basic cells. This common gate can be cut at position 27 in the basic cell and at position 28 above and below the basic cell, if desired.

Further, 29a, 29a 'and 29 of FIG.
Reference numerals b and 29b 'are substrate or well contact regions.
The above-mentioned patterns forming the PMOS transistor and the NMOS transistor are symmetrical with respect to the axes X1-X2 and X1'-X2 ', and the basic cell 13a is shown in FIGS.
As shown in FIG. 3, since the cells are continuously spread vertically and horizontally without any gap, it is possible to take the position of 13a 'as the area of the basic cell by reversing the top and bottom.

As described above, this description example is shown in FIG.
Compared with the conventional device of FIG. 21, one more PMOS transistor and one NMOS transistor are provided in the same area. Therefore, the width of the logic cell is, for example, 1/2 for a 2-input AND circuit, and the D-type flip-flop of FIG. As for the circuit, wiring can be designed as shown in FIGS.
It can be reduced to 4 each, which contributes to higher density and higher speed of logic cells.

Furthermore, since the degree of freedom in arranging the logic cells and allocating the wiring area is large, it is possible to minimize the useless empty area. For this reason, it is possible to reduce the size of the LSI chip, and hence to improve the yield and improve economy. 4 to 6, TG1 to TG4 are transmission gates, CK is a clock signal, D is input data, and Q is output data.

FIGS. 7 and 8 show another basic explanation example of the present invention, in which one PMOS transistor and one NMOS transistor are further added to the explanation examples of FIGS. 2, 30 and 30 'are sources or drains of additional transistors, 31, 31' are gates of additional transistors, and 32 and 32 'are additional transistors.
It is a source or a drain shared with the transistor of the explanation example of FIG.

If the basic cell 13b of this example is used, the memory cell which is the main constituent element of the RAM most frequently used as a regular circuit is one basic cell as shown in FIGS. 9 (a) and 9 (b). Configurable (see MC in Figure 9 (a)),
Higher density of RAM can be achieved. Therefore, if the present description example is applied to an LSI having a large storage capacity of RAM, the effect is most remarkable.

FIG. 10 and FIG. 11 exemplify various techniques for effectively utilizing the basic cell according to the present description example. That is, in the 2-input NAND gate NAND (see FIG. 11A), for example, G1, G1 'and G2, G2' are connected in parallel, and the gate width of the transistor is increased, whereby the speed can be increased.

Two-input AND gate AND (see FIG. 11)
(See (b)), G3, G3 ',
An inverter circuit composed of G4 'is added to form an AND gate. Here, by increasing the gate width by arranging the PMOS transistors of G3 and G4 in parallel, the rise time of the output waveform of the output terminal T3 is speeded up and is almost the same as the fall time. In addition, G3 '
Is a gate of an unused transistor, which is connected to VSS through a contact hole C1 to keep this transistor in a non-operating state at all times.

The third example in FIGS. 10 and 11 requires, for example, an inverter with a transfer gate and an inverter (see the in-cell gate CG in FIG. 10 and FIG. 11C) that operate independently in the logic cell. In this case, the common gate is separated into G5 and G5 'at the position S and connected to VDD and VSS through the contact holes C2 and C2' so that the PMOS transistor and the NMOS transistor are always inoperative. As a result, the left and right transistors of G5 and G5 'can operate independently, and the above-mentioned two types of independent circuits can be obtained. In addition, T1 of FIG.
T2 and T4 to T8 are terminals.

12 and 13 show an example in which a D-type flip-flop circuit is constructed by using the basic cell according to the present explanation example, and can be realized with the same width as the explanation examples of FIGS. 2 and 3. FIG.
2. In FIG. 13, TG1 to TG4 are transmission gates, CK is a clock signal, D is input data, and Q is
Is output data.

14 and 15 show another basic explanation example of the present invention, which is different from the explanation examples shown in FIGS.
The feature is that the patterns 40 and 40 'for connecting 41' and the gate 43 are formed in the same step as the gate. The connection patterns 40, 40 'can be cut at the positions 42, 42' and 42 "in the same step as the cutting of the other gates, and can also be used as independent gates.

Applying this explanation example to the configuration of the D-type flip-flop circuit concretely, the clock signal C of the transmission gates TG1 to TG4 shown in FIGS.
The second metal wiring of the K wiring patterns L1 and L2 and the through holes at both ends thereof and the contact holes C1 and C2 are unnecessary, and as a result, the second metal wiring tracks T2-2 and 2 are provided.
-3, 2-4, and 2-5 can be unused in the logic cell.

That is, in the D-type flip-flop circuits of FIGS. 12 and 13, the second metal wiring tracks T2-1 to T2-8 in the substrate contact region and the well contact region are used.
Are all unused. Therefore, this track can always be used as a wiring track for connection between logic cells or for vertical connection between VDD lines and VSS lines.
It is possible to reduce the man-hours for designing and arranging and wiring the LSI chip, suppress the generation of waste space, and improve the characteristics of the power supply system.

FIGS. 16 and 17 exemplify the layout of logic cells in an LSI chip, wiring between cells, and VDD and VDD wiring. The wiring channel between the logic cells has a minimum width, and 4 tracks can be used for the first metal wiring. The respective common gate patterns are cut above and below the logic cell placement regions G10 and G20 to enable a predetermined logic cell operation. Each line of VDD and VSS is
The electrical characteristics of the power supply system are improved by connecting the first metal wiring in the horizontal direction and the second metal wiring in the vertical direction to each other.

By applying the basic cells according to the explanation examples of FIGS. 14 and 15, it is possible to determine the vertical wiring tracks of VDD and VSS in advance without restricting the layout of the logic cells. This brings the advantage that the power supply system pattern can be easily created. Note that WC in FIG. 16 is a wiring channel.

FIGS. 18 and 19 are a circuit diagram and a pattern diagram of the CMOS integrated circuit device showing the first embodiment of the present invention. The gate 2 is different from the explanation example of FIGS.
The feature is that 5 and 25 'and 23 and 23' are formed separately in advance. This is because, in the example of FIGS. 7 and 8, one more mask for cutting the polysilicon is required to separate the common gate, but instead of this, the gate to be connected with the contact hole by Al is desired. The idea is to connect.

A PMOS transistor of the basic cell 13d,
The pattern forming the NMOS transistor is the axis X10-
Since it is symmetrical with respect to X20, X10′-X20 ′ and is spread as shown in FIG. 19, it is possible to minimize the feature described so far, that is, useless empty area. It also has the characteristic that a dynamic circuit, especially a RAM, can be mounted efficiently.

Further, although there is a slight increase in the number of Al wirings, the number of masks can be reduced by one, so that an improvement in manufacturing yield can be expected. In the present embodiment,
For example, as shown by the gates 23 ', 25' and 31 ', 32 ", the channel widths of the two sets of complementary MOS transistors arranged in the center are the same as the complementary MO transistors arranged on the left and right sides thereof.
It is longer than the channel width of the S transistor.

[0029]

As described above, according to the present invention, the basic cells are spread over the entire predetermined area.
It becomes possible to allocate wiring channels with variable number of wiring tracks for the first type metal wiring, which is extremely effective in increasing the speed and integration of the LSI. In addition, regular circuits such as RAM, ROM, and multipliers can be densely configured,
It is possible to economically realize a high-performance and high-function LSI in which a logic circuit and these regular circuits are mounted together. That is, since the master slice LSI using the basic cell according to the present invention has a wide range of applicable areas, it can sufficiently cope with the tendency of the LSI to be manufactured in the production of small lots of various kinds.

[Brief description of drawings]

FIG. 1 is a layout diagram of a basic cell according to the present invention.

FIG. 2 is an equivalent circuit diagram showing a basic explanation example of the present invention.

FIG. 3 is a pattern diagram showing a basic explanation example of the present invention.

FIG. 4 is a circuit diagram of a D-type flip-flop circuit.

FIG. 5 is a pattern diagram of a D-type flip-flop circuit using the basic description example of FIGS.

6 is an equivalent circuit diagram of the D-type flip-flop circuit of FIG.

FIG. 7 is an equivalent circuit diagram showing another basic explanation example of the present invention.

FIG. 8 is a pattern diagram showing another basic explanation example of the present invention.

9A and 9B are a pattern diagram and an equivalent circuit diagram of a memory cell using the basic description example of FIGS.

FIG. 10 is a pattern diagram showing an example in which the basic cells of FIGS. 7 and 8 are used.

11 is an equivalent circuit diagram of the pattern of FIG.

FIG. 12 is a pattern diagram of a D-type flip-flop circuit using the basic cell of FIGS.

FIG. 13 is an equivalent circuit diagram of the D-type flip-flop circuit of FIG.

FIG. 14 is a circuit diagram showing another basic explanation example of the present invention.

FIG. 15 is a pattern diagram showing another basic explanation example of the present invention.

FIG. 16 is a pattern diagram showing an example of arrangement and wiring in an LSI chip according to the present invention.

FIG. 17 is a circuit diagram of the pattern of FIG.

FIG. 18 is a CMOS showing a first embodiment of the present invention.
It is a circuit diagram of an integrated circuit device.

19 is a pattern diagram of the CMOS integrated circuit device of FIG.

FIG. 20 is an equivalent circuit diagram of a conventional basic cell.

FIG. 21 is a pattern diagram of a conventional basic cell.

FIG. 22 is a layout view of a conventional basic cell.

[Explanation of symbols]

10 ... LSI chip, 11 ... Logic circuit area, 12 ... Peripheral circuit area, 13, 13a to 13d ... Basic cell, 20, 2
0 ', 22, 22', 24, 24 ', 26, 26', 3
0, 30 ', 32, 32' ... Source or drain, 2
1, 21 ', 23, 23', 25, 25 ', 31, 3
1 '... gate, 27,28 ... position.

Front page continued (72) Inventor Noboru Onishi 2-10-2 Benten, Urayasu-shi, Chiba (72) Inventor Toshinori Yamamoto 1-24-229, Onta-cho, Higashimurayama-shi, Tokyo (72) Tsutomu Hosaka 2-15-15 Kita 2-chome, Kunitachi, Tokyo

Claims (1)

[Claims] 1. A complementary type M comprising one P-channel MOS transistor and one N-channel MOS transistor.
It has four sets of OS transistors, and these four sets of complementary MOS
A CMOS integrated circuit device in which basic cells having transistors arranged in parallel to each other are spread over a predetermined region, and the basic cell includes two complementary MOS transistors arranged in the center of the four groups, which are P-type to each other. Alternatively, the source or drain region is formed for each N-channel MOS transistor, and the source or drain region is shared for each P- or N-channel MOS transistor with the complementary MOS transistors arranged on the left and right thereof. Formed, each gate of the transistor is formed separately, and two sets of complementary M arranged in the center are formed.
A difference is provided between the channel width of the OS transistor and the channel widths of complementary MOS transistors arranged on the left and right of the OS transistor, and the patterns forming the four P-channel MOS transistors in the basic cell are these four transistors. CMOS which is symmetric with respect to a center line common to the channels of the four transistors, and at the same time, is symmetric with respect to a center line common to the channels of these four transistors. Integrated circuit device.