JPH0475664B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and relates to a gate array type MOS type large-scale integrated circuit using a master slice method.

The master slicing method involves creating a large number of basic cells consisting of multiple elements on a semiconductor substrate in advance.
It attempts to obtain a desired circuit operation by changing contact holes and metal wiring, and is characterized by being able to respond to requests for circuits with new functions relatively easily. In other words, since the semiconductor chips created through the process up to the point where metal wiring is formed are common to all functional circuits, it is possible to shorten the development period and reduce manufacturing costs, making it possible to manufacture a wide variety of chips, which has been considered difficult in the past. , to enable small-scale production,
It has been attracting attention in recent years.

In a gate array type large-scale integrated circuit based on the master slice method, the inside of a semiconductor chip is divided into a basic cell area where basic cells are connected and a wiring area that interconnects groups of basic cells. Since the basic cells are arranged according to a certain rule regardless of the desired circuit, not all elements of the basic cells are necessarily used in gate array type large-scale integrated circuits. However, in order to realize large-scale integrated circuits with more advanced and complex functions, it is necessary to increase the utilization rate of basic cells and make effective use of them. Furthermore, in order to effectively utilize the wiring area, shorten the wiring length, etc., the basic cell also needs to serve as a wiring area that connects the wiring areas. Furthermore, it is essential that the basic cells take a form that allows circuits with various functions to be constructed.

The present invention was made in view of the above-mentioned points, and
The present invention provides a semiconductor integrated circuit suitable for a gate array type large-scale integrated circuit using a master slice method.

FIG. 1 shows an equivalent circuit of a basic cell constituting a large-scale integrated circuit according to the present invention. There are 4 basic cells
Consists of MOS transistors TR1 to TR4. T.R.
1.TR2 is a P channel MOS transistor,
TR3 and TR4 are N-channel MOS transistors. The sources or drains of TR1 and TR2 of the P channel are jointly connected, and the sources or drains of TR3 and TR4 of the N channel are also jointly connected. Also of P channel
The gate electrodes of TR1 and TR3 of the N channel are shared and integrally connected, but the gate electrodes of TR2 and N of the P channel
The gate electrode of channel TR4 is not integrated or shared.

FIG. 2 is a pattern diagram showing a basic cell according to an embodiment of the present invention. 1 and 2 are continuously formed integrally with the gate electrodes of TR1 and TR3, and 3 and 4 are the gate electrodes of TR1 and TR3.
2. The gate electrodes of TR4 are formed independently. Reference numerals 5, 6, and 7 denote P ⁺ impurity diffusion regions that serve as sources or drains of the P channel MOS transistors TR1 and TR2, of which the P ⁺ impurity diffusion region 6 is shared by TR1 and TR2.
8, 9, 10 are N-channel MOS transistors
Becomes the source or drain of TR3 and TR4
Among the N ⁺ impurity diffusion regions, N ⁺ impurity diffusion region 9 is shared by TR3 and TR4. Several contact holes can be formed in each of these impurity diffusion regions. 11 is a P-well.

FIGS. 3a and 3b are cross-sections of the pattern shown in FIG. 2 taken along lines A-A' and B-B', respectively.
12 is an N-type silicon wafer, and P well 11
TR3 and TR4 are formed in the areas where there is no P well, and TR1 and TR2 are formed in areas where there is no P well. 13 is a field oxide film.

In order to fabricate the basic cell as described above on a silicon chip, a conventional process for fabricating a complementary MOS transistor integrated circuit may be used.

Using this basic cell, a desired logic circuit can be created by simply changing the connection layout of the metal wiring layer. Next, an embodiment will be described in which the basic cell described above is used to construct a logical NOR (NOR) circuit, a clock drain inverter, and a static delay flip-flop (DFF) circuit. For convenience, the case of a silicon gate MOS transistor in which impurity-diffused polycrystalline silicon is used for the gate electrode and Al is used for the metal wiring layer will be described. FIG. 4 is an equivalent circuit diagram of the NOR circuit, and FIG. 5 is a pattern layout diagram thereof. In FIG. 5, the solid line drawn on the cell pattern indicates the first layer Al wiring, and the broken line indicates the first layer Al wiring.
A second layer disposed on the wiring layer with an interlayer insulating film interposed therebetween.
Layer Al wiring is shown. The × mark indicates the position of the contact hole that makes an ohmic connection with the first layer Al wiring and the gate electrode made of polycrystalline silicon or the impurity diffusion layer, and the ○ mark indicates the position of the first layer Al wiring and the second layer Al wiring. The figure shows the position of a through hole to be made in the interlayer insulating film to connect the two. Polycrystalline silicon electrodes and impurity diffusion layers have a certain degree of electrical resistance. This results in a reduction in the operating speed of the circuit. In order to keep this small, the former uses Al wiring,
The electrodes are short-circuited at both ends, and in the latter case, a contact hole is formed in the center of the impurity diffusion layer.

In this way, according to this embodiment, a NOR circuit can be constructed using all one basic cell.

FIG. 6 is an equivalent circuit diagram of an embodiment applied to a clocked inverter, and FIG. 7 is a pattern layout diagram thereof. In this embodiment as well, as in the previous embodiment, a clocked inverter can be constructed extremely easily using one basic cell.

FIG. 8 is an equivalent circuit diagram using gate symbols of an embodiment applied to a DFF circuit, FIG. 9 is a detailed equivalent circuit diagram thereof, and FIG. 10 is a pattern layout diagram thereof. The NOR circuits G ₁₁ and G ₁₂ and the clocked inverters G ₂₁ to _{G 24} are each constructed using one basic cell as explained in the previous embodiment, and the two inverters G ₃₁ and G ₃₂ are constructed using one basic cell. Constructed using basic cells. That is, although seven basic cells are used in this embodiment, there is no unused transistor in the basic cell, and the transistor utilization rate is 100%, which is extremely efficient.

In Fig. 10, the two Al wires in the left and right wiring channel regions are used to make ohmic contact with the substrate and P-well for each basic cell in order to reduce the potential gradient of the substrate and P-well. A V _SS power line is provided.

FIG. 11 is a schematic surface diagram of a chip (so-called master) in which basic cells according to the present invention are integrated in an arrangement suitable for large-scale integrated circuits. In the figure, 21
2 is an area where input/output pads are placed, 22 is an area where an input/output (I/O) circuit connecting the input/output pads and internal circuits is placed, 23 is an area where basic cells are arranged, and 24 is an area where basic cells are used. This is a wiring area that connects circuits. In the basic cell area 23, 18 first layer Al wirings are placed in the Y direction per basic cell,
Three first-layer and second-layer Al wirings can be passed in this direction. Therefore, almost all logic circuits (such as DFF in the previous example) consisting of multiple basic cells,
This can be achieved only by wiring within the basic cell area, and does not require wiring in the wiring area. Therefore, the wiring area only needs to have the number of wiring channels to connect logic circuits, and does not require a large area. This is an advantageous condition for achieving high integration.

As shown in the above examples, the basic cells according to the present invention are NOR, which is a basic circuit that configures logic by using one or a plurality of cells in combination.
Since various circuits such as clocked inverters and flip-flops can be obtained, this cell is sufficient to realize almost all logic functions, and is suitable for efficiently constructing gate array type large-scale integrated circuits using the master slice method. It can be seen that it is. That is, using this basic cell,
Compared to the gate array type large-scale integrated circuit using the conventional master slice method, the integration density is improved, the utilization rate of transistors is improved, and a circuit using a clocked inverter can be easily realized.

Furthermore, according to the present invention, the wiring pattern for realizing a desired logic circuit using a plurality of basic cells has a two-layer structure, so that the desired logic circuit can be realized by wiring almost within the basic cell area. . Therefore, less wiring is required in the wiring area for connecting the plurality of logic circuits obtained. As a result,
The wiring area requires only a small space, the chip area can be used effectively, and a large-scale integrated circuit can be easily obtained.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram of a basic cell according to the present invention;
Fig. 2 is a pattern diagram for realizing this basic cell, and Fig. 3 a and b are respectively A-A' and B- of Fig. 2.
B' cross-sectional view, Figure 4 is an equivalent circuit diagram of an embodiment applied to a logical NOR (NOR) circuit, Figure 5 is its pattern layout diagram, and Figure 6 is an equivalent circuit diagram of an embodiment applied to a clocked inverter. The circuit diagram, Fig. 7 is its pattern layout diagram, Fig. 8 is an equivalent circuit diagram with gate symbols of an embodiment applied to a delay flip-flop (DFF) circuit, Fig. 9 is its detailed equivalent circuit diagram, and Fig. 10 is its circuit diagram. Similarly, the pattern layout diagram, FIG. 11, is a schematic diagram of the surface of a chip in which the basic cell according to the present invention is applied to a large-scale integrated circuit. TR1, TR2...P channel MOS transistor, TR3, TR4...N channel MOS transistor.

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit device in which a plurality of basic cells each consisting of a plurality of MOS transistors are arrayed and integrated on a semiconductor substrate, and a desired circuit operation is realized by a wiring pattern, wherein the basic cell is a source. Consisting of two p-channel MOS transistors that share one of their regions or drain regions, and two n-channel MOS transistors that share one of their source or drain regions, one of the p-channel MOS transistors and the n-channel MOS One of the transistors shares a gate electrode with the other of the p-channel MOS transistors and the n-channel MOS transistor.
The gate electrodes of the other MOS transistors are independent of each other, and the wiring pattern includes a first wiring layer connected to the gate electrode and the source and drain regions through contact holes, and a first wiring layer connected to this wiring layer through through holes. A semiconductor integrated circuit device comprising: a second wiring layer connected to the second wiring layer;