JPH0563944B2 - - Google Patents
Info
- Publication number
- JPH0563944B2 JPH0563944B2 JP58108108A JP10810883A JPH0563944B2 JP H0563944 B2 JPH0563944 B2 JP H0563944B2 JP 58108108 A JP58108108 A JP 58108108A JP 10810883 A JP10810883 A JP 10810883A JP H0563944 B2 JPH0563944 B2 JP H0563944B2
- Authority
- JP
- Japan
- Prior art keywords
- cell
- metal wiring
- layer metal
- wiring
- basic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000002184 metal Substances 0.000 claims description 26
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、多層金属配線構造を利用するマスタ
ースライス方式の半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a master slice type semiconductor integrated circuit that utilizes a multilayer metal wiring structure.
マスタースライス方式の半導体集積回路は、複
数の素子により構成される基本セルの集合である
セル列を、半導体基板上に複数個配列形成してマ
スターチツプとし、これに金属配線を施して所望
の論理機能を実現するものである。
In a master slice type semiconductor integrated circuit, a master chip is formed by forming a plurality of cell rows, which are a collection of basic cells made up of multiple elements, on a semiconductor substrate, and metal wiring is applied to this to create the desired logic. It is something that realizes a function.
従来の一般的なマスタースライス方式による
CMOS集積回路では、第１層金属配線と第２層
金属配線を用いて各基本セル内での回路機能を実
現している。そしてセル列の間には配線領域を設
け、各基本セルの両端から端子をこの配線領域に
導出して、配線領域にも第１層金属配線と第２層
金属配線を施すことにより、セル間の接続を行つ
ている。 By conventional general master slicing method
In a CMOS integrated circuit, a first layer metal wiring and a second layer metal wiring are used to realize circuit functions within each basic cell. Then, a wiring area is provided between the cell rows, terminals are led out from both ends of each basic cell to this wiring area, and first-layer metal wiring and second-layer metal wiring are applied to the wiring area as well. connection is being made.
このような従来の構造では、セル列の間に配線
領域を設けているため、チツプの利用率が低いと
いう問題があつた。 In such a conventional structure, since a wiring area is provided between the cell rows, there is a problem in that the chip utilization rate is low.
本発明は上記の点に鑑み、チツプの利用率の向
上を図ると共に、セル間配線の自由度の向上を図
つたマスタースライス方式の半導体集積回路を提
供することを目的とする。
SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a master slice type semiconductor integrated circuit which is capable of improving the chip utilization rate and increasing the degree of freedom in wiring between cells.
本発明においては、隣接するセル列をその間に
配線領域を設けることなく基本セルを対称パター
ンとして密に配列する。対称パターンとは、隣接
するセル列で基本セルを構成する素子の導電型が
対称となるパターンであり、線対称でも回転対称
でもよい。そして、各基本セルの回路機能は第１
層金属配線だけで実現すると共に、電源線（接地
線を含む）を隣接するセル列で共用させてセル列
の境界上に第１層金属配線により形成する。従つ
てセル間接続は第２層または第３層金属配線によ
りセル列領域上で行うことになるが、この場合、
これらの配線と各基本セルの端子とのコンタクト
位置を各基本セル領域上に一直線上に並ばないよ
うに分散させて配置するのが望ましい。
In the present invention, basic cells are densely arranged in a symmetrical pattern without providing a wiring area between adjacent cell columns. The symmetrical pattern is a pattern in which the conductivity types of elements constituting basic cells in adjacent cell rows are symmetrical, and may be linearly symmetrical or rotationally symmetrical. The circuit function of each basic cell is the first
This is realized only by layered metal wiring, and the power supply line (including the ground line) is shared by adjacent cell columns, and is formed by first layer metal wiring on the boundary between the cell columns. Therefore, connections between cells are made on the cell column area using second or third layer metal wiring, but in this case,
It is desirable that the contact positions between these wiring lines and the terminals of each basic cell are distributed and arranged so that they are not lined up in a straight line on each basic cell region.
本発明によれば、セル列間に格別な配線領域を
設けず、セル列領域上でセル間接続を行うため、
チツプ利用率が向上する。しかも、電源線とセル
内配線を第１層金属配線のみで構成し、基本セル
端子と第２層、第３層金属配線とのコンタクト位
置を基本セル領域上で分散配置させているため、
配線の自由度が高い。従つて複雑な論理集積回路
を容易に実現することができる。
According to the present invention, since inter-cell connections are made on the cell column area without providing a special wiring area between the cell columns,
Improves chip utilization. Moreover, since the power supply line and the intra-cell wiring are composed of only the first layer metal wiring, and the contact positions between the basic cell terminal and the second and third layer metal wiring are distributed over the basic cell area,
High degree of freedom in wiring. Therefore, complex logic integrated circuits can be easily realized.
以下、本発明をCMOS集積回路に適用した実
施例につき説明する。第１図は一つの基本セル部
分について、第１層金属配線まで施した状態のパ
ターンであり、第２図がこの状態での基本セルの
等価回路である。第１図において、１１はｐチヤ
ネルMOSFET−Qp1，Qp2の領域、１２はｐチヤ
ネルMOSFET−Qp3，Qp4の領域である。１３は
ｐウエルであつて、この内にｎチヤネル
MOSFET−Qo1，Qo2の領域１４およびｎチヤネ
ルMOSFET−Qo3，Qo4の領域１５が設けられて
いる。Qp1，Qo1，Qp2，Qo2，Qp3，Qo3および
Qp4，Qo4の各FET対はそれぞれ共通の多結晶シ
リコンゲート電極を有する。第１図の斜線を施し
た部分１６1〜１６4は第１層金属配線であり、１
６1はVDD線、１６2がVSS線、１６3および１６4が
セル内配線である。これら第１層金属配線１６1
〜１６4を施すことにより、第２図に示すように、
この基本セルの回路機能が実現されている。また
１７ａ〜１７ｅはこの第１層金属配線１６1〜１
６4が施された基本セルを、第２層、第３層金属
配線により他の基本セルと接続するためのコンタ
クトホールである。コンンタクトホール１７ａ〜
１７ｄは第２図の入力端子Ａ〜Ｄにそれぞれ対応
し、コンタクトホール１７ｅは同じく出力端子Ｅ
に対応する。
An example in which the present invention is applied to a CMOS integrated circuit will be described below. FIG. 1 shows a pattern of one basic cell portion, which includes the first layer metal wiring, and FIG. 2 shows an equivalent circuit of the basic cell in this state. In FIG. 1, 11 is a region of p-channel MOSFET-Q p1 and Q p2 , and 12 is a region of p-channel MOSFET-Q p3 and Q p4 . 13 is a p-well, within which there is an n-channel.
A region 14 for MOSFETs Q o1 and Q o2 and a region 15 for n-channel MOSFETs Q o3 and Q o4 are provided. Q p1 , Q o1 , Q p2 , Q o2 , Q p3 , Q o3 and
Each FET pair Q p4 , Q o4 has a common polycrystalline silicon gate electrode. The hatched portions 16 1 to 16 4 in FIG. 1 are the first layer metal wiring;
6 1 is a V DD line, 16 2 is a V SS line, and 16 3 and 16 4 are intra-cell wiring lines. These first layer metal interconnections 16 1
By applying ~ 164 , as shown in Figure 2,
The circuit function of this basic cell is realized. Further, 17a to 17e are the first layer metal wirings 16 1 to 1
This is a contact hole for connecting a basic cell coated with 6 4 to other basic cells through second and third layer metal wiring. Contact hall 17a~
17d correspond to the input terminals A to D in FIG. 2, and the contact hole 17e corresponds to the output terminal E.
corresponds to
第３図はこのような基本セルのセル列パターン
を模式的に示している。即ちセル列１８，１８1，
１８2…は、隣接するものを対称パターンとして、
隣接するもの同志でVDD線１６1，１６11，１６12，
…およびVSS線１６2，１６21，１６22，…を共用
させて密に配列している。 FIG. 3 schematically shows a cell column pattern of such basic cells. That is, cell rows 18, 18 1 ,
18 2 ... is a symmetrical pattern with adjacent ones,
Adjacent V DD lines 16 1 , 16 11 , 16 12 ,
. . . and V SS lines 16 2 , 16 21 , 16 22 , . . . are shared and densely arranged.
本実施例によれば、セル列がその間に格別な配
線領域を設けることなく密に配列され、しかも隣
接するセル列で電源線を共用させているため、高
密度集積化によりチツプの利用率向上が図られ
る。また電源線と全てのセル内配線を第１層金属
配線により構成し、セル領域上で第２層以上の金
属配線を用いてセル間接続を行うから、セル間接
続配線のレイアウトが容易である。しかもこの場
合、第２層以上の金属配線のコンタクトホール位
置をセル領域上で分散配置しているため、配線の
自由度が高い。即ち、第２層、第３層金属配線は
通常CADシステムを用いて設計され、セル列と
並行して走る配線が多い。例えば第１図のパター
ンにおいて、コンタクトホールの位置として一般
的に好ましいと考えられるのは、セルの両側を走
る電源線から遠いｐチヤネルMOSFET領域とｎ
チヤネルMOSFET領域との境界領域上である。
しかしこの領域にコンタクトホールを一直線上に
並べたとすると、セル列と並行する第２層、第３
層配線を曲げることなくコンタクトホールで下層
の端子に接続することが大きく制約される。本実
施例ではコンタクトホール位置を分散させている
ため、このような制約が少ない。 According to this embodiment, the cell rows are densely arranged without any special wiring area between them, and the power supply lines are shared between adjacent cell rows, which improves the chip utilization rate through high-density integration. is planned. In addition, the power supply line and all intra-cell wiring are constructed from first-layer metal wiring, and inter-cell connections are made using second-layer or higher-layer metal wiring on the cell area, so the layout of inter-cell connection wiring is easy. . Moreover, in this case, since the contact hole positions of the metal wiring in the second layer or higher are distributed over the cell region, the degree of freedom in wiring is high. That is, the second and third layer metal interconnections are usually designed using a CAD system, and many of the interconnections run parallel to the cell columns. For example, in the pattern shown in Figure 1, the generally preferred locations for contact holes are the p-channel MOSFET region far from the power supply lines running on both sides of the cell, and the n-channel MOSFET region far from the power supply lines running on both sides of the cell.
It is on the boundary area with the channel MOSFET area.
However, if the contact holes are arranged in a straight line in this region, the second and third layers parallel to the cell rows
There are significant restrictions on connecting to lower layer terminals through contact holes without bending layer wiring. In this embodiment, since the contact hole positions are dispersed, there are few such restrictions.
本発明は上記実施例に限られない。例えば基本
セルは実施例で示したCMOS構造以外のCMOS
構造、あるいはｐチヤネルMOSやｎチヤネル
MOS構造でもよく、またバイポーラトランジス
タを用いたものであつてもよい。 The present invention is not limited to the above embodiments. For example, the basic cell is a CMOS structure other than the CMOS structure shown in the example.
structure, or p-channel MOS or n-channel
It may have a MOS structure or may use a bipolar transistor.
第１図は本発明の一実施例につき第１層金属配
線を施した状態での基本セル部分のパターンを示
す図、第２図はその状態での基本セルの等価回路
図、第３図は同じくその基本セルを用いたセル列
パターンを示す図である。
１６1〜１６4…第１層金属配線、１６1，１６
11，１６12，… …VDD線、１６2，１６21，１６
22，… …VSS線、１７ａ〜１７ｅ…コンタクト
ホール、１８，１８1，１８2，… …セル列。
Fig. 1 is a diagram showing the pattern of the basic cell portion with the first layer metal wiring applied according to an embodiment of the present invention, Fig. 2 is an equivalent circuit diagram of the basic cell in that state, and Fig. 3 is It is a figure showing a cell row pattern using the same basic cell. 16 1 to 16 4 ...first layer metal wiring, 16 1 , 16
11 , 16 12 , ... V DD line, 16 2 , 16 21 , 16
22 ,...V SS line, 17a to 17e...contact hole, 18 , 181, 182 ,...cell row.
Claims (1)
より構成される基本セルが複数個形成されたセル
列を複数個配列形成し、多層の金属配線を施して
所望の論理機能を実現する半導体集積回路におい
て、 基本セルを構成する素子の導電型が隣接するセ
ル列で対称となるように密に配置し、各基本セル
を構成する素子の接続を第１層金属配線だけで実
現すると共に、電源線を隣接するセル列で共用さ
せてセル列の境界上に第１層金属配線により配設
し、かつ前記各基本セル間の接続を第２層または
第３層金属配線で行つたことを特徴とする半導体
集積回路。[Claims] 1. A plurality of cell rows each having a plurality of basic cells formed by connecting a plurality of elements are formed on a semiconductor substrate, and a desired logic function is achieved by applying multilayer metal wiring. In the semiconductor integrated circuit that will be realized, the conductivity types of the elements that make up the basic cells will be arranged closely so that they are symmetrical in adjacent cell rows, and the connections of the elements that make up each basic cell will be realized using only the first layer metal wiring. At the same time, the power supply line is shared by adjacent cell columns and arranged by first layer metal wiring on the boundary between the cell columns, and the connection between each of the basic cells is made by second or third layer metal wiring. A semiconductor integrated circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10810883A JPS59232442A (en) | 1983-06-16 | 1983-06-16 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10810883A JPS59232442A (en) | 1983-06-16 | 1983-06-16 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59232442A JPS59232442A (en) | 1984-12-27 |
| JPH0563944B2 true JPH0563944B2 (en) | 1993-09-13 |
Family
ID=14476089
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10810883A Granted JPS59232442A (en) | 1983-06-16 | 1983-06-16 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59232442A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0644613B2 (en) * | 1985-10-22 | 1994-06-08 | 日本電気株式会社 | Semiconductor device |
| JPH05136380A (en) * | 1991-11-13 | 1993-06-01 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated circuit device |
| KR100229577B1 (en) * | 1996-01-31 | 1999-11-15 | 포만 제프리 엘 | Integrated circuit chip having gate array book personalization using local interconnect |
| JP2008147331A (en) * | 2006-12-08 | 2008-06-26 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit and method of modifying semiconductor integrated circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5120268A (en) * | 1974-08-08 | 1976-02-18 | Takashi Ishikawa | Taika * tainetsusei goseijushi |
| JPS5582450A (en) * | 1978-12-15 | 1980-06-21 | Nec Corp | Semiconductor integrated circuit |
| JPS586157A (en) * | 1981-07-03 | 1983-01-13 | Nippon Telegr & Teleph Corp <Ntt> | Cmos master slice lsi |
-
1983
- 1983-06-16 JP JP10810883A patent/JPS59232442A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5120268A (en) * | 1974-08-08 | 1976-02-18 | Takashi Ishikawa | Taika * tainetsusei goseijushi |
| JPS5582450A (en) * | 1978-12-15 | 1980-06-21 | Nec Corp | Semiconductor integrated circuit |
| JPS586157A (en) * | 1981-07-03 | 1983-01-13 | Nippon Telegr & Teleph Corp <Ntt> | Cmos master slice lsi |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59232442A (en) | 1984-12-27 |
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