JP2634800B2 - Semiconductor integrated circuit standard cell - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a standard cell for a semiconductor integrated circuit, and more particularly to a standard cell effective for reducing a chip area.

[Conventional technology]

2. Description of the Related Art Conventionally, a standard cell of a semiconductor integrated circuit is composed of required elements and a plurality of wirings connecting these elements, and constitutes a cell circuit having required functions such as logic. When this cell is configured as an integrated circuit, it is necessary to connect a plurality of cells to each other or to another external circuit. For this reason, in each cell, an input contact and an output contact are provided on one conductive layer for performing cell internal wiring in the cell region, and the input contact and the output contact are connected to another conductive layer.
Wiring to each other and to the outside is performed via other conductive layers.

[Problems to be solved by the invention]

In the above-mentioned conventional standard cell, one conductive layer provided on the cell, that is, the input contact and the output contact of the first conductive layer are fixedly provided at positions laid out in advance, so that they are provided above this cell. When the cells are connected to each other and to external circuits using another conductive layer, that is, the second conductive layer, the extension of the second conductive layer may be restricted. For example, in the case where it is difficult to extend the second conductive layer to the position of the input contact or the output contact and directly connect the first conductive layer here, for the reason of the layout of a plurality of various wirings provided, It is required that the first conductive layer is once drawn out of the cell region and is configured to make contact with the second conductive layer at this position.

For this reason, it is necessary to secure a contact area for connecting the first and second conductive layers in a place different from the standard cell area, and by newly securing a space for this contact area, the cell area is reduced. The integration density is reduced, or it is an obstacle in reducing the chip area.

[Means for solving the problem]

The semiconductor integrated circuit standard cell of the present invention enables connection of both conductive layers without providing a special region for connecting the first and second conductive layers, thereby improving the integration density of the cell and reducing the chip area. This enables reduction.

The semiconductor integrated circuit standard cell of the present invention has a first conductive layer as each of input and output contact layers extending over substantially the entire width direction of the standard cell region.
A large number of second conductive layers, which are insulated and separated from these first conductive layers, extend in parallel in a direction orthogonal to the first conductive layers, and any one of these second conductive layers is input. Each of the output wirings is selected, and a contact portion is provided at each position where the first conductive layer and the selected second conductive layer intersect in the cell region.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a plan layout diagram of an embodiment of the present invention. Here, an example in which a non-inverting buffer using two complementary MOS transistors (CMOS) composed of a P-channel MOS transistor and an N-channel MOS transistor is illustrated. Is shown.

That is, in the standard cell region of the semiconductor integrated circuit 1, the P-channel MOS transistor row 2 and the N-channel MOS transistor row 3 are opposed to each other with an appropriate distance therebetween. The P-channel MOS transistor row 2 and the N-channel MOS transistor row 3 are respectively composed of two transistors 2A, 2B and 3A, by a polycrystalline silicon layer 4 and a first aluminum layer 5.
3B, corresponding P and N channels
CMOS transistors 6A and 6B are constituted by the MOS transistors 2A and 3A and 2B and 3B, respectively.

In addition, one of the CMOSs 6A has the polycrystalline silicon layer 4 and the first
Portions 4a and 5a of the aluminum layer 5 connect to the input contact layer 7, and the other CMOS 6B connects to the polycrystalline silicon layer 4 and the output contact layer 8 at other portions 4b and 5b of the first aluminum layer 5. doing. The input contact layer 7 and the output contact layer 8 are made of a first aluminum wiring formed simultaneously with the first aluminum wiring 5, and extend in the width direction of the MOS transistor rows 2 and 3 on both sides of each of the MOS transistor rows 2 and 3. The length is set so as to reach substantially the entire width of the cell region.

In the cell thus configured, the second aluminum layer 10 provided on the insulating film (not shown) extends in the length direction of the MOS transistor rows 2 and 3 on the cell region as shown in FIG. It extends in a direction orthogonal to the contact layer 7 and the output contact layer 8. Here, the second aluminum layer 10
Are arranged in parallel, some of which are
A and another part are provided as ground wirings 10B, respectively, and a wiring row 10C connected to input and output is provided between these wirings 10A and 10B.

The power supply line 10A is connected to the P-channel MOS transistor row 2 by the power supply contact 11, and is connected to the ground wiring 10B.
Are connected to the N-channel MOS transistor row 3 by a ground contact 12. Also, input and output wiring arrays 10
In C, an input contact 13 and an output contact 14 are arranged at arbitrary intersections among the intersections of the input contact layer 7 and the output contact layer 8, and the respective connections are made.

Therefore, according to this configuration, the input and output wiring columns
Input contact 13 and output contact 14 provided at 10C
Can be set at arbitrary positions in the length direction of the input contact layer 7 and the output contact layer 8, respectively. For this reason, even when the arrangement position of the contact is restricted by the cell layout or another wiring layout, the contact can be arranged at a relatively free position in the cell region.

Thus, there is no need to make a connection between the first conductive layer and the second conductive layer outside the cell region, and it is not necessary to secure a space therefor. Therefore, the space can be reduced by this amount, and the cell integration density and the chip area can be reduced.

Here, the above embodiment is merely an example of a standard cell, and can be similarly applied to cells having other various configurations.

Further, in the previous example, the case where the first conductive layer and the second conductive layer are each formed of an aluminum layer has been described. However, when each is a polycrystalline silicon layer, one is a polycrystalline silicon layer and the other is an aluminum layer. It is also possible to use various combinations such as when one or both are a polycide layer or a high melting point metal layer.

〔The invention's effect〕

As described above, according to the present invention, the first conductive layer extends in substantially the entire width direction of the standard cell region, and the second conductive layer extends in a direction orthogonal to the first conductive layer. Since the contact portion is arranged at an arbitrary position where the crossing is made, the contact portion can be arranged in the cell region, and no special space is required for the contact,
This area can be reduced to improve the cell integration density and reduce the chip area.

[Brief description of the drawings]

FIG. 1 is a plan layout diagram showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... P-channel MOS transistor row, 2A, 2B ... P-channel MOS transistor, 3 ... N-channel MOS transistor row, 3A, 3B ... N-channel MOS transistor, 4 ... Polycrystalline silicon Layer 5, aluminum layer, 6A, 6B CMOS, 7 input contact layer (first aluminum layer), 8 output contact layer (first aluminum layer), 10 second aluminum layer, 11 …… Power contact, 12 …… Ground contact, 13 …… Input contact, 14
...... Output contact.

Claims (2)

(57) [Claims] 1. A semiconductor integrated circuit standard cell comprising a required element and a conductive layer, wherein a first conductive layer as each of input and output contact layers is provided over substantially the entire width direction of the standard cell region. And a plurality of second conductive layers that are insulated and separated from these first conductive layers are extended in parallel in a direction orthogonal to the first conductive layers. Arbitrary ones are selected as input and output wirings from among them, and contact portions are arranged at respective positions where the first conductive layer and the selected second conductive layer intersect in the cell region. A standard cell for a semiconductor integrated circuit, characterized in that: 2. The semiconductor integrated circuit standard cell according to claim 1, wherein the first conductive layer and the second conductive layer are any one of an aluminum layer, a polycrystalline silicon layer, a polycide layer, and a refractory metal layer. .