JP3236745B2 - LSI chip layout method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates is related to layout method for highly integrated LSI chip using standard cell method.

[0002]

2. Description of the Related Art LSI layout systems can be broadly classified into a macro cell system, a standard cell system, and a gate array system.
Among these, the standard cell system has a degree of integration and design man-hours intermediate between the macro cell system and the gate array system, and is based on channel wiring (T. Yoshimura and ESKuh, "Efficient Algorit
hms for Channel Router ", IEEE Tans.on Computer-Aide
d Design, Vol.CAD-1, No.1, pp.25-35,1986)
Since 0% wiring is guaranteed, it is widely used for LSI design.

FIG. 8 shows a conventional logic circuit comprising a cell row composed of a plurality of standard cells 1 and a first metal channel wiring 2 made of aluminum or the like between the cell rows, a second metal channel lead-in wiring 3 and the like. FIG. 2 is a diagram in which a part of the layout of the LSI chip is extracted. The upper row of cells is 1
Standard cells 1 and two standard cells 1 in the lower cell row.
Was expressed.

The longitudinal direction of the gate electrode 4 made of polysilicon or polycide is perpendicular to the direction in which the standard cells 1 are arranged (the horizontal direction in FIG. 8), and the diffusion islands 5 as a group of transistor rows are horizontal. Are arranged in different directions. That is, the direction of the gate length of the MOS transistor is the same direction as the arrangement of the standard cells 1.

A PMOS transistor array (a plurality of PMOS transistors are arranged in a row in the gate length direction and is arranged in the horizontal direction in FIG. 8) 6 is a well provided so as to surround the diffusion island 5. 7 (N well), and the well 7 and a power supply line (first power supply line: VDD)
Numeral 8 is connected by a substrate contact 9 so that a substrate bias is applied to the well 7.

An NMOS transistor array (a plurality of NMOS transistors)
A transistor 10 in which transistors are arranged in the same direction as the PMOS transistor array 6 is formed in a substrate (P substrate), and this substrate and a ground line (second power line: VSS) 11
Are connected by a substrate contact 9 to apply a substrate bias.

The power supply line 8 and the ground line 11 are made of a first metal layer such as aluminum, and are horizontally arranged so as to sandwich the diffusion island 5 of the PMOS transistor array 6 and the diffusion island 5 of the NMOS transistor array 10 from above and below in FIG. The power supply line 12 and the ground supply line 13 made of the same first metal layer are wired in a vertical direction to the power supply node and the ground node of the MOS transistor. Have been.

The wiring layer in the standard cell 1 includes external terminals 14
8 is also formed of a polysilicon layer, a polycide layer, or a metal second layer, and has a vertically passing wiring (a wiring that passes through one standard cell in the vertical direction and is not shown in FIG. 8). Is the same. If the wiring cannot be completed within the standard cell 1, the tip of the vertical wiring 15 drawn out from the inside in the vertical direction is drawn to the area outside the standard cell 1, and the protruding wiring of the metal first layer provided there is provided. 16 are connected.

Reference numeral 17 denotes a diffusion contact for connecting a diffusion region serving as a source or drain to a polysilicon layer, a polycide layer, or a first metal layer, and 18 denotes a polysilicon layer, a polycide layer, a first metal layer, or a first metal layer. This is a through hole for connecting the two layers.

[0010]

However, in the above-mentioned conventional layout system, the distance L between the power supply line 8 and the ground line 11 for connection between the standard cells 1 is set to be equal to the gate width of the driver or the like. It is necessary to standardize according to a large MOS transistor. For this reason, even if MOS transistors having a small gate width are used in order to reduce power consumption and fan inload, they are arranged in the same column as other MOS transistors having a large gate width. There is a problem that a useless area 19 is generated between the line 8 and the ground line 11.

The wiring in the standard cell 1 is made of metal 1
Since the power supply line 12 and the ground supply line 13 formed by the layers hinder each other, the wiring of the first metal layer cannot be used effectively. Therefore, wiring different from the first metal layer from inside the standard cell 1, that is, polysilicon, polycide, etc. Alternatively, it may be necessary to take a method of using the vertical wiring 15 of the second metal layer to extend to the outside of the power supply line 8 and the ground line 11 and then connecting with the horizontal wiring 16 of the first metal layer. there were. For this reason, an increase in the wiring channel region, a decrease in the region through which the wiring can pass through the second metal layer, and the like are caused, and there is a problem that the integration density is hindered.

An object of the present invention is to reduce the useless area and eliminate the protruding wiring to improve the degree of integration .
Layout method of L SI chip is to provide a.

[0013]

For this purpose, the L of the present invention is used.
The layout method of the SI chip is a standard gate width standard.
Quasi-gate width transistor arrays and smaller gates
Lay standard cells with narrow gate width transistor arrays
Out of the gate of the small gate width transistor
The total width in the direction perpendicular to the longitudinal direction of the
Lengthwise direction of the above gate electrode of the small gate width transistor array
The maximum height in the direction parallel to the first and second power lines
If the distance is larger than the sum of
The array of cells is composed of multiple standard cells.
The gate electrode is shaped so that the direction parallel to the
Inverted MOS transistor array formed and reverse to the above
In addition, the direction perpendicular to the cell row arrangement direction is the longitudinal direction.
Non-inverted MOS transistor with gate electrode formed
It is a star row.

[0014]

[0015]

[0016]

[0017]

[0018]

[0019]

According to the present invention, a MOS transistor having a small gate width is provided.
The column part is an inverted MOS transistor column under predetermined conditions.
These are efficiently arranged in space.
It is.

[0020]

[0021]

[0022]

[0023]

[0024]

[0025]

Embodiments of the present invention will be described below. In the drawings used in the following description, the same or similar components as those shown in FIG. In the present invention, a non-inverted MOS in which a gate electrode is formed so that a longitudinal direction is a direction perpendicular to a direction of a standard cell row is used as a standard cell.
Transistor row (multiple MOs parallel to the standard cell row)
A non-inverted standard cell (conventional standard cell shown in FIG. 8) consisting solely of S transistors arranged in a row,
An inverted standard consisting only of an inverted MOS transistor array having a gate electrode formed so that the longitudinal direction is parallel to the standard cell array (a plurality of MOS transistors are arranged in a row in a direction perpendicular to the standard cell array). Cell and non-inverted MO
Three types of standard cells, that is, mixed type standard cells including both S transistor rows and inverted MOS transistor rows are used. In the following, a non-inverted standard cell is referred to as an A type standard cell 1A,
The inverted type standard cell is called a B type standard cell 1B, and the mixed type standard cell is called a C type standard cell 1C.

[First Embodiment] FIG. 2 shows such A, B,
A logic circuit composed of three lines of cell columns 21 constituted by combining three types of standard cells 1A, 1B and 1C of C and a channel wiring 2 and a channel lead-in wiring 3 wired in a wiring channel region, and no standard cell is used. FIG. 3 is a diagram showing a layout of an LSI chip composed of a macro cell 22 composed of I / O pads and I / O pads 23 provided in the periphery. Note that FIG.
In the cell row 21, three types of standard cells 1A, 1B, 1C
Are used, but two types of cells may be used.

[0027] Figure 1 is a diagram showing a logic circuit, the lower the arranged standard cell 1A, and 1B in the cell column, a standard cell 1C arranged in the upper, channel routing thereof wiring channel region 2 and the channel The connection is made by the lead-in wiring 3. Reference numeral 20 denotes a vertical passage wiring. Here, the predetermined
Under the condition (1), the MOS transistor rows having a gate width smaller than the standard are collectively inverted, that is, the longitudinal direction of the gate electrode 4 (the gate width direction of the MOS transistor alone) is parallel to the cell row direction. (The left-right direction in FIG. 1). by this,
The generation of unnecessary gaps in the cell is minimized,
The cell size can be reduced accordingly.

In this embodiment, it is assumed that the condition for inverting the MOS transistor array in this manner is to reduce the area. In this embodiment, the following equation is used as a criterion for reducing the area, which represents a condition for reducing a useless gap between the power supply line 8 or the ground line 11 and the MOS transistor array. Σwi> s + hmax (1)

Here, wi is the lateral width of the diffusion island 5 to be inverted (that is, the width of the MOS transistor column in the column direction: see FIG. 8). Σwi is the total of the widths wi of the individual diffusion islands 5 in the case where there are two or more diffusion islands 5 in the horizontal direction in FIG. 8 in one standard cell 1 (one in FIG. 8). Here, Σwi <L. L is power line 8 and ground line 1
This is the interval between the two. h is the height of the transistor row to be inverted (the height in the gate width direction: see FIG. 8), and h
max is its maximum value. s is the distance from the diffusion island 5 to the power supply line 12 and the ground supply line 13 when it is inverted (see FIG. 1).

The above equation (1) indicates that the greater the value on the left side than the value on the right side, the greater the effect of inversion. For example, assuming that the unit is μm, Σwi = 18, s
If = 2, a standard cell is created such that hmax is inverted up to 15 and non-inverted above hmax.

[Second Embodiment] This second embodiment is particularly for a mixed type standard cell 1C. FIG. 3 is a plan view of the mixed standard cell 1C, and FIG. 4 is a view showing a pattern of the metal second layer 24 and the well (N-well) 7 of the mixed standard cell 1C of FIG. In the mixed-type standard cell 1C of the second embodiment, only the inverter component 25 that outputs a signal from the mixed-type standard cell 1C to the outside is a non-inverted type.
The part 26 constituting another logic circuit is of an inverted type.
Thereby, the cell width (length in the cell column direction) of the mixed standard cell 1C shown here is set to 3/3 of the cell width (33 pitch) of the standard cell 1 according to the general layout shown in FIG. It was reduced to 4. FIG. 7 is a diagram showing a pattern of the metal second layer 24 and the well 7 of the standard cell 1 shown in FIG.

Although the MOS transistor has the advantage that low power and low fan inload can be realized by reducing the gate width, there is a possibility that the driving capability is insufficient. Therefore,
In this embodiment, a MOS transistor connected only inside the cell has a reduced gate width, and a MOS transistor as a driver (inverter) connected to output a signal to the outside of the cell has a large gate width. It is composed of an inverted transistor. As a result, a reduction in driving capability does not occur.

The mixed standard cell 1 of the second embodiment
In C, the PMOS transistor row 6 and the NMOS transistor row 10 of the inverted transistor row are paired and arranged adjacent to each other. That is, as shown in FIG. 3, the PMOS transistor line 6, the NMOS transistor line 10, the NMOS transistor line 10, the PMOS transistor line 6, the PMOS transistor line 6, and the NMOS transistor line 10 are arranged in this order from the left side in the longitudinal direction. I have.

Thus, the P of the adjacent inverted pair is obtained.
The power supply line 12 and the ground supply line 13 can be shared between the MOS transistor rows 6 or between the pair of NMOS transistor rows 10, and the cell area can be reduced. The PMOS transistor row 6 requiring the well 7 has a pair of adjacent PMOS transistors.
The wells 7 are shared by the transistor rows 6. As described above, in the present embodiment, it is not necessary to separate the well 7 for each inverted transistor row, and the substrate contact 9 from the well 7 can be easily obtained. As a result, the power supply and the ground are also stabilized. These effects are not limited to the mixed type standard cell 1C, and the same effects can be obtained with the inverted type standard cell 1B.

Further, in the mixed standard cell 1C of the second embodiment, the power supply line 12 and the ground supply line 1 described above are utilized by utilizing the area between the inverted MOS transistor rows.
Not only 3 but also wiring in the cell. In a normal non-inverted MOS transistor train, internal wiring cannot be performed except for adjacent nodes.
In the inverted type, since a gap region is formed in a direction perpendicular to the wiring direction of the power supply line 8 and the ground line 11, connection can be performed by passing internal wiring of polysilicon, polycide, and the first metal layer in that region. it can. As a result, as compared with the conventional standard cell 1 of FIG. 6, the number of columns of the protruding wiring 16 outside the cell is reduced from six columns shown in FIG. 7 to zero columns shown in FIG.
Further, the usage rate of the metal second layer 24 was reduced from 16 columns shown in FIG. 7 to 6 columns as shown in FIG. Such an operation and effect is the same for the inverted standard cell 1B.

[Third Embodiment] The third embodiment is an embodiment characterized by the wiring structure of the power supply line and the ground line.
FIG. 5 is a diagram showing an example. Here, the power line 2
7. A ground line 28 is formed on the transistor by a third metal layer (of course via an interlayer insulating film). The area occupied by the power supply line 8 and the ground line 11 of the metal first layer having the structure shown in FIG. 1 is in the direction along the transistor row when not inverted, so that the power supply line 8 and the ground line Although it is possible to arrange the lines 11 in an overlapping manner, in the case of inversion, the power line 8 and the ground line 11 are arranged so as to overlap with the signal line because the direction is perpendicular to the transistor row and overlaps with the signal line. It is impossible.

Therefore, in the present embodiment, the inverted standard cell 1B
In order to reduce the cell area even in the mixed standard cell 1C or the mixed type standard cell 1C, metal 1
By using the third metal layer instead of the layer, the power supply line 27 and the ground line 28 can be arranged on the transistor.

At this time, since the channel lead-in line 3 connected to the channel wiring 2 is made of polysilicon, polycide, the second metal layer, etc., the power supply line 27 of the third metal layer is used.
The ground line 28 does not obstruct the wiring, and the power line 2
7. The ground line 28 can be formed by thick wiring, and the power supply line and the ground line can be stabilized. A power supply node of the transistor from the power supply line 27 and the ground line 28,
The connection to the ground node is made by a power supply line 12 and a ground supply line 13 of the second metal layer.
By arranging these metal second layer wirings on the transistor, the cell area can be further reduced.

[0039]

As described above , according to the present invention , in the layout of the standard cell system of the LSI, there are great effects on cell area reduction, low power consumption, and stabilization of power supply and ground.
Moreover, the operation speed is not adversely affected. And the prescribed article
MOS transistor with a small gate width if the condition is satisfied
The rows are inverted and the standard cell area is reliably reduced.
Can be reduced.

[Brief description of the drawings]

FIG. 1 shows a non-inverted standard cell according to a first embodiment of the present invention;
FIG. 4 is a plan view of a layout of a part of a cell row including an inverted standard cell and a mixed standard cell.

FIG. 2 is a plan view of a layout of an LSI chip composed of a logic circuit composed of a cell row composed of a non-inverted standard cell, an inverted standard cell, and a mixed standard cell and a macro cell according to the first embodiment;

FIG. 3 is a plan view of a layout of a mixed-type standard cell showing a second embodiment.

FIG. 4 is a plan view showing a second metal layer and a well portion of the standard cell of FIG. 3;

FIG. 5 is a view showing a third embodiment, in which metal third
FIG. 5 is a plan view of a layout of a cell row including a non-inverted standard cell, an inverted standard cell, and a mixed standard cell in which a power line and a ground line by layers are wired.

FIG. 6 is a plan view of a layout of a conventional standard cell.

FIG. 7 is a plan view showing a second metal layer and a well portion of the standard cell of FIG. 6;

FIG. 8 is a plan view of a layout of a conventional standard cell.

[Explanation of symbols]

1: Conventional standard cell 1A: Non-inverted standard cell 1B: Inverted standard cell 1C: Mixed standard cell 2: Channel wiring (metal first layer) 3: Channel lead-in wiring (polysilicon, polycide, or metal second) 4): Gate electrode (polysilicon or polycide) 5: Diffusion island 6: PMOS transistor array 7: Well 8: Power supply line (metal first layer) 9: Substrate contact 10: NMOS transistor array 11: Ground line (metal layer) 12: power supply line (metal first layer) 13: ground supply line (metal first layer) 14: external terminal (polysilicon, polycide, or metal second layer) 15: vertical wiring (polysilicon, polycide, or (Metal second layer) 16: Protruding wiring (Metal first layer) 17: Diffusion contact 18: Through hole 19: Waste area 20: Vertical Direct passage wiring 21: Cell row 22: Macro cell 23: I / O pad 24: Metal second layer 25: Inverter 26: Other circuit part 27: Power supply line (Metal third layer) 28: Ground line (Metal third) layer)

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-314847 (JP, A) JP-A-60-20532 (JP, A) JP-A-6-69471 (JP, A) JP-A-60-1985 17931 (JP, A) JP-A-4-212438 (JP, A) JP-A-6-216251 (JP, A) JP-A-4-132255 (JP, A) (58) Fields investigated (Int. ⁷ , DB name) H01L 21/82 H01L 27/04

Claims (1)

(57) [Claims] 1. A standard gate width transformer having a standard gate width.
Small gate width transistors with a gate array and smaller gate width
When laying out a standard cell having a transistor row, the longitudinal direction of the gate electrode of the small gate width transistor row
The total width in the direction perpendicular to
In the direction parallel to the longitudinal direction of the gate electrode of the transistor row.
From the sum of the maximum height and the distance to the first or second power line
If the gate width is too large
Direction parallel to the direction of the cell row consisting of standard cells
Inverted MOS with gate electrode formed in the longitudinal direction
Transistor row, in the opposite case, the direction perpendicular to the cell row direction
Non-inverted with the gate electrode formed so that the direction is the longitudinal direction
LSI chip characterized by a MOS transistor array
Layout method.