JPS6324636A - Semiconductor integrated circuit standard cell - Google Patents

Abstract

PURPOSE:To contrive improvement in the degree of integration of the title standard cell by a method wherein the first conductive layer is provided on the region ranging over almost overall width direction of a standard cell, the second conductive layer is provided in the direction crossing at right angle with the first conductive layer, and a contact part is provided at the arbitrary position where both conductive layers are intersect each other. CONSTITUTION:P-and N-channel MOS transistor TR columns 2 and 3 are opposingly arranged at a propper interval on the standard cell region of an integrated circuit 1. Then, columns 2 and 3 are composed of two TRs 2A and 2B, and TRS 3A and 3B respectively using a polycrystalline Si layer 4 and the first Al layer 5, and CMOS 6A and 6B are composed of the corresponding P and N type MOSTR 2A and 2B, and 2B and 3B respectively. Then, the CMOS 6A on one side is connected to an input contact point layer 7 using the parts 4a and 5a of the layers 4 and 5, and the other CMOS 6B is connected to an output contact point layer 8 using the parts 4B and 5B of the layers 4 and 5. The output contacts 13 and 14 can be provided at an arbitrary position in the longitudinal direction of the layers 7 and 8 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit standard cell, and particularly to a standard cell that is effective in reducing the chip area.

[Conventional technology]

A standard cell of a conventional semiconductor integrated circuit is composed of required elements and a plurality of wirings connecting these elements, and constitutes a cell circuit having required functions such as logic. and,
When configuring the cells as an integrated circuit, it is necessary to wire-connect the cells to each other or to other external circuits. For this reason, each cell is provided with an input contact and an output contact on a conductive layer that performs cell internal wiring within the cell area, and these input and output contacts are connected to another conductive layer, and this other conductive layer is connected to the other conductive layer. Wiring to each other and to the outside is performed through the

[Problem that the invention seeks to solve]

In the conventional standard cell described above, the second conductive layer provided in the cell, that is, the input contact and the output contact of the first conductive layer, are fixedly provided at the positions laid out in advance. Another conductive layer, i.e. the second
When connecting cells to each other and to external circuits using conductive layers, there may be restrictions on the extension of this second yL conductive layer. For example, if it is difficult to extend the second conductive layer to the manual contact or output contact position and make a direct connection with the first conductive layer there due to the layout of various wirings, It is required that a part of the first conductive layer be drawn out to the outside of the cell region and be configured to make contact with the second conductive layer at this position.

Therefore, it is necessary to secure a contact area for connecting the first and second conductive layers in a location separate from the standard cell area, and by securing a new space for this contact area, the cell This reduces the integration density or becomes an obstacle to reducing the chip area.

[Means for solving problems]

The semiconductor integrated circuit standard cell of the present invention enables connection of both conductive layers without providing a special area for connecting the first and second conductive layers, thereby improving cell integration density and reducing chip area. This makes it possible to

In the semi-quadrilateral integrated circuit standard cell of the present invention, a first conductive layer extends over substantially the entire width direction of the standard cell region, a second conductive layer extends in a direction perpendicular to the first conductive layer, A contact portion is provided at an arbitrary position where both conductive layers intersect.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

The figure is a plan layout diagram of an embodiment of the present invention, in which a P-channel MO3) transistor and an N-channel MO5 transistor are shown.
) Complementary MOS transistor (0
An example of a non-inverting buffer using two MO5) is shown.

That is, in the standard cell area of the semiconductor integrated circuit l, P
channel MO3) transistor row 2 and N channel MO3)
The transistor array 3 is arranged opposite to the transistor row 3 with an appropriate distance.

These P-channel MOS transistor array 2 and N-channel MOS transistor array 3 each have two transistors 2 formed by a polycrystalline silicon layer 4 and a first aluminum layer 5.
A, 2B and 3A, 3B, and the corresponding P and N channels MO5I - transistors 2A and 3A
2B and 3B constitute CMOs 36A and 6B, respectively.

One CMO 56A has an input contact layer 7 formed by the polycrystalline silicon layer 4 and parts 4a and 5a of the first aluminum layer 5.
The other OMO 36B is connected to the output contact layer 8 through the other portions 4b and 5b of the polycrystalline silicon layer 4 and the first aluminum layer 5. These input contact layer 7 and output contact N8 are made of first aluminum wiring formed at the same time as the first aluminum wiring 5, and are formed on both sides of each MO3) transistor row 2, 3 in the width direction of the MOS transistor row 2, 3. The length is set to cover approximately the entire width of the cell area.

In the cell configured in this manner, the second aluminum layer 1O disposed on the insulating film (not shown) is directed in the length direction of the MOS transistor array 2°3 on the cell region, that is, in the direction of the input It extends in a direction perpendicular to the contact layer 7 and the output contact layer 8. Here, a plurality of second aluminum layers 10 are arranged in parallel, and some of them are arranged as power supply wiring 10A, and the other part is arranged as ground wiring *10B, and these wirings 10A, IOB A wiring array 10C connected to inputs and outputs is arranged between them.

The power supply wiring 10A is connected to the P-channel MO transistor array 2 through a power contact 11, and the ground wiring 10B is connected to the N-channel MO transistor array 2 through a ground contact 12.
It is connected to the OS transistor row 3. Further, the input and output wiring rows 10C include the input contact layer 7 and the output contact layer 8.
An input contact 13 and an output contact 14 are arranged at an arbitrary intersection position among the intersections, and the respective connections are made.

Therefore, according to this configuration, input and output wiring row 1
Input contact 13 and output contact provided at 0C) 1
4 can be set at any position in the length direction of the input contact layer 7 and the output contact layer 8, respectively. Therefore, even if the arrangement position of the contact is restricted by the cell layout, other wiring layout, etc., the contact can be arranged at a relatively free position within the cell region.

Thereby, there is no need to connect the first conductive layer and the second conductive layer outside the cell area, and there is no need to secure a space for this purpose. Therefore, the space can be reduced by this amount, and the cell integration density and chip area can be reduced.

Here, the embodiment described above is merely an example of a standard cell, and can be similarly applied to cells having various other configurations.

In addition, in the previous example, the case where the first conductive layer and the second conductive layer were each made of an aluminum layer was explained, but if each is a polycrystalline silicon layer, one is a polycrystalline silicon layer and the other is an aluminum layer, Various combinations are also possible, such as when one or both of the layers is a polycide layer or a high melting point metal layer.

[Effects of the Invention]' As explained above, the present invention provides a fourteenth conductive layer that extends across substantially the entire width of the standard cell region, and a second conductive layer that extends in a direction perpendicular to the first conductive layer. Since the structure is such that the contact part is placed at any position where both gate conductor layers intersect, the contact part can be placed within the cell area and no special space is required for the contact. It is possible to reduce the area, improve cell integration density, and reduce the chip area.

[Brief explanation of drawings]

The figure is a plan layout diagram showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Semiconductor substrate, 2...P channel MO3) transistor row, 2A, 2B...P channel Moc; transistor, 3...N channel MOS transistor row, 3
A, 3B...N channel MO3) transistor, 4...
- Polycrystalline silicon layer, 5...aluminum layer, 6A. 6B...0MO3,? ... Input contact layer (first aluminum N), 8... Output contact layer (first aluminum layer) 10... Second aluminum layer, 11... Power contact, 12... Ground contact, 13 ...Input contact, 14...Output contact. Agent: Patent attorney Akio Suzuki.

Claims (1)

[Claims] (1) In a semiconductor integrated circuit standard cell in which a cell is constituted by a required element and a conductive layer, a first conductive layer is provided extending over substantially the entire width direction of the standard cell region, and the first conductive layer A semiconductor characterized in that an insulated and separated second conductive layer extends in a direction perpendicular to the first conductive layer, and a contact portion is provided at a position where both conductive layers intersect within the cell region. Integrated circuit standard cell. (1) The first conductive layer and the second conductive layer are aluminum layers,
The semiconductor integrated circuit standard cell according to claim 1, which is any one of a polycrystalline silicon layer, a polycide layer, and a high melting point metal layer.