JPH0369176B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a three-dimensional semiconductor device, and particularly relates to a two-dimensional semiconductor device.
The present invention relates to a semiconductor device that improves the wiring structure of a C-MOS logic circuit having an active layer of more than two layers.

[Technical background of the invention and its problems]

In semiconductor integrated circuits, the degree of integration has conventionally been improved by arranging element parts two-dimensionally and miniaturizing the element parts, but this improvement in the degree of integration is approaching its limit. Recently, techniques for forming semiconductor single crystal films on insulating films, such as laser annealing and electron beam annealing, have progressed, and three-dimensional arrangement of elements has been considered. In such a structure, a C-MOS structure is considered advantageous from the viewpoint of power consumption. In particular, P-
The method of forming a structure in which a MOS and an N-MOS are layered is advantageous in terms of process because only one type of transistor is formed in one layer.

By the way, the C-MOS structure has N channel and P channel.
Since it is necessary to have a gate connection for the transistors in the channel, one contact hole is required for this connection for each set of transistors. Also, taking a NAND gate as an example, a series-transistor and a parallel P-
A top and bottom connection always occurs at the connection of a transistor. Therefore, the NAND gate requires a total of three connection holes between the upper and lower sides. This has a great influence on the degree of integration of the tertiary elements.

FIG. 1 is a circuit configuration diagram showing a 2-input NAND gate. In the figure, 1 and 2 are P-channel MOS transistors, and 3 and 4 are N-channel MOS transistors. - transistors 3, 4 are formed in the lower layer; In such a structure, transistors 1 and 3
Three contact holes are required to connect the gates of the transistors 2 and 4, the gates of the transistors 2 and 4, and the drains of the transistors 1, 2, and 3 between the upper and lower layers. Further, in the case of a flip-flop using two NAND gates with two inputs as shown in FIG. 2, six contact holes are required for connection between the upper and lower layers. and,
Contact holes for connection between the upper and lower layers are a major factor that hinders the improvement of device integration.

[Purpose of the invention]

An object of the present invention is to provide a three-dimensional semiconductor device in which connection holes between upper and lower layers can be reduced and the degree of integration can be improved.

[Summary of the invention]

The gist of the present invention is based on the fact that when a logic circuit is constructed using a plurality of gate circuits, the N,P gate electrode pair is always connected to the previous output part, that is, the drain connection part of the N,P-transistor. Based on this, C
The purpose is to omit part of the N and P gate connections that are unique to MOS.

That is, the present invention has a two-layer structure, and one layer contains P.
A channel MOS transistor, an N channel MOS transistor is formed in another layer, and a C-MOS is formed from a plurality of the above N and P channel MOS transistors.
In a semiconductor device in which a gate circuit is configured and a logic circuit is configured using a plurality of gate circuits, a portion where a gate forming an input terminal of the gate circuit and a drain forming an output terminal of another gate circuit should be connected is Transistors of the same channel are connected to each other by planar wiring, and one of the gates of transistors of different channels forming the input terminals or the drains of transistors of different channels connected to these are connected through a contact hole between upper and lower layers. It was designed to connect.

〔Effect of the invention〕

According to the present invention, when a logic circuit is configured using a plurality of C-MOS gate circuits, the number of gate connections between the upper and lower layers of one gate circuit can be reduced. For example, when a logic circuit (such as an RS flip-flop) is configured using multiple 2-input NAND gates, there is only one connection between the upper and lower layers for each NAND gate, excluding the connection of the gate that is the input end of the logic circuit. That's enough.
Further, even when a three-input NAND gate is used, only one gate connection between the upper and lower layers is required for one NAND gate. However, if a gate is connected to each C-MOS, 3 gates will be connected with 2-input NAND,
Three-input NAND requires four interlayer connections.

For devices using thick interlayer insulating films, such as three-dimensional integrated circuits, considering that interlayer insulation increases reliability and pattern margin, reducing interlayer connections in this way will improve integration. It is extremely effective in improving the degree of

[Embodiments of the invention]

FIG. 3 is a schematic diagram showing the three-dimensional configuration of a semiconductor device according to an embodiment of the present invention, and FIG. 4 is a circuit diagram of the device. This device has two inputs.
This is a flip-flop using two NAND gates, with a P-channel MOS transistor formed in the upper layer and an N-channel MOS transistor formed in the lower layer. In the figure, 10 and 20 are P-channel MOS transistors, and 30 and 40 are N-channel MOS transistors.
A NAND gate (first gate circuit) with 0 to 2 inputs is configured. Further, 50 and 60 are P-channel MOS transistors, and 70 and 80 are N-channel MOS transistors, and these transistors 50 to 80 constitute a two-input NAND gate (second gate circuit).

Here, regarding the first gate circuit, the portions that require connection between the upper and lower layers are the transistors 10 and 3.
Between each gate 11 and 31 of 0, the transistor 20,
40 between each gate 21 and 41 and transistor 1
These are the three locations between the drains 12, 22, and 32 of 0, 20, and 30, respectively. The gates 11 and 31 and the drains 12, 22 and 32 are connected through contact holes as in the conventional case. On the other hand, gates 21 and 41 are not directly connected, and P-
The gate 21 of the transistor 20 is connected in a plane to the commonly connected drains 52, 62 of the P-transistors 50, 60 forming the second gate circuit, and the gate 41 of the N-transistor 40 forms the second gate circuit. It is connected in a plane to the drain 72 of the N-transistor 70 that constitutes it. here,
The above-mentioned planar connection means connection using the same plane wiring layer. The gates 21 and 41 are the second gates.
The transistors 50, 60, in the gate circuit of
The drains 52, 62, and 72 of 70 are indirectly connected by the upper and lower interlayer connections.

On the other hand, regarding the second gate circuit, between the gates 51 and 81 of the transistors 50 and 80 and between the drains 52 and 6 of the transistors 50, 60 and 70,
2 and 72 are connected by a contact hole between the upper and lower layers as in the conventional case. On the other hand, the gates 61 and 71 of the transistors 60 and 70 are not directly connected, and the gate 61 is connected to the P-transistors 10 and 2 that constitute the first gate circuit.
The gate 71 is connected in a planar manner to the commonly connected drains 12 and 22 of the N-transistor 30 forming the first gate circuit. Here, since the drains 12, 22, and 32 are connected through contact holes between the upper and lower layers, the gates 61, 7
1 will be indirectly connected.

Note that 13 and 23 in FIG. 3 are the sources of the P-transistors 10 and 20, which are commonly connected to the Vdd terminal by a planar wiring (for example, a diffusion layer). 33 is the source of the N-transistor 30, 42
is the drain of the N-transistor 40, and these are also commonly connected by a planar wiring. 43 is N-
This is the source of the transistor 40, and is similarly connected to the ground terminal by a planar wiring. Also, 53,6
Reference numeral 3 indicates the sources of P-transistors 50 and 60, which are commonly connected to the Vdd terminal by planar wiring. 73 is the source of the N-transistor 70;
82 is the drain of the N-transistor 80;
These are commonly connected by planar wiring. 83 is the source of the N-transistor 80, which is similarly connected to the ground terminal by a planar wiring.

With such a configuration, each gate 21 of the transistors 20 and 40 in the first gate circuit
There is no need for a contact hole between the upper and lower layers for the connection of the transistors 41, and furthermore, there is no need for a contact hole between the upper and lower layers for the connection between the gates 61 and 71 of the transistors 60 and 70 in the second gate circuit. Therefore, it is extremely effective in improving the degree of integration. Here, regarding the first gate circuit, instead of requiring a contact hole for connection between the gates 21 and 41, the connection between the gate 21 and the drain of the transistor 60, or the connection between the gate 41 and the gate 41 is eliminated.
1 and the source 72 of the N-transistor 70 is required. However, since elements are usually located close to each other, wiring with gate polysilicon, and in the case of tertiary elements, routing wiring layers within the same layer does not pose much of an obstacle in terms of area. Therefore,
The ability to use a plane wiring layer instead of the connection between the upper and lower layers is extremely effective for integrating tertiary elements. Further, this effect is the same for the second gate circuit.

Note that the present invention is not limited to the embodiments described above. For example, the gate circuit has two inputs.
Not limited to NAND gates, but 3-input
Any gate circuit using NAND or other C-MOS transistors may be used. Further, the logic circuit is not limited to a flip-flop, but may be any logic circuit configured by connecting the input end of a gate circuit to the input end of another gate circuit. Further, contrary to the embodiment, an N-channel MOS transistor may be formed in the upper layer and a P-channel MOS transistor may be formed in the lower layer. In addition, various modifications can be made without departing from the gist of the present invention.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing a two-input NAND gate, FIG. 2 is a circuit configuration diagram showing a flip-flop using two of the above NAND gates, and FIG. 3 is a three-dimensional diagram of a semiconductor device according to an embodiment of the present invention. FIG. 4 is a schematic diagram showing the general configuration of the device. 10, 20, 50, 60...P channel MOS
Transistor, 30, 40, 70, 80...N channel MOS transistor, 11, 21, 31,
41, 51, 61, 71, 81...gate, 1
2, 22, 32, 42, 52, 62, 72, 82
...Drain, 13, 23, 33, 43, 53,
63, 73, 83... sauce.

Claims (1)

[Claims] 1. Has a two-layer structure, with a P channel in one layer.
MOS transistor, an N channel MOS transistor is formed in another layer, and the above N and P channel
In a semiconductor device in which a C-MOS gate circuit is constructed from a plurality of MOS transistors and a logic circuit is constructed using a plurality of these gate circuits, a gate forming an input terminal of the gate circuit and an output terminal of another gate circuit are connected to each other. The parts to be connected to the drains of the transistors of the same channel are connected to each other by planar wiring, and the gates of the transistors of different channels forming the input terminals, or the drains of transistors of different channels connected to these are connected to each other by plane wiring. A semiconductor device characterized in that the upper and lower layers are connected through a contact hole between upper and lower layers. 2. The semiconductor device according to claim 1, wherein the gate circuit is a two-input NAND gate, and the logic circuit is a flip-flop using two of the NAND gates.