JPH06283604A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06283604A JPH06283604A JP5090544A JP9054493A JPH06283604A JP H06283604 A JPH06283604 A JP H06283604A JP 5090544 A JP5090544 A JP 5090544A JP 9054493 A JP9054493 A JP 9054493A JP H06283604 A JPH06283604 A JP H06283604A
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- semiconductor device
- bonding
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、半導体装置に関し、
特にゲートアレイ等のマスタースライス型半導体装置に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, it relates to a master slice type semiconductor device such as a gate array.
【０００２】[0002]
【従来の技術】一般に、ゲートアレイは、通常半導体チ
ップ上に基本セルを規則正しく配列し、その周辺部に入
出力セルを配置して構成されている。そしてチップ周辺
部に配置されている入出力セルは、ボンディングパッド
を備えており、メタル配線によって電源パッドや入力パ
ッド，出力パッド等の機能を設定できるようになってい
る。この入出力セルを構成する各素子のレイアウトは様
々であるが、ボンディングパッドは一般にチップ端の近
傍に配置されている。（富沢孝 外一名 監訳「ＣＭＯ
ＳＶＬＳＩ設計の原理」、昭和62年８月30日丸善株式会
社発行、第193 〜199 頁参照）2. Description of the Related Art Generally, a gate array is generally constructed by regularly arranging basic cells on a semiconductor chip and arranging input / output cells in the peripheral portion thereof. The input / output cells arranged in the peripheral portion of the chip are provided with bonding pads, and the functions of the power supply pad, the input pad, the output pad, etc. can be set by metal wiring. Although the layout of each element constituting the input / output cell is various, the bonding pad is generally arranged near the chip end. (Translated by Takato Tomizawa, "CMO"
Principles of SVLSI Design, "Maruzen Co., Ltd., August 30, 1987, pp. 193-199)
【０００３】[0003]
【発明が解決しようとする課題】ところで、最近のゲー
トアレイは、機能の向上と共に多ピン化の傾向にあり、
チップの周辺部には入出力セルをより多く配置させるた
め、該入出力セルに設けられるボンディングパッドのピ
ッチが小さくなりつつある。したがって、入出力パッド
等のボンディングパッドの狭ピッチ化に伴い、ワイヤー
ボンディング時のワイヤー間隔も狭くなり、隣接するワ
イヤーによる短絡の危険性が増大している。By the way, recent gate arrays tend to have a large number of pins as the functions are improved.
Since more input / output cells are arranged in the peripheral portion of the chip, the pitch of bonding pads provided in the input / output cells is becoming smaller. Therefore, as the pitch of the bonding pads such as the input / output pads becomes narrower, the wire interval at the time of wire bonding also becomes narrower, and the risk of short circuit due to adjacent wires increases.
【０００４】図４は、半導体チップのコーナー付近のワ
イヤーボンディングの状態を示す図であり、101 は半導
体チップ、102 は入出力セル、103 は入出力セル102 に
設けたボンディングパッド、104 は外部回路のリード、
105 はボンディングパッド103 とリード104 とを接続す
るボンディングワイヤーである。この図から分かるよう
に、特に半導体チップのコーナー付近では、ボンディン
グワイヤーの間隔が一段と狭くなっている。FIG. 4 is a diagram showing a state of wire bonding in the vicinity of a corner of a semiconductor chip. 101 is a semiconductor chip, 102 is an input / output cell, 103 is a bonding pad provided on the input / output cell 102, and 104 is an external circuit. The lead of
A bonding wire 105 connects the bonding pad 103 and the lead 104. As can be seen from this figure, the spacing between the bonding wires is further narrowed, especially near the corners of the semiconductor chip.
【０００５】本発明は、従来のゲートアレイ等の半導体
装置における上記問題点を解消するためになされたもの
で、チップ上に配列される入出力セルのピッチを拡げる
ことなく、ワイヤーボンディング時のワイヤー間スペー
スを十分確保し、ワイヤー同志による短絡を避けること
ができるようにした半導体装置を提供することを目的と
する。The present invention has been made in order to solve the above-mentioned problems in the conventional semiconductor device such as a gate array, and the wire at the time of wire bonding without expanding the pitch of the input / output cells arranged on the chip. It is an object of the present invention to provide a semiconductor device in which a sufficient space can be secured and a short circuit caused by wires can be avoided.
【０００６】[0006]
【課題を解決するための手段及び作用】上記問題点を解
決するため、本発明は、内部セル領域を備えた半導体チ
ップ上の周辺部に入出力セルを配置した半導体装置にお
いて、上記入出力セル内に配置されるボンディングパッ
ドを前記半導体チップの周辺縁より離れた内部セル領域
に近い位置に配置して構成するものである。In order to solve the above problems, the present invention provides a semiconductor device in which input / output cells are arranged in the peripheral portion on a semiconductor chip having an internal cell region. The bonding pad arranged inside is arranged at a position close to the internal cell region apart from the peripheral edge of the semiconductor chip.
【０００７】このように入出力セルのボンディングパッ
ドを内部セル領域に近い位置に配置することにより、特
に半導体チップのコーナー部では、ボンディングワイヤ
ー間隔が広がり、ボンディングワイヤー間での短絡の危
険性を抑えることが可能となる。By arranging the bonding pads of the input / output cells in the positions close to the internal cell region in this way, especially at the corners of the semiconductor chip, the spacing between the bonding wires is widened and the risk of short circuit between the bonding wires is suppressed. It becomes possible.
【０００８】[0008]
【実施例】次に実施例について説明する。図１は、本発
明の基本的な実施例を示す概念図である。図１におい
て、１は半導体チップ、２は内部セル領域、３は半導体
チップ１の周辺部に多数配置された入出力セル、４は入
出力セル３に設けられたボンディングパッドで、半導体
チップ１の周辺縁より離れた内部セル領域２に近い位置
に配置されている。５は外部回路のリード、６はリード
５とボンディングパッド４とを接続するボンディングワ
イヤーである。EXAMPLES Next, examples will be described. FIG. 1 is a conceptual diagram showing a basic embodiment of the present invention. In FIG. 1, 1 is a semiconductor chip, 2 is an internal cell region, 3 is an input / output cell arranged in the peripheral portion of the semiconductor chip 1, and 4 is a bonding pad provided on the input / output cell 3. It is arranged at a position close to the inner cell region 2 apart from the peripheral edge. Reference numeral 5 is a lead of an external circuit, and 6 is a bonding wire connecting the lead 5 and the bonding pad 4.
【０００９】このように、入出力セル３のボンディング
パッド４を内部セル領域側へ配置することにより、特に
半導体チップ１のコーナー部では、入出力セル３のピッ
チを拡げなくても、ボンディングワイヤー６の間隔が広
がり、ワイヤー同志による短絡を有効に阻止することが
できる。By arranging the bonding pads 4 of the input / output cells 3 on the inner cell region side in this manner, the bonding wires 6 can be formed at the corners of the semiconductor chip 1 without expanding the pitch of the input / output cells 3. The distance between the two can be expanded, and a short circuit due to the wires can be effectively prevented.
【００１０】次に、本発明の具体的な実施例を図２に基
づいて説明する。この実施例は、入出力セルのボンディ
ングパッドを電源パッドとして使用するように構成した
ものである。図２において、11は入出力セル、12はボン
ディングパッド、13は入出力バッファ用電源線、14は入
出力バッファ用接地線、15は内部セル用電源線、16は内
部セル用接地線である。ボンディングパッド12からチッ
プ端方向及びチップ内部方向の相反する方向に延伸形成
した２系統のメタル配線17，18で、入出力バッファ用電
源線13と内部セル用電源線15とがボンディングパッド12
に接続されている。入出力セル11内には入力バッファや
出力バッファ等のセル素子が予め第１層目のメタル層で
配置されている。ところが、この実施例ではボンディン
グパッドを電源用パッドとして使用しているので、上記
入出力バッファ等は接続する必要がない。そのため上記
電源線13，15、接地線14，16及びメタル配線17，18は第
２層目のメタル層で構成されている。Next, a concrete embodiment of the present invention will be described with reference to FIG. In this embodiment, the bonding pads of the input / output cells are used as power supply pads. In FIG. 2, 11 is an input / output cell, 12 is a bonding pad, 13 is an input / output buffer power supply line, 14 is an input / output buffer ground line, 15 is an internal cell power supply line, and 16 is an internal cell ground line. . Two lines of metal wirings 17 and 18 are formed extending from the bonding pad 12 in opposite directions of the chip end direction and the chip inner direction, and the input / output buffer power supply line 13 and the internal cell power supply line 15 form the bonding pad 12
It is connected to the. In the input / output cell 11, cell elements such as an input buffer and an output buffer are arranged in advance in the first metal layer. However, since the bonding pad is used as a power supply pad in this embodiment, it is not necessary to connect the input / output buffer and the like. Therefore, the power supply lines 13 and 15, the ground lines 14 and 16 and the metal wirings 17 and 18 are composed of the second metal layer.
【００１１】一般に、入出力セルにおける出力バッファ
を同時に駆動すると、同時スイッチングノイズやリンギ
ングノイズが発生する。この時、入出力バッファの電源
線や接地線が不安定になることがあり、内部セルの誤動
作を起こしかねない。これに対して、上記実施例におい
ては、入出力バッファ用電源線13と内部セル用電源線15
の間にボンディングパッド12を設けて、相反する方向に
延伸した２系統の第２層目のメタル配線17，18で接続し
ているので、それぞれの電源線13，15のインダクタンス
は別系統になり、分離することができる。その結果、入
出力バッファ用電源線13で発生したノイズの影響を、内
部セル用電源線15では最小限に抑えることができる。Generally, when the output buffers in the input / output cells are driven simultaneously, simultaneous switching noise and ringing noise occur. At this time, the power supply line and the ground line of the input / output buffer may become unstable, which may cause malfunction of the internal cells. On the other hand, in the above embodiment, the input / output buffer power line 13 and the internal cell power line 15
Since the bonding pad 12 is provided between the two lines and the two lines are connected by the second-layer metal wirings 17 and 18 of the two systems, the inductances of the respective power supply lines 13 and 15 are different systems. , Can be separated. As a result, the influence of noise generated in the input / output buffer power supply line 13 can be minimized in the internal cell power supply line 15.
【００１２】なお、上記実施例では、入出力セルのボン
ディングパッドを電源パッドとして用いた場合を示した
が、このボンディングパッドを接地線パッドとして用い
ることもでき、同様な作用効果が得られる。In the above embodiment, the bonding pad of the input / output cell is used as the power supply pad, but this bonding pad can be used as the ground line pad, and the same effect can be obtained.
【００１３】また上記実施例では、入力バッファや出力
バッファが第１層目のメタル層で配置されているため、
電源線を第２層目のメタル層で配線しているものを示し
たが、前記バッファ類に影響がなければ、電源線を第１
層目のメタル層で構成しても何ら問題ない。Further, in the above embodiment, since the input buffer and the output buffer are arranged in the first metal layer,
The power supply line is shown as being wired in the second metal layer, but if the buffers are not affected, the power supply line should be the first
There is no problem even if it is composed of the metal layer of the second layer.
【００１４】次に、本発明の具体的な他の実施例を図３
を用いて説明する。この実施例は、入出力セルのボンデ
ィングパッドを出力パッドとして使用するように構成し
たものである。図３は、出力バッファ部分を示す断面図
で、21はＮチャネルＭＯＳトランジスタ、22はＰチャネ
ルＭＯＳトランジスタ、23は第１層目メタル配線、24は
第１層間膜、25は第２層目メタル配線、26は第２層間
膜、27は第３層目メタル配線、28はパッシベーション
膜、29はボンディングパッドである。Next, another specific embodiment of the present invention will be described with reference to FIG.
Will be explained. In this embodiment, the bonding pad of the input / output cell is used as the output pad. FIG. 3 is a cross-sectional view showing an output buffer portion. 21 is an N-channel MOS transistor, 22 is a P-channel MOS transistor, 23 is a first layer metal wiring, 24 is a first interlayer film, and 25 is a second layer metal. Wiring, 26 is a second interlayer film, 27 is a third layer metal wiring, 28 is a passivation film, and 29 is a bonding pad.
【００１５】最近のゲートアレイは、２層又は３層のメ
タル配線を使用しているものが主流となっている。第２
層目のメタル配線でボンディングパッドを形成した場
合、その直下に入出力セルの素子を配置するのはレイア
ウト的に難しく、またAlメタル配線のつき抜けによる素
子破壊や短絡，断線の危険を伴う。これに対して本実施
例では、ボンディングパッド29を第３層目メタル配線27
で構成しているので、パッド直下に素子を配置したとし
ても、層間膜が厚いので、Alメタルのつき抜けは避けら
れ、入出力セルの一層のコンパクト化が可能となる。ま
た第３層目メタル配線を用いることによりレイアウト的
に自由度が増す。Most recent gate arrays mainly use two-layer or three-layer metal wiring. Second
When the bonding pad is formed by the metal wiring of the layer, it is difficult to arrange the element of the input / output cell directly under the bonding pad, and there is a risk of element destruction, short circuit, or disconnection due to sticking out of the Al metal wiring. On the other hand, in this embodiment, the bonding pad 29 is connected to the third-layer metal wiring 27.
Even if the element is arranged immediately below the pad, since the interlayer film is thick, the Al metal can be prevented from sticking through, and the input / output cell can be made more compact. In addition, the use of the third layer metal wiring increases the degree of freedom in layout.
【００１６】上記実施例は、ボンディングパッドを出力
パッドとして用いるように構成したものを示したが、ボ
ンディングパッドを入力パッドとして用いた場合でも、
同様にパッド直下に素子を配置することができる等の利
点が得られるのは言うまでもない。Although the above embodiment shows the structure in which the bonding pad is used as the output pad, even when the bonding pad is used as the input pad,
It goes without saying that similar advantages can be obtained such that elements can be arranged directly below the pads.
【００１７】[0017]
【発明の効果】以上実施例に基づいて説明したように、
本発明によれば、入出力セルのボンディングパッドを内
部セル領域側に配置したので、ワイヤーボンディング時
のボンディングワイヤー間隔を十分確保してワイヤーに
よる短絡を阻止することができる。As described above on the basis of the embodiments,
According to the present invention, since the bonding pads of the input / output cells are arranged on the internal cell region side, it is possible to secure a sufficient bonding wire interval during wire bonding and prevent a short circuit due to the wires.
【図１】本発明に係る半導体装置の基本的な実施例を示
す概念図である。FIG. 1 is a conceptual diagram showing a basic embodiment of a semiconductor device according to the present invention.
【図２】本発明の具体的な実施例を示す平面図である。FIG. 2 is a plan view showing a specific embodiment of the present invention.
【図３】本発明の他の具体的な実施例を示す断面図であ
る。FIG. 3 is a cross-sectional view showing another specific embodiment of the present invention.
【図４】従来の半導体装置の構成例を示す図である。FIG. 4 is a diagram showing a configuration example of a conventional semiconductor device.
１ 半導体チップ ２ 内部セル領域 ３ 入出力セル ４ ボンディングパッド ５ リード ６ ボンディングワイヤー 1 semiconductor chip 2 internal cell region 3 input / output cell 4 bonding pad 5 lead 6 bonding wire
Claims (3)
周辺部に入出力セルを配置した半導体装置において、上
記入出力セル内に配置されるボンディングパッドを前記
半導体チップの周辺縁より離れた内部セル領域に近い位
置に配置したことを特徴とする半導体装置。1. A semiconductor device in which an input / output cell is arranged in a peripheral portion of a semiconductor chip having an internal cell region, wherein a bonding pad arranged in the input / output cell is separated from a peripheral edge of the semiconductor chip. A semiconductor device characterized in that the semiconductor device is arranged at a position close to a cell region.
グパッドから、半導体チップ端方向と半導体チップ内部
方向にそれぞれメタル配線を形成し、チップ端方向のメ
タル配線は入出力バッファ用の電源線又は接地線に接続
し、チップ内部方向のメタル配線は内部セル領域の電源
線又は接地線に接続し、前記ボンディングパッドを電源
線用パッド又は接地線用パッドとしたことを特徴とする
請求項１記載の半導体装置。2. Metal wires are respectively formed in the semiconductor chip end direction and the semiconductor chip inner direction from the bonding pads arranged in the input / output cells, and the metal wires in the chip end direction are the power supply line or ground for the input / output buffer. 2. The wiring according to claim 1, wherein the metal wiring inward of the chip is connected to a power supply line or a ground line in the internal cell region, and the bonding pad is a power supply line pad or a ground line pad. Semiconductor device.
上のメタル配線で構成し、入出力セルの素子の真上に配
置されていることを特徴とする請求項１又は２記載の半
導体装置。3. The semiconductor device according to claim 1, wherein the bonding pad is composed of a metal wiring of a third layer or more and is arranged right above the element of the input / output cell.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5090544A JPH06283604A (en) | 1993-03-26 | 1993-03-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5090544A JPH06283604A (en) | 1993-03-26 | 1993-03-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06283604A true JPH06283604A (en) | 1994-10-07 |
Family
ID=14001365
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5090544A Withdrawn JPH06283604A (en) | 1993-03-26 | 1993-03-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06283604A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001339047A (en) * | 2000-05-29 | 2001-12-07 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JP2002299567A (en) * | 2001-04-02 | 2002-10-11 | Sony Corp | Semiconductor element |
| US6930380B2 (en) | 2003-06-06 | 2005-08-16 | Renesas Technology Corp. | Semiconductor device |
| US8178981B2 (en) | 2004-02-26 | 2012-05-15 | Renesas Electronics Corporation | Semiconductor device |
| JP2016021522A (en) * | 2014-07-15 | 2016-02-04 | ラピスセミコンダクタ株式会社 | Semiconductor device |
| JP2016111154A (en) * | 2014-12-04 | 2016-06-20 | ルネサスエレクトロニクス株式会社 | Semiconductor device and method of manufacturing the same |
-
1993
- 1993-03-26 JP JP5090544A patent/JPH06283604A/en not_active Withdrawn
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001339047A (en) * | 2000-05-29 | 2001-12-07 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JP2002299567A (en) * | 2001-04-02 | 2002-10-11 | Sony Corp | Semiconductor element |
| US6930380B2 (en) | 2003-06-06 | 2005-08-16 | Renesas Technology Corp. | Semiconductor device |
| US7078824B2 (en) | 2003-06-06 | 2006-07-18 | Renesas Technology Corp. | Semiconductor device having a switch circuit |
| US8178981B2 (en) | 2004-02-26 | 2012-05-15 | Renesas Electronics Corporation | Semiconductor device |
| JP2016021522A (en) * | 2014-07-15 | 2016-02-04 | ラピスセミコンダクタ株式会社 | Semiconductor device |
| JP2016111154A (en) * | 2014-12-04 | 2016-06-20 | ルネサスエレクトロニクス株式会社 | Semiconductor device and method of manufacturing the same |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20000530 |