JPH09148545A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the I/O region area in a multipin gate array(G/A) of a semiconductor integrated circuit. SOLUTION: This device comprises the following in an I/O cell 102 region of a gate array; pads 101, an I/O cell 102, aluminum wirings 103 for connecting the pads 101 with the I/O cell 102, and power supply wirings 104-107 wired on the I/O cell 102. An aluminum layer constituting the aluminum wirings 103 is different from an aluminum layer constituting the power supply wirings 104-107. The aluminum wirings 103 intersect the power supply wirings 104-107 and connect the pads 101 with the I/O cell 102. Thereby the spaces of the pads 101 and the I/O cell 102 can be minimized, so that the area of the I/O cell 102 region can be reduced. Further the chip size is made small and the chip cost can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-pin gate array for a semiconductor integrated circuit.

[0002]

2. Description of the Related Art A conventional multi-pin gate array (G / A) has a pad 201 provided for connection with the outside of the IC and an outside of the IC as shown in the block diagram of the I / O region of FIG. The input cell that receives a signal from the IC and the I / O cell 202 that constitutes an output cell that propagates the signal to the outside of the IC are separated, and the pad 201 is connected by the aluminum wiring 203 for I / O connection.
And the I / O cell 202 is connected to form an I / O area.

At this time, power supply wirings 204, 205, 206, 2 provided to supply power to the I / O cell 202.
07 and the I / O connecting aluminum wiring 203 were formed of the same aluminum wiring layer.

[0004]

However, in the above-mentioned prior art, since the power supply wiring and the I / O connecting aluminum wiring are formed in the same aluminum wiring layer, the I / O cell and the I / O connecting aluminum wiring are formed. The connection portion of the wiring is limited to the outer peripheral side of the chip of the I / O cell, and there is a problem that the area of the aluminum wiring region for I / O connection increases, that is, the increase of the chip area leads to an increase of the chip cost. .

Therefore, the present invention solves such a problem, and an object of the present invention is to provide a multi-pin G / A having a small I / O area.

[0006]

According to the present invention, there is provided a semiconductor device comprising:
In the I / O cell area of the gate array, the pad and the I
/ O cell, an aluminum wiring connecting the pad and the I / O cell, and a power wiring wired on the I / O cell. The aluminum layer forming the aluminum wiring and the power wiring are connected to each other. It is characterized by different aluminum layers.

Further, the aluminum wiring intersects the power supply wiring to connect the pad and the I / O cell.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a first embodiment of the present invention.
A configuration diagram of the I / O area of the multi-pin G / A is shown in FIG.

In FIG. 1, a pad 101 for connecting to the outside of the IC is provided on the outermost peripheral portion of the IC. At this time, in order to provide a larger number of pads even with the same chip size, the pad 1 is also provided in the chip corner space.
01 is installed.

An input cell that is customized using the first layer aluminum and the second layer aluminum and propagates a signal from the outside of the IC to the inside of the IC, an output cell that propagates a signal from the inside of the IC to the outside of the IC, A bidirectional cell that also serves as an input cell and an output cell, and a power supply cell
The / O cells 102 are arrayed inside the pad 101.

In addition, the internal cell region 108 in which the basic cells are arranged in an array to form a logic circuit is the I / O cell 10.
It is located inside 2.

On the I / O cell 102, first potential power supply (VDD) wirings 104 and 106 and ground potential power supply (VSS) wirings 105 and 107 are laid using the second layer aluminum. , Pch transistors and Nch transistors in the I / O cell 102 are supplied with potentials.

The pad 101 and the I / O cell 102 are also provided.
The aluminum wiring 103 for I / O connection for connecting to is composed of a third layer of aluminum.

Here, each pad 101 and each I / O cell 1
I / O because the arrangement relationship of 02 is different for each combination
Although the wiring area of the connecting aluminum wiring 103 increases as the number of pins increases, the aluminum wiring layers of the VDD wirings 104 and 106 and the VSS wirings 105 and 107 are
Since the aluminum wiring layer of the O wiring aluminum wiring 103 is different,
The I / O connection aluminum wiring 103 is a VDD wiring 104,
106 and the VSS wirings 105 and 107 can be crossed and wired. Therefore, the I / O cell 103 can be arranged with a minimum space between the pad 101 and the pad 101, and the pad 101 and the I / O cell 102 can be arranged.
Is connected between the VDD wiring 104 and the VSS wiring 105.

As described above, the area of the I / O region can be minimized even in the case of the G / A having a large number of pins.

Further, although three-layer aluminum wiring is used in FIG. 1, this also applies to G / A having four-layer aluminum wiring or more.

In FIG. 1, one VDD power source is used, but this also applies to a G / A that supplies two or more power sources.

Further, in FIG. 1, the pad 101 and I /
Although the O cell 102 is connected between the VDD wiring 104 and the VSS wiring 105, this also applies to the connection between all the power supply wirings.

In FIG. 1, the pad 101 and I /
All the connections of the O cell 102 are made between the same power supply lines, but this also applies to the case where the connection location is changed for each pad.

[0020]

As described above, according to the present invention, the area of the I / O region can be minimized in the multi-pin compatible G / A. This also has the effect of reducing the chip size and the chip cost.

[Brief description of the drawings]

FIG. 1 is a multi-pin G / A I showing a first embodiment of the present invention.
FIG.

FIG. 2 is a configuration diagram of an I / O area of a multi-pin G / A showing a conventional example.

[Explanation of symbols]

101, 201 Pads 102, 202 I / O cells 103, 203 I / O connection aluminum wirings 104, 105, 106, 107, 204, 205, 2
06, 207 Power wiring 108 Internal cell area

Claims (2)

[Claims] 1. An I / O cell region of a gate array,
An aluminum layer, which comprises a pad, an I / O cell, an aluminum wire connecting the pad and the I / O cell, and a power wire wired on the I / O cell, and which constitutes the aluminum wire; A semiconductor device, wherein the aluminum layers forming the power supply wiring are different. 2. The semiconductor device according to claim 1, wherein the aluminum wiring intersects with the power supply wiring to connect the pad and the I / O cell.