JPH01168042A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To eliminate a reduction in buffer cells by disposing more pads than the number of the cells by decreasing the disposing pitch of the pads smaller than that of buffer cell rows, and using excess pads except the pads corresponding to the respective cells for a power supply or a ground. CONSTITUTION:The disposing pitch of pads in a semiconductor chip 101 is reduced smaller than that of buffers, thereby forming excess pads 10a1, 10a2, 10b not corresponding by 1:1 thereby in addition to the pads 10 corresponding by 1:1 to the buffers 7. A power source line is provided by a second layer aluminum 11a through an insulating layer on the row of the buffer cells 7, and the buffers 7 are connected to the pads 10 through aluminum wirings 11. The excess pads 10a1 are connected through second layer aluminum wirings 11a directly to a GND line 9, and the excess pads 10a2 are connected through first layer aluminum wirings 11b and second layer aluminum wirings 11c connected by a contact 12 to a VCC line 8. Thus, the pads 10a1, 10a2 are connected directly to the power source line thereby to increase the number of the pads for the power supply or the ground.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to semiconductor integrated circuit devices, and particularly semiconductor integrated circuit devices that require a large number of power supply pads or grounding pads, particularly semi-custom LSIs, that is, gate array type devices. The present invention relates to an integrated circuit device.

[Conventional technology]

In the gate array method, internal cells and buffer cells with active or passive elements are formed on a semiconductor substrate after completing a diffusion process in advance, and then realized. Only the wiring is designed and completed according to the performance.

FIG. 2 shows an example of a gate array type LSI.

In FIG. 2, an internal cell region 2 is arranged in the center of a semiconductor chip 1, and a plurality of input/output buffer cells 3 are arranged around it. A power supply fin 4 and a power supply fin 5 are provided above these buffer cell rows. A plurality of pads 6 are arranged in parallel with the buffer cell row, and adjacent buffer cells 3 and pads 6 are closely read.

[Problem that the invention seeks to solve]

In recent years, with regard to input/output interfaces, there has been a demand for improvement in the output driving ability of input/output buffer cells. The maximum drive capability of an input/output buffer cell depends on the number of transistors arranged within the buffer cell. In other words, if the drive capacity is designed to be large, the number of transistors arranged in the buffer cell will increase, and the input/output buffer cell itself will inevitably become larger. However, when each buffer cell 3 is arranged in one-to-one correspondence with the pad 6 as shown in the diagram, in order to ensure that the arrangement pitch of the buffer cells 3 and the arrangement pitch of the pads 6 are the same, it is necessary to The distance m is influenced by the pitch of the buffer cells 3 and becomes larger than the distance determined by the restrictions imposed upon wire bonding. Further, as the driving capacity increases, it becomes necessary to use a large number of pads as power supply pads or grounding pads. For this reason, the number of power supply buffers or grounding buffers corresponding to the power supply pads or grounding pads increases, reducing the number of buffers that can be used as input/output buffers, and forcing a decline in the functionality of the semiconductor integrated circuit device. There was a problem.

[Means for Solving the Problems] In order to solve the conventional problems, the present invention provides an internal cell area in the center of a semiconductor chip, arranges an input/output buffer cell array around the internal cell area, In a semiconductor integrated circuit device having a structure in which a pad row is arranged parallel to the buffer cell row, the pad arrangement pitch is made smaller than the arrangement pitch of the buffer cell row, and more pads than the number of buffer cells are arranged. A semiconductor integrated circuit is constructed by using the surplus pads other than the pads corresponding to the buffer cells for power supply or grounding.

[Action of the invention]

According to the present invention, the extra pads that do not have a one-to-one correspondence between buffer cells and pads are used for power supply or grounding, and the buffer cells for power supply or grounding are not used. Even if the number of supply or grounding pads increases, the number of buffer cells used for input/output does not decrease.

〔Example〕

An embodiment of the present invention is shown in FIGS. 1(a) and 1(b). 1st
FIG. 1(a) shows a side portion of the chip, and FIG. 1(b) shows a corner portion of the chip.

In the semiconductor chip IO1, a buffer cell is arranged around the internal cell region 102, and pads lo, 10a, s 10az are arranged in parallel with the buffer cell/L/7 column.

10b is arranged.

Here, by making the arrangement pitch of the pads smaller than the arrangement pitch of the buffers, in addition to the pads 10 that correspond one-to-one to the buffer 7, it is possible to form surplus pads 1oale 10a2*10b that do not correspond one-to-one. . Power supply fins (VCC fins 8 and GND fins 9
) is set, /(Tuff 7 and pad 10 are Al wiring 1
1. In the figure, extra pad 1
0a1 is directly connected to the GND fin 9 through the second layer kl wiring 11af, and the redundant pad 10a2 is connected to the first layer Al? through the contact 12. It is connected to the vCC fin 8 via the wiring 11b and the second layer A4 wiring 11c. As above, surplus pad 10 al 110a
2 can be directly connected to the power supply fin, thereby increasing the number of power supply pads or grounding pads.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to increase the number of power supply pads or grounding pads without increasing the chip area or reducing the functionality of the semiconductor circuit device.

[Brief explanation of the drawing]

Figure 1 ≠ Spring ÷ Vio shows the main part of an embodiment of the present invention! The plan view shown in FIG. 1 is a plan view showing the shape of a conventional gate array LSI. 7... Buffer cell, 8... vCC fin, 9
...GND fin, 10...pad, 10 a
1 el 0 a 2 * 10 b... Surplus bad, 11 - AI wiring, lla... Second layer Al wiring, llb... Third layer AI wiring, 11
c...Second layer Al wiring, 12...-th layer AA',!
: Contact with second layer, 101... semiconductor chip,
102... Internal cell area.

Claims (1)

[Claims] 1. A gate array type in which an internal cell region is provided in the center of a semiconductor chip, a buffer cell row is arranged around the internal cell region, and a pad row is arranged parallel to the buffer cell row. In a semiconductor integrated circuit device, the arrangement pitch of the pads is made smaller than the arrangement pitch of the buffer cell rows to provide more pads than the number of buffer cells, and the surplus pads are connected to power supply fins or grounding fins. Semiconductor integrated circuit device.