JPH0542823B2 - - Google Patents
Info
- Publication number
- JPH0542823B2 JPH0542823B2 JP17859183A JP17859183A JPH0542823B2 JP H0542823 B2 JPH0542823 B2 JP H0542823B2 JP 17859183 A JP17859183 A JP 17859183A JP 17859183 A JP17859183 A JP 17859183A JP H0542823 B2 JPH0542823 B2 JP H0542823B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- output circuit
- circuit area
- area
- type semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 description 6
- 238000003491 array Methods 0.000 description 5
- 238000006073 displacement reaction Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11898—Input and output buffer/driver structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、マスタ・スライス型半導体装置に係
わり、得に入出力回路領域の改良をはかつたマス
タ・スライス型半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a master slice type semiconductor device, and more particularly to a master slice type semiconductor device with an improved input/output circuit area.
マスタ・スライス型半導体装置は、予め複数の
素子からなる基本セルを半導体基板上に多数作り
込んでおき配線層並びに接続孔を変更することに
より所望の回路動作を得ようとするもので、新た
な機能の回路の要望に対して比較的簡単に対処で
きる特徴を有している。即ち、金属配線を形成す
る以前の工程により作成される半導体チツプは全
て機能回路に共通であるため、上記方式を採用す
ると、開発期間の短縮及び製造コストの低減がは
かれ、多品種小量生産が可能となる。
A master slice type semiconductor device is a device in which a large number of basic cells consisting of multiple elements are fabricated in advance on a semiconductor substrate, and the desired circuit operation is obtained by changing the wiring layers and connection holes. It has the feature that it can relatively easily meet the demands of functional circuits. In other words, since all semiconductor chips created through processes before forming metal wiring have a common functional circuit, adopting the above method shortens the development period and reduces manufacturing costs, allowing for high-mix, low-volume production. becomes possible.
マスタ・スライス型半導体装置の一つとして、
ゲート・アレイの例を第１図に示す。この半導体
装置は半導体チツプ１上が基本素子領域２とその
周辺の入出力回路領域３とに分けられている。入
出力回路領域中３には、複数の入出力端子（ボン
デイング・パツド）４が設置される。 As one of the master slice type semiconductor devices,
An example of a gate array is shown in FIG. In this semiconductor device, a semiconductor chip 1 is divided into a basic element area 2 and an input/output circuit area 3 surrounding it. In the input/output circuit area 3, a plurality of input/output terminals (bonding pads) 4 are installed.
しかしながら、このような方式にあつては次の
ような問題があつた。即ち、入出力端子のピツチ
は、外囲器（パツケージ）とのボンデイングの際
の制約や入出力回路を構成する際の制約によりそ
れ程小さくすることができない。このため、特に
大規模なゲート・アレイにおいては、内部の基本
セルの数に比較して入出力端子数が不足するよう
な欠点があつた。また、入出力回路の数が多くな
ると、多数の出力回路がONすることにより発生
する電源の揺ぎや変位電流により、誤つた読込み
やラツチアツプ虞れが問題となる。 However, such a method has the following problems. That is, the pitch of the input/output terminals cannot be made so small due to restrictions in bonding with the envelope (package) and restrictions in configuring the input/output circuit. For this reason, especially in large-scale gate arrays, there was a drawback that the number of input/output terminals was insufficient compared to the number of internal basic cells. Furthermore, as the number of input/output circuits increases, problems arise such as erroneous reading and latch-up due to fluctuations in the power supply and displacement currents that occur when a large number of output circuits are turned on.
本発明の目的は、内部の基本セルの数に比較し
て入出力端子の数を十分多くすることができ、か
つ電源の揺ぎや変位電流の低減をはかり得、多数
の入出力回路を有するゲート・アレイ等に適した
マスタ・スライス型半導体装置を提供することに
ある。
An object of the present invention is to provide a gate having a large number of input/output circuits, which can sufficiently increase the number of input/output terminals compared to the number of internal basic cells, and can reduce fluctuations in power supply and displacement current. - To provide a master slice type semiconductor device suitable for arrays, etc.
本発明の骨子は、半導体チツプの周囲に配置さ
れる入出力回路領域の面積増大をはかると共に、
ボンデイングの妨げとならないよう入出力端子の
配置位置を定めたことにある。
The gist of the present invention is to increase the area of an input/output circuit area arranged around a semiconductor chip, and
The input/output terminals are arranged in such a way that they do not interfere with bonding.
即ち本発明は、半導体基板に複数個の能動素子
からなる基本セルを複数個配列した基本素子領域
と、その周囲に入出力領域が形成されてなるチツ
プに必要に応じた配線パターンを施して所望の回
路動作に実現するマスタ・スライス型半導体装置
において、上記入出力領域を上記基板の最外周に
形成された第１の入出力回路領域と、その内側に
形成された第２の入出力回路領域とから構成し、
かつ第２の入出力回路領域のボンデイング・パツ
ドを第１の入出力回路領域の隣り合う２つのボン
デイング・パツド間に形成するようにしたもので
ある。 That is, the present invention provides a chip having a basic element area in which a plurality of basic cells each consisting of a plurality of active elements are arranged on a semiconductor substrate, and an input/output area formed around the basic element area, and a wiring pattern as required to form a desired wiring pattern. In a master slice type semiconductor device that realizes circuit operation, the input/output area is a first input/output circuit area formed on the outermost periphery of the substrate, and a second input/output circuit area formed inside the first input/output circuit area. Consisting of
In addition, the bonding pad in the second input/output circuit area is formed between two adjacent bonding pads in the first input/output circuit area.
本発明によれば、入出力回路をチツプの最外周
だけでなくその内側にも形成しているので、従来
と同ピツチであつても入出力端子の個数を十分多
くすることができる。即ち、多ピン化が可能とな
る。また、外側と内側との入出力回路に供給する
電源線或いは接地線を分離することにより多数の
出力回路を外側と分配することができ、出力回路
が同時にONする際の電源線の揺ぎや変位電流を
低減することが可能となる。このため、特に大規
模なゲート・アレイ等において極めて有効であ
る。
According to the present invention, since the input/output circuit is formed not only on the outermost periphery of the chip but also on the inner side thereof, the number of input/output terminals can be sufficiently increased even with the same pitch as the conventional chip. That is, it becomes possible to increase the number of pins. In addition, by separating the power line or ground line that supplies the input/output circuits on the outside and inside, multiple output circuits can be distributed to the outside, and fluctuations and displacement of the power line when the output circuits are turned on at the same time can be avoided. It becomes possible to reduce the current. Therefore, it is extremely effective, especially in large-scale gate arrays.
第２図は本発明の一実施例に係わるゲート・ア
レイの概略構成を示す平面模式図である。図中１
０は半導体チツプであり、このチツプ１０上の中
央部には基本素子領域２０が形成されている。基
本素子領域２０の外側には入出力回路領域（第２
の入出力回路領域）３０が形成され、その外側に
は入出力回路領域（第１の入出力回路領域）４０
が形成されている。これらの入出力回路領域３
０，４０には、マスター工程においてトランジス
タの他に抵抗等の保護回路が形成される。なお、
第２図は配線工程を施した後の図であり、そのう
ち特に本発明に関する配線だけを示している。
FIG. 2 is a schematic plan view showing a schematic configuration of a gate array according to an embodiment of the present invention. 1 in the diagram
0 is a semiconductor chip, and a basic element region 20 is formed in the center of this chip 10. Outside the basic element area 20 is an input/output circuit area (second
An input/output circuit area (first input/output circuit area) 30 is formed outside the input/output circuit area (first input/output circuit area) 40.
is formed. These input/output circuit areas 3
0 and 40, a protection circuit such as a resistor is formed in addition to a transistor in the master process. In addition,
FIG. 2 is a diagram after the wiring process has been performed, of which only the wiring particularly related to the present invention is shown.
最外周の第１の入出力回路領域４０にはトラン
ジスタや保護回路等を配線接続して入力回路及び
出力回路等が形成される。さらに、この入出力回
路領域４０にはボンデイング・パツド（入出力端
子）４１、電源線（Vdd線）４２及び接地線
（Vss線）４３が形成される。電源線４２及び接
地線４３に電位を供給するのは入出力回路領域４
０のうちの１つ或いは複数の入出力回路である。 In the first input/output circuit area 40 on the outermost periphery, input circuits, output circuits, etc. are formed by connecting transistors, protection circuits, etc. with wiring. Further, in this input/output circuit area 40, a bonding pad (input/output terminal) 41, a power line (Vdd line) 42, and a ground line (Vss line) 43 are formed. The input/output circuit area 4 supplies potential to the power supply line 42 and the ground line 43.
0 or more input/output circuits.
一方、内側の第２の入出力回路領域３０にもボ
ンデイング・パツド３１、電源線３２及び接地線
３３が形成される。ここで、ボンデイング・パツ
ド３１は最外周の隣り合う２つのボンデイング・
パツド４１間に形成される。また、電源線３２及
び接地線３３のうちの少なくとも一方は最外周の
電源線４２若しくは接地線４３と接続されず、入
出力回路領域３０の１つ或いは複数個の入力回路
から電位を供給される。さらに、基本素子領域２
０への電位の供給は入出力回路領域３０の電源線
３２及び接地線３３よりなされる。 On the other hand, a bonding pad 31, a power supply line 32, and a ground line 33 are also formed in the inner second input/output circuit area 30. Here, the bonding pad 31 is connected to two adjacent bonding pads on the outermost periphery.
It is formed between pads 41. Further, at least one of the power line 32 and the ground line 33 is not connected to the outermost power line 42 or the ground line 43, and is supplied with a potential from one or more input circuits in the input/output circuit area 30. . Furthermore, basic element area 2
0 is supplied from the power supply line 32 and ground line 33 of the input/output circuit area 30.
このような構成であれば、入出力回路領域を最
外周のみに形成したものに比して入出力端子の数
を大幅に増加させることができる。このため、多
数の入出力端子を持つゲート・アレイにも十分対
処することができる。また、内側の入出力回路領
域３０を入力回路だけに用いると、電源線３２及
び接地線の３３の少なくとも一方が最外周の電源
線４２若しくは接地線４３と接続されていないた
め、最外周の多数の出力回路が同時にONする場
合にも、従来と比較して電源線３２及び接地線３
３の揺ぎや変位電流等を低減することができる。 With such a configuration, the number of input/output terminals can be significantly increased compared to a configuration in which the input/output circuit area is formed only on the outermost periphery. Therefore, it can adequately handle gate arrays having a large number of input/output terminals. Furthermore, if the inner input/output circuit area 30 is used only for the input circuit, at least one of the power supply line 32 and the ground line 33 is not connected to the outermost power supply line 42 or the ground line 43, so that many of the outermost circumference Even when the output circuits of
It is possible to reduce the fluctuation, displacement current, etc. of No. 3.
なお、本発明は上述した実施例に限定されるも
のではない。例えば、前記各入出力回路領域のボ
ンデイング・パツドの数及びピツチ等は仕様に応
じて適宜定めればよい。さらに、ゲート・アレイ
に限らず各種のマスタ・スライス型半導体装置に
適用できるのは勿論のことである。また、入出力
回路領域は２つに限定されるものではなく、それ
以上形成することも可能である。さらに、複数の
入出力回路領域がマスター工程により入力回路専
用領域及び出力回路専用領域等に形成されている
場合にも適用可能である。その他、本発明の要旨
を逸脱しない範囲で、種々変形して実施すること
ができる。 Note that the present invention is not limited to the embodiments described above. For example, the number and pitch of bonding pads in each input/output circuit area may be determined as appropriate according to specifications. Furthermore, it goes without saying that the present invention can be applied not only to gate arrays but also to various master slice type semiconductor devices. Furthermore, the number of input/output circuit areas is not limited to two, and more than two areas can be formed. Furthermore, it is also applicable to a case where a plurality of input/output circuit areas are formed as an input circuit dedicated area, an output circuit dedicated area, etc. by a master process. In addition, various modifications can be made without departing from the gist of the present invention.
第１図は従来のゲート・アレイ構造を示す平面
模式図、第２図は本発明の一実施例に係わるゲー
ト・アレイの概略構成を示す平面図である。
１０……半導体チツプ、２０……基本素子領
域、３０……第２の入出力回路領域、４０……第
１の入出力回路領域、３１，４１……ボンデイン
グ・パツド（入出力端子）、３２，４２……電源
線、３３，４３……接地線。
FIG. 1 is a schematic plan view showing a conventional gate array structure, and FIG. 2 is a plan view showing a schematic configuration of a gate array according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 10... Semiconductor chip, 20... Basic element area, 30... Second input/output circuit area, 40... First input/output circuit area, 31, 41... Bonding pad (input/output terminal), 32 , 42...power line, 33,43...ground line.
Claims (1)
セルを複数個配列した基本素子領域と、その周囲
に入出力領域が形成されてなるチツプに必要に応
じた配線パターンを施して所望の回路動作を実現
するマスタ・スライス型半導体装置において、前
記入出力領域は前記基板の最外周に形成された第
１の入出力回路領域と、その内側に形成された第
２の入出力回路領域とからなるもので、かつ第２
の入出力回路領域のボンデイング・パツドは第１
の入出力回路領域の隣り合う２つのボンデイン
グ・パツト間に形成されたものであることを特徴
とするマスタ・スライス型半導体装置。 ２ 前記第２の入出力回路領域は、入力回路のみ
で構成されていることを特徴とする特許請求の範
囲第１項記載のマスタ・スライス型半導体装置。 ３ 電源線或いは接地線の少なくとも一方が、前
記第１の入出力回路領域と第２の入出力回路領域
とで接続されていないことを特徴とする特許請求
の範囲第１項記載のマスタ・スライス型半導体装
置。 ４ 電源線或いは接地線の少なくとも一方が、前
記第１の入出力回路領域と第２の入出力回路領域
とで接続されておらず、かつ第２の入出力回路領
域から基本素子領域へ電位を供給することを特徴
とする特許請求の範囲第１項記載のマスタ・スラ
イス型半導体装置。[Claims] 1. A chip having a basic element area in which a plurality of basic cells each consisting of a plurality of active elements are arranged on a semiconductor substrate, and an input/output area formed around it, is provided with a wiring pattern as necessary. In a master slice type semiconductor device that realizes a desired circuit operation, the input/output area includes a first input/output circuit area formed on the outermost periphery of the substrate, and a second input/output circuit area formed inside the first input/output circuit area. a circuit area, and a second
The bonding pad in the input/output circuit area is
A master slice type semiconductor device, characterized in that it is formed between two adjacent bonding pads in an input/output circuit area. 2. The master slice type semiconductor device according to claim 1, wherein the second input/output circuit area is composed of only input circuits. 3. The master slice according to claim 1, wherein at least one of the power supply line and the ground line is not connected between the first input/output circuit area and the second input/output circuit area. type semiconductor device. 4. At least one of the power supply line and the ground line is not connected between the first input/output circuit area and the second input/output circuit area, and does not transmit a potential from the second input/output circuit area to the basic element area. A master slice type semiconductor device according to claim 1, wherein the master slice type semiconductor device is provided with a master slice type semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17859183A JPS6070742A (en) | 1983-09-27 | 1983-09-27 | Master slice type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17859183A JPS6070742A (en) | 1983-09-27 | 1983-09-27 | Master slice type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6070742A JPS6070742A (en) | 1985-04-22 |
| JPH0542823B2 true JPH0542823B2 (en) | 1993-06-29 |
Family
ID=16051136
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17859183A Granted JPS6070742A (en) | 1983-09-27 | 1983-09-27 | Master slice type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6070742A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02180049A (en) * | 1989-01-04 | 1990-07-12 | Nec Corp | Semiconductor device |
| US5216280A (en) * | 1989-12-02 | 1993-06-01 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device having pads at periphery of semiconductor chip |
| JPH0327529A (en) * | 1990-02-23 | 1991-02-05 | Seiko Epson Corp | Semiconductor integrated circuit device |
| US5548135A (en) * | 1995-05-12 | 1996-08-20 | David Sarnoff Research Center, Inc. | Electrostatic discharge protection for an array of macro cells |
| JP2006100436A (en) | 2004-09-28 | 2006-04-13 | Toshiba Corp | Semiconductor device |
-
1983
- 1983-09-27 JP JP17859183A patent/JPS6070742A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6070742A (en) | 1985-04-22 |
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