JPS6290948A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To effectively utilize an inner gate region by removing a buffer region formed heretofore, enlarging the inner gate region, composing to alternately disposing P-type and N-type MOS transistor rows, and constructing a buffer circuit of the transistor arrays for the inner gate, thereby omitting the waste in the buffer region. CONSTITUTION:A semiconductor integrated circuit device has a transistor array region (inner gate substrate) 1 and a pad region 3 only. The array region 1 is alternately arranged with the rows of P-type, N-type MOS transistors. P-type and N-type MOS transistor regions 15, 16 are formed of 2 MOS transistors in such a manner that the sources or the drains of two transistors are composite. Terminals 18, 19 are connected with a power source VDD and a ground point. When P-type MOS transistors T1-T6, N-type MOS transistors T7-T12 are wired suitably in parallel, an output buffer is formed. Similarly, an input buffer is composed by the transistors of the region 1.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a mask-sliced complementary MOS in which transistors are arranged in an array to form a logic gate.
(0MOS) type integrated circuit device.

[Conventional technology]

The 0-mask slicing method is known as a method for realizing many types of logic integrated circuit devices in a short period of time by manufacturing gate arrays using the mask slicing method.
In the mastering process, transistors common to each type are formed in advance, and in the slicing process, the required connections for each type of transistor are made between the transistors to realize the desired logic integrated circuit device. , is a diagram showing an example of a chip configuration of a conventionally known CMOS type gate array. In FIG. 2(a), (1) is an internal gate area for configuring a logic circuit, (2) is a buffer area for matching the inside and outside of the semiconductor chip, and (3) is an internal gate area for configuring this semiconductor chip. This is a pad for connection to a mounted package (not shown).

The internal gate region (1) has V<C as shown in FIG. 2(b).
Multiple transistor rows for configuring MOS gates (wiring area α for interconnection between IQ and transistor rows a0])! It is composed of this.

The first # wiring @,
2nd layer wiring (to) and 1st layer wiring. A through hole α4 for connecting the second layer wiring is used. In gate arrays, the number of wires permissible for a given wiring area is determined in advance, so the number of wires allowed in a gate array is set wide enough to allow wiring even when configuring complex logic2. Fixed. Therefore, in the case of a logic configuration that is possible with simple wiring, the large unused wiring area (b) is completely wasted (wasteful and rare. Also, in order to create as many logic gates as possible consisting of transistor arrays αQ
Is it necessary to provide a large number of In order to avoid wasting the wiring area and configure many transistor rows αq, as shown in FIG. )
'The transistor array method used as the Y wiring area has been described in 4u-[ (for example, 1982 VLSI Symposium [116-17)]. According to this method, when a small number of wirings are needed, a small number of transistor rows 00 are printed, and when a large number of wirings are required, many transistor rows QQ are printed as a wiring area, and the wiring area is not fixed and the logic Since it can be changed freely depending on the configuration, it is possible to configure a very large number of logic gates in a cooking circuit with simple wiring. Figure 2 (b) shows an example of the case where the same configuration is applied. , as shown in FIG. 2(c), the length of the wiring is shortened, and moreover, it is possible to mount more logic circuits with the same ff1li product.

[Problem that the invention seeks to solve]

However, traditional gate arrays, transistors.

As shown in Figure 2(a), the array has a physically fixed buffer area in addition to the necessary internal gate area, so for example, 200 input and output buffers are prepared. , if only 20 input and output sofas were used in the slicing process, the remaining 18
Space in 0 buffers was wasted.

It is an object of the present invention to provide a semiconductor integrated circuit device having an array configuration that can eliminate such waste in the buffer area and effectively utilize the internal gate area within the semiconductor chip.

[Means for solving problems]

The transistor array according to the present invention, as shown in FIG.
It is constructed by alternately arranging S-transistor rows and n-type MOSI-transistor rows, so that the buffer circuit can be constructed from transistor rows for internal gates.

[For production]

Since the input and output buffers of the transistor array according to the present invention are constituted by transistor rows in the internal gate area, the buffer area required in the conventional transistor play can be replaced with the internal gate area, and the number of buffers used can be reduced. [Embodiment of the Invention] FIG. 1(a) is a schematic diagram showing the overall configuration of an embodiment of the present invention. gate d area)
The book 7 consists only of (1) and bad area (3).

The play area (1) is a row of p-type MOS transistors as shown in FIG. 1(b) and below. Rows of transistors are arranged alternately.

Next, the case where a buffer is formed by the MOS transistor array in this play area (1) will be explained in detail.

In FIG. 1(b), a pattern showing the configuration of the output buffer 7) is a p-type MOS transistor region, and σ is an n-type 1viO
8 transistor area, α + tMOSl-transistor gate, light is substrate outlet of p-type MOS transistor, α
g is the substrate outlet of the n-type MOS transistor.

The MOS transistor region and α region each consist of two MOS transistors, and are in the form of a composite of the sources or drains of the two transistors. Terminals 4 and 119 are connected to the power supply VDD and the ground point, respectively.P-type MOS transistors T1 to T6 and n-type MOS transistors T7 to TI2 are connected in parallel as appropriate as shown in FIG. 1(b). , it is easy to understand that it is possible to construct an output sofa whose equivalent circuit is shown in FIG. 1(c).

Fig. 1(d) is a cross-sectional diagram showing an example of the configuration of a manual buffer, and Fig. 1(e) is its equivalent circuit diagram. )27
The 9222 gate electrode layers are used as input protection resistors R, and the sources and
The junction between V and the substrate is used as a diode D and an island, respectively, and the three p-type MOS transistors from the right end are left open.

In this way, the input and output signals can be freely configured using the transistors in the array area (1). [Effects of the Invention] As described above, according to the present invention, the Since the buffer area provided as the area was removed and the buffer circuit was configured using transistors existing in the internal gate area, it is possible to configure more internal gates than before with the same chip area.

[Brief explanation of drawings]

FIG. 1(a) is a schematic diagram showing the overall configuration of an embodiment of the present invention, and FIG. 1(b) is a pattern diagram showing an example of an output sofa constructed of MOS transistor arrays in the transistor array region of this embodiment. , FIG. 1(C) is its equivalent circuit diagram, FIG. 1(d) is a pattern diagram showing a configuration example of the input buffer, FIG. 1(b) is its equivalent circuit diagram, and FIG. 2(a) is its equivalent circuit diagram. A chip configuration diagram of a conventional gate array. FIG. 2(b) is a configuration diagram showing an example in which a wiring area is provided in the internal gate area, and FIG. 2(c) is a configuration diagram showing an example of an internal gate area in which no wiring area is provided. In the figure, (1) is the transistor array area, (3
) is a pad region, 2) is a p-type MOS transistor region,
α is an n-type MOS transistor region, αη is a gate electrode, and R is an input protection resistor. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (3)

[Claims] (1) a transistor array region in which a plurality of p-type MOS transistor rows formed by arranging p-type MOS transistors in a row and n-type MOS transistor rows formed by arranging n-type MOS transistors in a row are alternately arranged; a pad area for connection to a package, and an input or output buffer for matching between a logic gate configured inside the array area and an external circuit is configured by a MOS transistor in the array area. A semiconductor integrated circuit device characterized by: (2) The semiconductor integrated circuit device according to claim 1, wherein the output buffer is constructed by connecting a plurality of MOS transistors in parallel as necessary. (3) Set the input protection resistance of the input buffer to p-type and n-type M.
3. The semiconductor integrated circuit device according to claim 1, wherein a gate electrode layer of an OS transistor is used.