JPH01125952A - Master slice integrated circuit - Google Patents

Master slice integrated circuit

Info

Publication number
JPH01125952A
JPH01125952A JP62286106A JP28610687A JPH01125952A JP H01125952 A JPH01125952 A JP H01125952A JP 62286106 A JP62286106 A JP 62286106A JP 28610687 A JP28610687 A JP 28610687A JP H01125952 A JPH01125952 A JP H01125952A
Authority
JP
Japan
Prior art keywords
basic
transistors
output current
buffer circuit
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62286106A
Other languages
Japanese (ja)
Inventor
Kazuyoshi Ofuji
大藤　一嘉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62286106A priority Critical patent/JPH01125952A/en
Publication of JPH01125952A publication Critical patent/JPH01125952A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11898—Input and output buffer/driver structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To obtain wide output current characteristic with a small number of basic transistors by connecting predetermined number of basic transistors in series or in parallel in response to the output current characteristics and composing an output buffer circuit. CONSTITUTION:A plurality of basic P-type transistors QP and basic N-type transistors QN are disposed on a region for forming an output buffer circuit on a semiconductor chip. The buffer circuit 1 connects only predetermined number of the transistors QP and QN by wirings 11 in series or in parallel at sources, drains, commonly at a gate thereby to form a CMOS to obtain predetermined output current characteristic. Two transistors QP and QN are respectively connected in parallel, and one is connected in series therewith thereby to obtain predetermined output current characteristic.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はマスタスライス集積回路に関し、特に出力電流
特性の異なる複数の出力バッファ回路を構成するマスタ
スライス集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a master slice integrated circuit, and more particularly to a master slice integrated circuit that constitutes a plurality of output buffer circuits having different output current characteristics.

〔従来の技術〕[Conventional technology]

従来、この種のマスタスライス集積回路は、出力電流特
性の異なる出力バッファ回路を構成する場合、第３図に
示すように、必要とする出力電流特性のうちの最も出力
電流の小さな出力バッファ回路を構成する１対のＰ型及
びＮ型のトランジスタを基本Ｐ型トランジスタＱｐ’及
び基本Ｎ型トランジスタＱＮ’とし、これらを複数個づ
つ準備しておき、出力電流特性に応じてこれら基本Ｐ型
トランジスタＱｐ’＋基本Ｎ型トランジスタＱＮ’を必
要数だけ並列に配線で接続することにより、所定の出力
電流特性の出力バッファ回路１ｂを構成していた。Conventionally, when configuring output buffer circuits with different output current characteristics, this type of master slice integrated circuit selects an output buffer circuit with the smallest output current among the required output current characteristics, as shown in FIG. A pair of P-type and N-type transistors constitute a basic P-type transistor Qp' and a basic N-type transistor QN', and a plurality of these are prepared, and these basic P-type transistors Qp are changed according to the output current characteristics. An output buffer circuit 1b having a predetermined output current characteristic was configured by connecting a necessary number of '+ basic N-type transistors QN' in parallel with wiring.

通常、単一機能を持った集積回路においては、後段の集
積回路を動作させるための必要な出力電流は決まってい
るため１種類の出力バッファ回路があればよかった。し
かし、ゲートアレイの様に、個々のシステムに合せた仕
様により作られるカスタム集積回路においては、大電流
を必要とするものもあれば、逆に出力の同時変化による
電源ノイズ対策や不要輻射対策のために、小さな出力電
流を要求される場合がある。Normally, in an integrated circuit having a single function, only one type of output buffer circuit is required because the output current required to operate the subsequent integrated circuit is fixed. However, in custom integrated circuits such as gate arrays, which are made according to specifications tailored to each individual system, some require large currents, and conversely, simultaneous changes in output require countermeasures against power supply noise and unnecessary radiation. Therefore, a small output current may be required.

このような、要求に対処し、従来、ゲートアレイの様な
マスタスライス集積回路は、上述の様に、出力電流の小
さなトランジスタを複数個準備しておき、これらを必要
に応じて並列に接続して必要な出力電流を得る構成とな
っていた。そして、この構成では、出力バッファ回路の
出力電流の大小の差が大きければ大きいほど多くのトラ
ンジスタが必要となっていた。To address these demands, conventional master slice integrated circuits such as gate arrays prepare multiple transistors with small output currents and connect them in parallel as necessary, as described above. The configuration was such that the necessary output current could be obtained. In this configuration, the larger the difference in the output current of the output buffer circuit, the more transistors are required.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のマスタスライス集積回路は、最も出力電
流の小さい出力バッファ回路を構成するための基本Ｐ型
トランジスタＱｐ’及び基本Ｎ型トランジスタＱＮ’を
複数個づつ準備しておき、これらを出力電流特性に応じ
て必要な数だけ並列接続し所定の出力電流特性の出力バ
ッファ回路を得る構成となっているので、出力電流の差
が大きくなると基本Ｐ型トランジスタＱｐ’及び基本Ｎ
型トランジスタＱＮ’（以下これらを基本トランジスタ
という）の数が多くなり、配置や配線などのレイアウト
の問題で難しくなる上に、半導体チップ面積も大きくな
るという欠点がある。In the conventional master slice integrated circuit described above, a plurality of basic P-type transistors Qp' and a plurality of basic N-type transistors QN' are prepared in order to configure an output buffer circuit with the smallest output current, and these are set according to the output current characteristics. The configuration is such that an output buffer circuit with a predetermined output current characteristic is obtained by connecting the required number in parallel according to the
The disadvantage is that the number of type transistors QN' (hereinafter referred to as basic transistors) increases, making layout problems such as placement and wiring difficult, and that the semiconductor chip area also increases.

また、既存のマスタスライス集積回路においては低出力
電流の出力バッファ回路が必要であっても基本トランジ
スタがその出力電流を得るだけの大きさになっていない
と、低出力電流の出力バッファ回路が構成できないとい
う欠点があった。In addition, in existing master slice integrated circuits, even if an output buffer circuit with a low output current is required, if the basic transistor is not large enough to obtain the output current, the output buffer circuit with a low output current is configured. The drawback was that it couldn't be done.

本発明の目的は、出力電流の差が大きい場合でも基本ト
ランジスタの数が増大せず、配置や配線が容易になる上
に半導体チップ面積が小さくでき、かつ基本トランジス
タの出力電流より小さい低出力電流の出力バッファ回路
も構成することができるマスタスライス集積回路を提供
することにある。An object of the present invention is to provide a low output current that does not increase the number of basic transistors even when the difference in output current is large, facilitates placement and wiring, and reduces the semiconductor chip area, and that is smaller than the output current of the basic transistor. An object of the present invention is to provide a master slice integrated circuit that can also configure an output buffer circuit.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のマスタスライス集積回路は、複数の基本トラン
ジスタと、出力電流特性に応じて、前記複数の基本トラ
ンジスタのうちの所定の数の基本トランジスタのソース
・ドレインを互いに直列または並列接続しゲートを共通
接続する配線とを備えた出力バッファ回路を有している
。The master slice integrated circuit of the present invention includes a plurality of basic transistors, and sources and drains of a predetermined number of basic transistors among the plurality of basic transistors are connected in series or parallel to each other according to output current characteristics, and gates are shared. It has an output buffer circuit with connecting wiring.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.

第１図（ａ）、（ｂ）はそれぞれ本発明の第１の実施例
を示す半導体チップ上の配置を考慮した等価回路図及び
通常の回路図である。FIGS. 1(a) and 1(b) are an equivalent circuit diagram and a normal circuit diagram, respectively, showing a first embodiment of the present invention, taking into consideration the arrangement on a semiconductor chip.

半導体チップ上の出力バッファ回路を形成する領域には
、それぞれ複数個の基本Ｐ型トランジスタＱｐ及び基本
Ｎ型トランジスタＱＮが配置されている。A plurality of basic P-type transistors Qp and a plurality of basic N-type transistors QN are respectively arranged in regions forming an output buffer circuit on the semiconductor chip.

出力バッファ回路１は、出力電流特性に応じて、これら
基本Ｐ型トランジスタＱｐ及び基本Ｎ型トランジスタＱ
、のうちの所定の数だけ、配線１１によりそれぞれソー
ス・ドレインを直列または並列接続しゲートを共通接続
して所定の出力電流特性を得るＣＭＯ３型の構成となっ
ている。The output buffer circuit 1 consists of these basic P-type transistors Qp and basic N-type transistors Q, depending on the output current characteristics.
, the sources and drains of a predetermined number of the transistors are connected in series or in parallel by wiring 11, and the gates are commonly connected to obtain a predetermined output current characteristic.

第１図（ａ）、（ｂ）は、低出力電流の出力バッファ回
路１を得るために、ソース・ドレイン直列接続した接続
が示されている。FIGS. 1(a) and 1(b) show a connection in which the source and drain are connected in series in order to obtain an output buffer circuit 1 with a low output current.

このように、基本Ｐ型トランジスタＱｐ及び基本Ｎ型ト
ランジスタＱＮ　（以下総称して基本トランジスタとい
う）を直列接続することにより、これら基本トラジスタ
のオン抵抗が直列接続されたことになり、出力バッファ
回路１の出力電流を大幅に低減することができる。In this way, by connecting the basic P-type transistor Qp and the basic N-type transistor QN (hereinafter collectively referred to as basic transistors) in series, the on-resistances of these basic transistors are connected in series, and the output buffer circuit 1 The output current can be significantly reduced.

第２図は本発明の第２の実施例を示す回路図である。FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

この例は、基本Ｐ型トランジスタＱｐ及び基本Ｎ型トラ
ンジスタＱＮをそれぞれ２個並列接続したものに１個を
直列接続し、所定の出力電流特性を得るようにしたもの
である。In this example, two basic P-type transistors Qp and two basic N-type transistors QN are connected in parallel, and one transistor is connected in series to obtain a predetermined output current characteristic.

これら実施例のように、出力電流特性に応じて、基本ト
ランジスタを直列または並列接続することにより、少な
い基本トランジスタで出力電流特性の範囲を拡大するこ
とができる。これは既設針のマスタスライス集積回路に
適用することができる。As in these embodiments, by connecting basic transistors in series or in parallel depending on the output current characteristics, the range of output current characteristics can be expanded with a small number of basic transistors. This can be applied to the existing needle master slice integrated circuit.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、出力電流特性に応じて所
定の数の基本トランジスタを直列または並列接続し出力
バッファ回路を構成することにより、少ない基本トラン
ジスタで幅広い出力電流特性を得ることができるので、
従来のように小さな出力電流の基本トランジスタを多数
作る必要がなく、配置、配線が容易になる上に半導体チ
ップの面積も小さくできるという効果がある。As explained above, the present invention makes it possible to obtain a wide range of output current characteristics with a small number of basic transistors by configuring an output buffer circuit by connecting a predetermined number of basic transistors in series or in parallel according to the output current characteristics. ,
There is no need to create a large number of basic transistors with small output currents as in the conventional method, which makes arrangement and wiring easier, and the area of the semiconductor chip can also be reduced.

また、既設針のマスタスライス集積回路についても配線
による接続を変えるだけで基本トランジスタ１個の出力
電流より低い低出力電流用の出力バッファ回路を構成す
ることができる効果がある。Furthermore, with respect to the existing master slice integrated circuit, it is possible to configure an output buffer circuit for a low output current lower than the output current of one basic transistor by simply changing the wiring connections.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）、（ｂ）はそれぞれ本発明の第１の実施例
を示す半導体チップ上の配置を考慮した等価回路図及び
通常の回路図、第２図は本発明の第２の実施例を示す回
路図、第３図は従来のマスタスライス集積回路の一例を
示す回路図である。 １．１−、ｌｂ・・・出力バッファ回路、２・・・パッ
ド、１１・・・配線、ＱＮ　、　ＱＮ　’・・・基本Ｎ
型トランジスタ、Ｑｐ、Ｑｐ’・・・基本Ｐ型トランジ
スタ。FIGS. 1(a) and 1(b) are an equivalent circuit diagram and a normal circuit diagram, respectively, taking into account the arrangement on a semiconductor chip, showing a first embodiment of the present invention, and FIG. 2 is a second embodiment of the present invention. Circuit Diagram Showing an Example FIG. 3 is a circuit diagram showing an example of a conventional master slice integrated circuit. 1.1-, lb...output buffer circuit, 2...pad, 11...wiring, QN, QN'...basic N
type transistor, Qp, Qp'...Basic P-type transistor.

Claims (1)

【特許請求の範囲】[Claims] 　複数の基本トランジスタと、出力電流特性に応じて、
前記複数の基本トランジスタのうちの所定の数の基本ト
ランジスタのソース・ドレインを互いに直列または並列
接続しゲートを共通接続する配線とを備えた出力バッフ
ァ回路を有することを特徴とするマスタスライス集積回
路。Depending on multiple basic transistors and output current characteristics,
A master slice integrated circuit characterized by having an output buffer circuit including a wiring that connects the sources and drains of a predetermined number of basic transistors among the plurality of basic transistors in series or parallel to each other and connects the gates in common.
JP62286106A 1987-11-11 1987-11-11 Master slice integrated circuit Pending JPH01125952A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62286106A JPH01125952A (en) 1987-11-11 1987-11-11 Master slice integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62286106A JPH01125952A (en) 1987-11-11 1987-11-11 Master slice integrated circuit

Publications (1)

Publication Number Publication Date
JPH01125952A true JPH01125952A (en) 1989-05-18

Family

ID=17700011

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62286106A Pending JPH01125952A (en) 1987-11-11 1987-11-11 Master slice integrated circuit

Country Status (1)

Country Link
JP (1) JPH01125952A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992012575A1 (en) * 1991-01-12 1992-07-23 Tadashi Shibata Semiconductor device
US5594372A (en) * 1989-06-02 1997-01-14 Shibata; Tadashi Source follower using NMOS and PMOS transistors

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5594372A (en) * 1989-06-02 1997-01-14 Shibata; Tadashi Source follower using NMOS and PMOS transistors
WO1992012575A1 (en) * 1991-01-12 1992-07-23 Tadashi Shibata Semiconductor device
US5469085A (en) * 1991-01-12 1995-11-21 Shibata; Tadashi Source follower using two pairs of NMOS and PMOS transistors

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