JPH05300006A - Two-input and circuit - Google Patents
Two-input and circuitInfo
- Publication number
- JPH05300006A JPH05300006A JP4122769A JP12276992A JPH05300006A JP H05300006 A JPH05300006 A JP H05300006A JP 4122769 A JP4122769 A JP 4122769A JP 12276992 A JP12276992 A JP 12276992A JP H05300006 A JPH05300006 A JP H05300006A
- Authority
- JP
- Japan
- Prior art keywords
- input
- circuit
- terminal
- signal
- inputted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Logic Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体デバイス全般に
使用する２入力ＡＮＤ回路に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a 2-input AND circuit used for semiconductor devices in general.
【０００２】[0002]
【従来の技術】従来使用されていた２入力ＡＮＤ回路は
ＣＭＯＳ回路の場合、入力の一方がローの場合、並列に
２つ配置配線されたＰ型トランジスタの１つがＯＮ状態
となり、電源ＶＤＤからハイの信号を出力し、次段のイ
ンバータを通過して、最終的にローを出力する。またす
べての入力がハイの場合には、直列に２つ配置配線され
たＮ型トランジスタがすべてＯＮ状態になり、グランド
ＧＮＤからローの信号を出力し、次段のインバータを通
過して最終的にハイを出力するという動作で実現されて
いたため、トランジスタ６個で構成されていた。2. Description of the Related Art Conventionally used two-input AND circuits are CMOS circuits. When one of the inputs is low, one of two P-type transistors arranged and wired in parallel is turned on and the power supply VDD goes high. Signal is output, passes through the inverter of the next stage, and finally outputs low. When all inputs are high, all two N-type transistors arranged and wired in series are turned on, output a low signal from ground GND, and pass through the inverter at the next stage to finally Since it was realized by the operation of outputting high, it was composed of six transistors.
【０００３】[0003]
【発明が解決しようとする課題】従来の２入力ＡＮＤ回
路は、上記説明のごとく６トランジスタ構成になってい
たため、これら論理ゲートを多数使用した場合レイアウ
ト面積が大きくなってしまうという問題があった。Since the conventional 2-input AND circuit has the 6-transistor configuration as described above, there is a problem that the layout area becomes large when a large number of these logic gates are used.
【０００４】本発明は上記事情に基づいてなされたもの
であり、２入力ＡＮＤ回路を構成するトランジスタ数を
減少させることによって、レイアウト面積の減少をはか
ることを目的とする。The present invention has been made based on the above circumstances, and an object thereof is to reduce the layout area by reducing the number of transistors forming a 2-input AND circuit.
【０００５】[0005]
【課題を解決するための手段】上記の目的を達成するた
めの本発明は、２つの入力端子を備えたＡＮＤ回路にお
いて、この２つの入力端子のうちの一方の入力端子にロ
ー信号が入力した際には、前記ＡＮＤ回路の出力信号を
ローにし、前記入力端子にハイ信号が入力した際には、
前記ＡＮＤ回路の出力信号を不変にすることを特徴とす
るものである。According to the present invention for achieving the above object, in an AND circuit having two input terminals, a low signal is input to one of the two input terminals. In this case, when the output signal of the AND circuit is set to low and a high signal is input to the input terminal,
The output signal of the AND circuit is invariable.
【０００６】[0006]
【作用】本発明の作用について、表１を参照して説明す
る。ａ，ｂは半導体論理回路の２入力ＡＮＤ回路におけ
る２つのデータ入力のことで、ｘは出力、ＧＮＤはグラ
ンドのことで信号ローをそれぞれ表す。まず入力ａがロ
ーの場合、出力ｘは無条件でＧＮＤとつながり、ロー状
態を取り、入力ａがハイの場合は出力ｘはｂが出力され
る。以上のアルゴリズムを基に回路構成トランジスタ数
を減らすことにより、レイアウト面積の減少を実現す
る。The operation of the present invention will be described with reference to Table 1. a and b are two data inputs in the two-input AND circuit of the semiconductor logic circuit, x is an output and GND is a ground, which represents a signal low. First, when the input a is low, the output x is unconditionally connected to GND and takes a low state, and when the input a is high, the output x is b. By reducing the number of circuit transistors based on the above algorithm, the layout area can be reduced.
【０００７】[0007]
【表１】 [Table 1]
【０００８】[0008]
【実施例】以下に図面を参照しつつ本発明の実施例につ
いて説明する。図１は本発明の一実施例である２入力Ａ
ＮＤ回路である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a 2-input A which is an embodiment of the present invention.
It is an ND circuit.
【０００９】図１において、入力端子ａがローを入力し
た場合、入力端子ｂに入力される信号にかかわらずＰ型
トランジスタＰ０がＯＮし出力端子ｘにグランド端子Ｇ
ＮＤからローが出力される。またａにハイを入力した場
合、Ｎ型トランジスタＮ０がＯＮし出力端子ｘには入力
端子ｂに入力した信号が出力される。この動作によっ
て、２つの入力信号のうちいずれかがローの場合は、出
力信号はローを、また２つの入力信号の両方がハイの場
合には出力信号にハイを出力する２入力ＡＮＤ回路がト
ランジスタ２つで実現する。In FIG. 1, when the input terminal a inputs low, the P-type transistor P0 is turned on regardless of the signal input to the input terminal b and the output terminal x is connected to the ground terminal G.
Low is output from ND. When a high is input to a, the N-type transistor N0 is turned on and the signal input to the input terminal b is output to the output terminal x. By this operation, a 2-input AND circuit that outputs a low output signal when either of the two input signals is low and a high output signal when both of the two input signals are high is a transistor. Realize in two.
【００１０】[0010]
【発明の効果】以上説明したように本発明によれば、２
入力ＡＮＤ回路のある決まった片方の入力がローの場
合、無条件で出力信号をローにし、ハイの場合は、もう
一方の入力をそのまま出力するというアルゴリズムを基
に、２個のトランジスタで２入力ＡＮＤ回路を構成する
ことを可能にし、この結果、従来よりも小さい面積の回
路を提供することができる。As described above, according to the present invention, 2
If one input of the input AND circuit is low, the output signal is unconditionally set to low, and if it is high, the other input is output as it is. It is possible to configure an AND circuit, and as a result, it is possible to provide a circuit having a smaller area than the conventional one.
【図１】本発明の一実施例である２入力ＡＮＤ回路であ
って２個のトランジスタで構成されている２入力ＡＮＤ
回路の回路図である。FIG. 1 is a 2-input AND circuit according to an embodiment of the present invention, the 2-input AND circuit including two transistors.
It is a circuit diagram of a circuit.
ａ，ｂ 入力端子 ｘ 出力端子 Ｎ０ Ｎ型トランジスタ Ｐ０ Ｐ型トランジスタ ＧＮＤ グランド端子 a, b Input terminal x Output terminal N0 N-type transistor P0 P-type transistor GND Ground terminal
Claims (1)
いて、この２つの入力端子のうちの一方の入力端子にロ
ー信号が入力した際には、前記ＡＮＤ回路の出力信号を
ローにし、前記入力端子にハイ信号が入力した際には、
前記ＡＮＤ回路の出力信号を不変にすることを特徴とす
るＡＮＤ回路。1. In an AND circuit having two input terminals, when a low signal is input to one of the two input terminals, the output signal of the AND circuit is set to low and the input signal is set to low. When a high signal is input to the terminal,
An AND circuit which makes the output signal of the AND circuit unchanged.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4122769A JPH05300006A (en) | 1992-04-16 | 1992-04-16 | Two-input and circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4122769A JPH05300006A (en) | 1992-04-16 | 1992-04-16 | Two-input and circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05300006A true JPH05300006A (en) | 1993-11-12 |
Family
ID=14844163
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4122769A Withdrawn JPH05300006A (en) | 1992-04-16 | 1992-04-16 | Two-input and circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05300006A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100560922B1 (en) * | 2004-08-09 | 2006-03-14 | 엘지이노텍 주식회사 | IC driving circuit |
| JP2006180197A (en) * | 2004-12-22 | 2006-07-06 | Nec Electronics Corp | Logic circuit and word driver circuit |
-
1992
- 1992-04-16 JP JP4122769A patent/JPH05300006A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100560922B1 (en) * | 2004-08-09 | 2006-03-14 | 엘지이노텍 주식회사 | IC driving circuit |
| JP2006180197A (en) * | 2004-12-22 | 2006-07-06 | Nec Electronics Corp | Logic circuit and word driver circuit |
| JP4562515B2 (en) * | 2004-12-22 | 2010-10-13 | ルネサスエレクトロニクス株式会社 | Logic circuit and word driver circuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990706 |