JP2661337B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reducing a clock skew in a gate array and consequently realizing an increase in the speed of an LSI. The present invention relates to a technique useful for a gate array called a system.

[Conventional technology]

Fig. 3 shows the document "IEICE Technical Report VLD89-1".
FIG. 31 is a pattern diagram showing an example of implementing clock distribution in the conventional gate array shown in “03, 47-52”.

In FIG. 3, A is a clock input terminal to which an external clock signal a is input, 2 is a clock driver, 3 is a clock receiver, 4 is a receiver / driver connection connecting the output of the clock receiver 3 and the input of the clock driver 2. Wiring, 1C is a clock signal line of a second layer metal thicker than the normal signal wiring connected to the output of the clock driver 2,
1A is a clock signal line made of a first layer metal connected to the clock signal line 1C through a through hole, 1B is a clock signal line made of a second layer metal connected to the clock signal line 1A through a through hole, and 1D is A clock branch line composed of a first-layer metal wiring connected to the clock signal lines 1B and 1C via a through-hole, 1E is a clock signal line composed of a second-layer metal wiring connected from the clock branch line 1D via a through-hole, and 5a is A sequential circuit such as a flip-flop, 5b is a combinational circuit, 6 is a second-layer power supply line made of a second-layer metal for supplying power to the area of the internal cells 5a and 5b, and 7 is an input / output buffer area. The clock signal lines 1A and 1B form a ring-shaped wiring, and the clock signal line 1E connects the clock branch line 1D and the input / output terminal of the sequential circuit 5a. Also, clock signal lines 1A and 1B, clock signal line 1C, clock branch line 1D, and clock signal line
1E constitutes the clock signal wiring.

Next, the wiring method and operation of the conventional semiconductor integrated circuit device will be described. In the semiconductor integrated circuit device shown in FIG. 3, the clock signal lines 1B and 1B
C is wired in advance. Since the area where the clock signal lines 1B and 1C are wired is treated as an internal gate and a second layer power supply wiring prohibited area in the wiring program, it does not affect the normal signal line wiring by the wiring program. In addition, the wiring of the clock signal line 1A is also inscribed in the input / output buffer area 7 and a wiring area is reserved in advance and treated as a prohibited area for internal cell placement and a signal wiring prohibited area by the first layer metal. This does not affect the signal line wiring. The clock branch line 1D needs to be thicker than a normal signal line in order to suppress skew. However, the number of clock signal lines 1B and 1C equal to the number of internal cell rows to be arranged is assigned to the first layer signal wiring channel.
The wiring can be easily performed by using a current commercially available layout tool. Also,
The connection between the clock signal line 1E and the sequential circuit 5a can also be easily wired using a commercially available layout tool.

As described above, since a large number of sequential circuits 5a can be driven collectively by the clock driver 2 without any special program for clock signal wiring, skew of clock signals can be reduced. That is, since each clock signal line is arranged in a mesh, the resistance from the clock driver to the sequential circuit is reduced, and the skew of the clock signal is reduced.

[Problems to be solved by the invention]

Since the conventional semiconductor integrated circuit device is configured as described above, there are the following problems.

Because the pin position where the clock signal can be input is fixed
Constrain the design of the board on which the LSI is mounted.

Since the external clock signal is directly applied to the circuit sequentially, it is difficult to control the suppression of the clock signal.

The present invention has been made in view of such a point,
The purpose is to make it possible to select the input pin position of the clock signal arbitrarily in the gate array of the master slice type, and to easily control the clock suppression etc. under various conditions, and to design the logic. It is to obtain an easy-to-use geoarray LSI.

[Means for solving the problem]

In order to achieve such an object, the present invention provides an input buffer cell for receiving a clock signal external to the chip and transmitting the clock signal to the inside of the chip, and a clock signal from the input buffer cell directly or via a control gate by the internal cell. A pre-driver circuit for receiving the output of the pre-driver circuit, at least one clock driver for driving the sequential circuit in response to the output of the pre-driver circuit, a clock signal line for connecting the output of the clock driver to the sequential circuit, and a clock signal line. A plurality of sequential circuits connected to each other, wherein the clock signal wiring is a ring-shaped wiring composed of a third-layer metal wiring and a second-layer metal wiring adjacent to the inner periphery of the input / output buffer area;
At least one second-layer metal wiring which runs adjacent to and parallel to the second-layer power supply wiring arranged in the internal cell region, is connected to the output terminal of the clock driver, and is connected to the ring-shaped wiring; It is composed of a layer metal wiring and at least one first-layer metal clock branch connected to a ring-shaped wiring, and the clock signal wiring is arranged in a grid pattern.

[Action]

In the semiconductor integrated circuit device according to the present invention, a clock signal can be input to an input buffer at an arbitrary position, and the clock signal can be transmitted to a clock distribution circuit directly or via an internal control gate.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 2 is a logic diagram showing logic of a clock signal in the semiconductor integrated circuit device according to the present invention. The external clock signal a is input to an input buffer A, its output is input to a control circuit B by internal cells, and the output of the circuit B is input to a pre-driver 3 (conventional clock receiver 3) for clock distribution. The output of the pre-driver 3 is supplied to the clock driver 2 via the pre-driver / driver connection wiring 4 (conventional receiver / driver connection wiring 4). In FIG. 2, 1 is a clock ring, 5a is a clock input cell as a sequential circuit, L is a dedicated line, 8
Is a clock distribution cell.

FIG. 1 is a pattern diagram showing a semiconductor integrated circuit device as an embodiment of the present invention, which realizes the clock signal logic diagram shown in FIG. In FIG. 1, A is a clock input terminal to which an external clock signal a is input, A1 is an input buffer (input buffer cell), B is a control gate, 2 is a clock driver, 3 is a pre-driver, and 4 is a pre-driver 3. A pre-driver / driver connection line for connecting the output to the input of the clock driver 2, 1C is a clock signal line made of a second layer metal thicker than a normal signal line connected to the output of the clock driver 2, and 1A is a clock signal line 1C. A clock signal line made of a first layer metal connected through a through hole,
1B is a clock signal line made of a second layer metal connected to the clock signal line 1A through a through hole, 1D is a clock branch line made of a first layer metal wiring connected to the clock signal lines 1B and 1C through a through hole, 1E is a clock signal line formed by a second-layer metal wiring connected from the clock branch line 1D via a through hole, 5a is a sequential circuit such as a flip-flop, 5b is a combinational circuit, 6 is a power supply to the area of the internal cells 5a and 5b. A second-layer power supply line made of a second-layer metal to be supplied, and 7 is an input / output buffer area. The clock signal lines 1A and 1B form a ring-shaped wiring, and the clock signal line 1E connects the clock branch line 1D and the input / output terminal of the sequential circuit 5a. The clock signal lines 1A and 1B, the clock signal line 1C, the clock branch line 1D, and the clock signal line 1E form a clock signal line.

Next, the wiring method and operation of the embodiment of the present invention will be described. In the semiconductor integrated circuit device shown in FIG. 1, clock signal lines 1B and 1C are wired in advance similarly to the second-layer power supply wiring 6. Since the area where the clock signal lines 1B and 1C are wired is treated as an internal gate and a second layer power supply wiring prohibited area in the wiring program, it does not affect the normal signal line wiring by the wiring program. In addition, the wiring of the clock signal line 1A is also inscribed in the input / output buffer area 7 and a wiring area is reserved in advance and treated as a prohibited area for internal cell placement and a signal wiring prohibited area by the first layer metal. This does not affect the signal line wiring.

As shown in FIG. 1, a user arbitrarily designates a pin position A for inputting the external clock signal a. When the output of the input buffer A1 at the pin position A is input to the control gate (control circuit) B and the output of the control gate B is input to the pre-driver 3, the control gate B is automatically controlled by the placement and routing program. The wiring from the input buffer A1 to the control gate B and the wiring from the control gate B to the pre-driver 3 are also easily wired by a general wiring program. The clock branch line 1D needs to be thicker than a normal signal line in order to suppress skew, but the number of clock signal lines equal to the number of internal cell columns to be arranged is assigned to the first layer signal wiring channel.
Wiring to connect to 1B and 1C can be easily performed using a current commercial layout tool.
Also, the connection between the clock signal line 1E and the sequential circuit 5a can be easily wired by a commercially available layout tool. In FIG. 2, the output signal of the input buffer A1 is input to the pre-driver 3 via the control gate B.
The signal may be directly input to the pre-driver 3 without passing through the control gate B.

As described above, since a large number of sequential circuits 5a can be driven collectively by the clock driver 2 without any special program for clock signal wiring, skew of clock signals can be reduced. That is, since each clock signal line is arranged in a mesh, the resistance from the clock driver to the sequential circuit is reduced, and the skew of the clock signal is reduced.

〔The invention's effect〕

As described above, according to the present invention, a clock signal can be input to an input buffer at an arbitrary pin position, and an output signal of the pre-driver or the clock driver can be output directly or via a control gate constituted by internal cells. Since the configuration can be easily and automatically wired to the clock distribution cell constituted by a general wiring program, there is an effect that the system design is easy and a gate array with low clock skew can be obtained.

[Brief description of the drawings]

1 is a pattern diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention, FIG. 2 is a logic diagram showing the logic of a clock signal in the device of FIG. 1, and FIG. 3 is a pattern showing a conventional clock distribution. FIG. A: Clock input terminal, A1: Input buffer, B:
Control gates, 1A to 1C, 1E: clock signal line, 1D: clock branch line, 2: clock driver, 3: predriver, 4: predriver / driver connection wiring, 5a:
Sequential circuit, 5b combination circuit, 6 second-layer power supply wiring,
7 ... I / O buffer area.

Claims (1)

(57) [Claims] An input buffer cell for receiving a clock signal external to the chip and transmitting the clock signal to the inside of the chip; a pre-driver circuit for receiving a clock signal from the input buffer cell directly or via a control gate of the internal cell; At least one clock driver that receives an output of the pre-driver circuit and drives a sequential circuit described below, a clock signal line for connecting an output of the clock driver to the sequential circuit, and a plurality of clock signals connected to the clock signal line. A clock circuit, wherein the clock signal wiring is arranged in a ring-shaped wiring composed of a first-layer metal wiring and a second-layer metal wiring adjacent to the inner periphery of the input / output buffer area, and in an internal cell area. It runs adjacent to and parallel to the second layer power supply wiring, is connected to the output terminal of the clock driver, and is connected to the ring-shaped wiring. At least one second-layer metal wiring, and at least one first-layer metal clock branch connected to the second-layer metal wiring and the ring-shaped wiring, and are arranged in a grid. A semiconductor integrated circuit device characterized by the above-mentioned.