JPH02246354A - Master slice layout integrated circuit device - Google Patents

Abstract

PURPOSE:To increase signal terminals substantially by using a bonding pad for an input buffer circuit in the case where an input/output buffer cell is used as an output buffer circuit by arranging an input/output buffer cell row and a row of bonding pads formed along the buffer cell row while being mutually displaced at half pitches. CONSTITUTION:The rows of input/output buffer cells 1-3 and the rows of bonding pads 51-53 shaped along the rows are disposed while being mutually displaced at half pitches. Consequently, when two of output buffer circuits 41-43 are connected in parallel in order to improve the driving capacitance of the output buffer circuits 41-43, only one bonding pad for an output signal may be employed because the output terminals 71-73 of the output buffer circuits 41-43 are connected directly to one bonding pad such as 51, and other bonding pads such as 52 can be used for application except the output signal. The bonding pad is bonded with a GND power wiring 16, and employed for reducing the fluctuation of the voltage of the GND power wiring 16. Accordingly, outer leads, etc., can be utilized effectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gate array type master slice type integrated circuit device, and particularly to a bonding pad arrangement method thereof.

[Prior Art] A gate array type master slice type integrated circuit device (hereinafter referred to as a gate array) is a device in which basic cells consisting of a plurality of elements that can configure basic logic functions are arranged in a matrix in advance. This is an integrated circuit device in which various circuits are configured on a master board using a type-specific metallization mask to realize specific circuit functions.

The configuration of a general gate array will be explained using the drawings.

FIG. 5 is a plan view of the gate array. As shown in FIG. 5, in the center of the integrated circuit 100 there is an internal cell area 102.
is provided, and basic cells 101 are arranged in a matrix within the area. Outside the internal cell area 102,
Output buffer cells 1 for interfacing the logic signal level in the internal cell area 102 with other integrated circuit devices are arranged in a row, and further, the output buffer cells 1 are arranged in a row in the outer area of the integrated circuit chip. A row of bonding pads 51 are provided for connecting leads to the integrated circuit device along the row of traffic buffer cells.

In the internal cell area 102, various logic functions can be realized by using one or more basic cells 101. Alternatively, a circuit can be configured as an input/output buffer circuit, and some gate arrays have an ECL-TTL level conversion circuit here.

FIG. 6 is a logical block diagram for explaining the functions of the crowd buffer cell 1. In FIG. 6, on the input/output buffer cell 1, an input buffer circuit 21, an output buffer circuit 41, and a pre-buffer circuit #I31 for driving the output buffer circuit 41 are written in logical symbols. When this input/output buffer cell is used as an input buffer circuit, the bonding pad 51 and the input terminal 61 of the input buffer circuit 21 are connected by the wiring 10, and the output terminal 71 of the input buffer circuit 21 is connected to the internal cell area. Connected to the input terminal of the internal logic circuit. Further, when used as an output buffer circuit, the bonding pad 51 and the output terminal 91 of the output buffer circuit 41 are connected by the wiring 10, and the input terminal 81 of the pre-buffer circuit 31
is connected to the output terminal of the logic circuit in the internal cell area.

In this way, by selecting and using circuits prepared in advance according to the application, an input/output buffer cell at an arbitrary position can be easily made into an input buffer circuit or an output buffer circuit.

By the way, as the applications of gate arrays have expanded in recent years,
Requirements for output buffer circuits are also diversifying. That is, on the one hand, there is a case where a large-scale gate array is used and the set is configured with a relatively small number of components, and in this case, the output signal of the output buffer circuit of the gate array is connected to a relatively small number of other integrated circuits. The drive capability of the buffer circuit does not need to be very high because it is used to transmit data to a device.On the other hand, if the set is configured using a relatively small-scale gate array and standard IC, in this case Since the output signal of the output buffer circuit of the gate array is transmitted to many other ICs, high driving ability of the output buffer circuit is required. The driving ability of the output buffer circuit is determined roughly by the size of the output transistor, so improving the driving ability of the output buffer circuit will increase the input/output buffer area. Mounting a human output buffer will increase the area of the integrated circuit chip, and conversely, if the area of the integrated circuit chip is not changed, the number of human output buffers will decrease.

Therefore, when configuring a set with a small number of parts as described above, an output buffer circuit with such a high driving capacity is unnecessary, so the gate array is designed to be able to cope with either case. In order to achieve this, input/output buffer cells should be designed to have load driving capacity under boat fishing conditions, and if high driving capacity is required, an output buffer circuit should be configured for each adjacent traffic buffer cell. However, two output buffer circuits are connected in parallel to improve the driving ability of the output buffer circuit.

FIG. 7 is a plan view of the vicinity of the human output buffer cell when the output buffer circuit is configured in this manner. In FIG. 7, the output terminals of the output buffer circuits in the input/output buffer cells 1 and 2 are the first layer wiring 18b indicated by dotted lines,
19b to the vicinity of bonding pads 51 and 52 provided near the integrated circuit chip end 100a, through holes 18c and 19c, and second layer wiring 18.
a, 19a to bonding pads 51, 52. The output terminals of the two output buffer circuits are connected in parallel by connecting the bonding pads 51 and 52rWi with the second layer wiring 20a.

Attendance buffer cell 3, which is not used in the example of FIG.
A bonding pad 53 corresponding to the human output buffer cell 3 is provided in a region closer to the integrated circuit chip end 100a, and the highest potential power supply wiring for supplying the power supply voltage is provided above the human output buffer cells 1 to 3. (hereinafter referred to as Vcc power supply wiring) 17 and lowest potential power supply wiring (hereinafter referred to as GND power supply wiring) 16 are provided.

FIG. 8 is a block diagram showing the circuit in the plan view of FIG. 7 using logic symbols. 2
3. Pre-buffer circuits 31 to 33, output buffer circuit 4
1 to 43, and input terminals 61 to 63, 81 to 83 and output terminals 71 to 73, and 91 to 93, which are connection terminals between these circuits and the outside.

As shown in FIG. 8, the output signal inside the cell area is
The wiring 11 inputs the pre-buffer circuits 31.32 on the input/output buffer cell 1.2 in parallel via the input terminals 81.82, and the output signals of the pre-buffer allo paths 31.32 are input to the output buffer circuits 41.42, respectively. The output signals of output buffer circuits 41 and 42 are transmitted to bonding pads 51 and 52 via output terminals 91 and 92 and wiring lines 18 and 19, respectively. and bonding pad 5
1.52 is connected by a wiring 20.

By the way, when two output buffer circuits are connected in parallel in this way, the number of bonding pads, bonding wires, and external leads of the integrated circuit device that can be used is two.
However, since it is sufficient to use one set, normally only one set is used except for bonding pads. This tendency is caused by the fact that adjacent input/output buffer cells on an integrated circuit chip In the external lead of an integrated circuit device, a multi-bin PGA (Pin Grid)
This is particularly noticeable in Array packages and the like.

[Problems to be Solved by the Invention] In the conventional method described above, a number of sets of bonding pads, bonding wires, and external leads of an integrated circuit device in which output buffer circuits are connected in parallel handle the same signal. In some situations, one set of bonding pads, bonding wires and external leads of the integrated circuit is sufficient, the remaining bonding pads are only used to connect between the output terminals of the output buffer circuit, and the other bonding wires, 4A The external leads of integrated circuit devices were hardly used.

Therefore, in conventional integrated circuit devices, an unnecessarily large area is used for parallel connection of output buffer circuits, and external leads etc. are not used effectively.

[Means for Solving the Problems] A master slice type integrated circuit device according to the present invention includes a plurality of basic cells arranged in a matrix, and rows of basic cells arranged at a constant pitch outside an internal cell area where the basic cells are arranged. The device comprises a plurality of input/output buffer cells arranged in a shape, and a plurality of bonding pads arranged at the same pitch as the constant pitch provided outside the row of input/output buffer cells. The row of the crowd buffer cells and the row of the bonding pads are shifted by approximately 1/2 pitch.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view showing one embodiment of the present invention, and FIG.
The figure is a logical block diagram of its internal circuit, and in these figures, parts common to FIGS. 7 and 8 are given the same reference numerals.

In FIG. 1, the output terminal of the output buffer circuit of the input/output buffer cell 1.2 is the first layer wiring shown by the dotted line! 2b, and this wiring connects the human output buffer cell 1.
It is drawn out to the vicinity of the bonding pad 51 corresponding to the through hole 12C1, and is connected to the bonding pad 51 via the second layer wiring 12a of the through hole 12C1. The bonding pad 51 is arranged so that its center lies on a straight line extending the boundary between the input/output buffer cells 1 and 2 toward the integrated circuit chip end 100a. Also, the boundary line of the input/output buffer 2.3 is set in the direction of the integrated circuit chip end 100a (
A bonding pad 52 corresponding to the crowd buffer cell 2 is laid on the extended straight line, but this bonding pad does not need to be used for signal transmission.
It is connected to the GND i source wiring 16 by the second layer wiring 13a and is used for stabilizing the GND potential.

As shown in the logic block diagram of FIG. 2, in this embodiment, unlike the conventional example of FIG. On the other hand, the bonding pad 52 corresponding to the input/output cell 2 is connected to the GND power supply wiring via the wiring 13.

In this way, by arranging the rows of buffer cells and the rows of bonding pads provided along these rows with a 1/2 pitch shift from each other, the output power can be adjusted to improve the driving ability of the output buffer circuit. When two buffer circuits are connected in parallel, the output terminal of the output buffer circuit can be directly connected to one of the bonding pads, for example 51, so only one bonding pad is needed for the output signal.
Other bonding pads, for example 52, can be used for purposes other than output signals.In this embodiment, this bonding pad is connected to the GND power supply wiring 16, and the voltage of the GNDt source wiring due to the transient current of the output buffer circuit is This bonding pad is also connected to the VCC power supply wiring 17 to reduce the fluctuation of VCC.
It may also be used to stabilize the power supply potential.

Next, another embodiment of the present invention will be described with reference to FIG. This embodiment is different from the previous embodiments in that the bonding pad 52 is connected to the second layer wiring 14a, the 1-2 interlayer through hole t4c, and the first layer wiring 14 indicated by the dotted line.
This point is connected to the input terminal of the input buffer circuit on the input/output buffer cell 2 via the terminal b. The output terminal of the input buffer circuit is connected to the input terminal of the internal logic circuit.

FIG. 4 is a diagram showing the circuit in the plan view of FIG. 3 as a logic block. As shown in FIG. 4, the bonding pad 52 is connected to the input terminal of the internal logic circuit via the wiring 14, the input terminal 62, the input buffer circuit 22, the output terminal 72, and the wiring 15.

In this way, in this embodiment, by connecting the output buffer circuits in parallel, the remaining bonding pads are effectively used for the input buffer circuit.

Further, in this embodiment, since the output buffer cell 2 is used for both the input buffer circuit and the output buffer circuit, it is possible to achieve higher density of the integrated circuit device.

[Effects of the Invention] As explained above, in the present invention, the input/output buffer cell rows and the bonding pad rows provided along them are arranged with a 1/2 pitch offset from each other. According to the invention, when output buffer circuits are connected in parallel, for example, when two output buffer circuits are connected in parallel, the number of bonding pads used is one; In this case, if the third output buffer circuit is connected in parallel between the bonding pads, the number of bonding pads used is two, and the number of bonding pads used is always one less than the number of output buffer circuits. be able to. In order to prevent fluctuations in power supply voltage due to transient currents that tend to occur when output buffer circuits are used frequently, surplus bonding pads can be used to reinforce power supply wiring, or input/output buffer cells can be used as output buffer circuits. If it is used, it can be used for an input buffer circuit that is not normally used to substantially increase the number of signal terminals.

[Brief explanation of drawings]

1 and 3 are plan views showing embodiments of the present invention, FIGS. 2 and 4 are logical block diagrams for explaining FIGS. 1 and 3, respectively, and FIG. 7 are a plan view of the conventional example, FIG. 6 is a logical block diagram for explaining a part of FIG. 5, and FIG. 8 is a logical block diagram for explaining FIG. 7. It is. 1-3...I/O buffer cell, 10-15.18
~20...Wiring, 16...GND power supply wiring, 1
7-V cciE source wiring, 12b, 14b, 18
b, 19b... 1st M wiring, 12c, 14c, 1
8c, 19c ・-1-2 interlayer through hole, 12a
, 13a, 14a, 18a, 19a... second layer wiring,
21-23...input buffer circuit, 31-33.
...Pre-buffer circuit, 41-43... Output buffer circuit, 51-53... Bonding pad,
61~63.81~83...input terminal, 71
~73.91~93...output terminal, 100...collection M
Circuit chip, 100a... integrated circuit chip end,
101... Basic cell, 102... Internal cell area.

Claims (1)

[Claims] A plurality of basic cells arranged in a matrix, a plurality of input/output buffer cells arranged in rows at a constant pitch outside the internal cell area where the basic cells are arranged, and a plurality of input/output buffer cells arranged in rows at a constant pitch. In a master slice type integrated circuit device comprising a plurality of bonding pads arranged at the same pitch as the constant pitch provided along the outer side thereof, the row of input/output buffer cells and the row of bonding pads are A master slice type integrated circuit device characterized by a deviation of approximately 1/2 pitch.