KR19980065642A - Output pad arrangement method of semiconductor memory device - Google Patents

Abstract

The present invention relates to a method for arranging an output pad of a semiconductor memory device. According to an aspect of the present invention, there is provided a method of arranging an output pad, comprising: a memory cell array portion, a peripheral circuit portion, and a plurality of output pads for outputting internal signals and supplying power to the outside; An output pad including a pad, a driver transistor, a field transistor, and a control circuit, for positioning the control circuit between the pad and the pad in the X direction and the driver transistor between the pad and the pad in the Y direction. It is characterized by. Therefore, in the method of arranging the output pads according to the present invention, when the pads are arranged in two layers, the area of the chip width direction, that is, the Y direction is reduced by disposing the pull-up transistor and the pull-down transistor of the driver transistor between the up and down directions of the pad. Can be. In addition, input capacitance can be reduced by sharing the capacities of the pull-up and pull-down transistors.

Description

Output pad arrangement method of semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for arranging output pads in a semiconductor memory device, and more particularly, to an output pad arranging method that can reduce chip area when two pads are disposed.

As semiconductor technology advances, memory capacities increase and processing speeds are rapidly evolving, but users do not require the package to grow larger than the package currently in use. To meet the needs of these users, semiconductor chip designers take various methods to reduce the chip area. The representative one is to reduce the chip area by optimizing the layout and simulation, and the design rule in the semiconductor manufacturing process. To reduce the rule. However, there is a limit to reducing chip area by optimizing layout and simulation, and minimizing chip area is a challenge for designers. In DRAM, chip area can be divided into memory cell, peripheral circuit, and pad area. Looking at the current semiconductor manufacturing process, memory cell and peripheral circuit areas are reduced in size due to continuous process development. However, the pad area is hardly reduced. On the contrary, the trend of memory devices is to multiply, which means that the number of pads increases. However, as the number of operation bits of the memory device increases, the number of output pads also increases in proportion to the pads, thereby increasing the ratio of the area occupied by the output pads to the total chip area. The configuration of the output pads can be divided into pads, output drivers, and control circuit layers. Until now, the layout of the output pads was based on arranging pads of the entire chip in a single line.

1 is a view showing a layout view of a conventional output pad.

Referring to FIG. 1, in the conventional output pad, control circuits 2a and 2b and field transistors 3a and 3b related to ESD are disposed on the right and left sides of the pads 1a and 1b, respectively. Pull-up transistors 4a and 4b and pull-down transistors 5a and 5b are disposed on the upper and lower sides based on 1a and 1b.

In the arrangement of the conventional output pad illustrated in FIG. 1, when the pads 1a and 1b are arranged in a single line, the space in the chip width direction is reduced since the free space around the pad can be utilized to the maximum. However, when the pads are arranged in two layers, the area of the chip increases in the width direction.

Accordingly, an object of the present invention is to provide a method for arranging an output pad of a semiconductor memory device which can reduce the chip area and reduce the chip area when the pad is disposed in two layers.

1 is a view showing a layout of a conventional output pad

2 illustrates a layout view of an output pad according to an exemplary embodiment of the present invention.

An output pad arrangement method according to the present invention for achieving the above object, the output of a semiconductor memory device having a memory cell array portion, a peripheral circuit portion, and a plurality of output pads for outputting an internal signal to the outside and supplying power In the pad arrangement, the output pad includes a pad, a driver transistor, a field transistor, and a control circuit, and the control circuit is positioned between the pad and the pad in the X direction and between the pad and the pad in the Y direction. The driver transistor is positioned.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a layout view of an output pad according to an exemplary embodiment of the present invention.

The pads arranged in two layers must have some distance due to the area of the peripheral circuit, and the output pads need a driver transistor, a field transistor, and a control circuit. 2, since the pads 6a and 6b are arranged in two layers, the control circuits 7a and 7b are disposed in the X direction and the driver transistors are disposed in the Y direction in the space therebetween. The pull-up transistors 8a and 8b and the pull-down transistors 9a and 9b of the driver transistors are arranged in the X direction to share the input junction stage of the two transistors.

Therefore, in the method of arranging the output pads of the semiconductor memory device according to the present invention, when the pads are arranged in two layers, the pull-up transistors and pull-down transistors of the driver transistors are disposed between the pads in the vertical direction, ie, in the chip width direction, that is, in the Y direction. Can reduce the area. In addition, input capacitance can be reduced by sharing the capacities of the pull-up and pull-down transistors.

Claims (2)

In an output pad arrangement of a semiconductor memory device having a memory cell array portion, a peripheral circuit portion, and a plurality of output pads for outputting internal signals and supplying power to the outside, the output pads may include pads, driver transistors, and field transistors. And a control circuit, wherein the control circuit is positioned between the pad and the pad in the X direction, and the driver transistor is positioned between the pad and the pad in the Y direction. In an output pad arrangement of a semiconductor memory device having a memory cell array portion, a peripheral circuit portion, and a plurality of output pads for outputting internal signals and supplying power to the outside, the output pads may include pads, driver transistors, and field transistors. And a control circuit, positioning the control circuit between the pad and the pad in the X direction and the driver transistor between the pad and the pad in the Y direction, the pull-up transistor and the pull-down transistor of the driver transistor. Output pad arrangement method characterized in that to arrange in parallel to the Y direction.