KR100207493B1 - Semiconductor memory device having memory cell array control circuit which the layout was developed - Google Patents

Abstract

The present invention relates to a semiconductor memory device having improved arrangement relationship of a memory cell array control circuit. The present invention provides a memory cell array, a sense amplifier block having one end of sense amplifiers for sensing data stored in the memory cell array in a row adjacent to the memory cell array, and the sense amplifier block adjacent to the sense amplifier block. A semiconductor memory device having a connection portion at which one end of a circuit for controlling a circuit is disposed and a row decoder disposed at a horizontal end of the memory cell array to control the memory cell array, comprising: a circuit for controlling the sense amplifier block; Some NMOS transistors of most transistors are disposed in the connection portion, and some PMOS transistors are distributed in an area adjacent to the row decoder and in an area opposite the row decoder as a row termination of the memory cell array, thereby improving integration.

Description

Semiconductor memory device with improved arrangement of memory cell array control circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to an arrangement of MOS transistors of an equalizing transistor control driver for a sense amplifier of a highly integrated semiconductor memory device.

With the rapid spread of computers, the demand for semiconductor memory devices with large memory capacities is increasing. In order to increase the memory capacity in a limited size semiconductor chip, the integration degree of the semiconductor chip must be increased. This requires efficient arrangement of semiconductor devices.

1 is a layout view of a memory cell array of a general semiconductor memory device. Referring to the structure of the figure, a plurality of 256 [KBit] memory cell arrays 11, sense amplifiers 13 disposed on the upper and lower ends of the memory cell arrays 11, and the memory cell arrays ( Sub wordline drivers 15 disposed on the left and right sides of the substrate 11, connections 17 disposed between the memory cell arrays 11, and the memory cell arrays 11. A column decoder 18 disposed at the lower end of the circuit and a row decoder 19 disposed at the right side of the memory cell arrays 11 are formed.

The connections include control drivers for equalizing the memory cell array, circuits for controlling the ISO transistors of the sense amplifier block that isolates the memory cell array, LAB drivers for enabling the N-type sense amplifiers, and P-type sense. There are a LA driver that enables the amplifier, a transfer transistor that connects the IO node of the sense amplifier block and the GIO line, and a PXI circuit that controls the sub wordline driver.

2 is a layout view of MOS transistors of an equalizing transistor control driver for a sense amplifier of a conventional semiconductor memory device. PMOS transistors 25 of the control drivers are disposed in the odd connectors 21, and NMOS transistors 27 of the control drivers are disposed in the even connectors 23. One sense amplifier is connected to each connection, so that the sense amplifiers 29 are arranged as many as the connection. In addition, no elements are disposed on the edge 201 of the semiconductor chip 20 and the outer side 205 of the row decoder 203 and the empty space remains.

In order to improve productivity and reduce costs, semiconductor chips must be more efficient. Moreover, as integration increases, space for memory peripheral circuits becomes increasingly scarce. As a result, the area of the sense amplifier and sub wordline driver is reduced, and the connection area is also reduced. This makes it impossible to place all of the control drivers that control the sense amplifiers and sub-wordline drivers in the connection.

As described above, as the degree of integration increases due to an increase in memory capacity, a problem arises in that all transistors of the control drivers for the sense amplifier cannot be disposed in the connection portion.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor memory device capable of improving the degree of integration without degrading characteristics of each device in disposing control drivers for a sense amplifier of a memory cell array.

1 is a layout view of a memory cell array of a general semiconductor memory device.

2 is a layout view of MOS transistors of an equalizing transistor control driver for a sense amplifier of a conventional semiconductor memory device.

3 is a layout view of MOS transistors of an equalizing transistor control driver for a sense amplifier of a semiconductor memory device according to the present invention.

In order to achieve the above object, the present invention provides a memory cell array, a sense amplifier block in which one end of sense amplifiers for sensing data stored in the memory cell array are arranged adjacent to the memory cell array in a row, and the sense amplifier block. 10. A semiconductor memory device having a connection portion having one end of a circuit for controlling the sense amplifier block adjacent thereto and a row decoder disposed at an end of a row of the memory cell array for controlling the memory cell array. Some NMOS transistors of the MOS transistors constituting the controlling circuit are disposed in the connection portion, and some PMOS transistors are distributed in an area adjacent to the row decoder and in an area opposite the row decoder as a row termination of the memory cell array. Peninsula It is to provide a sieve memory device.

Preferably, an area opposite to the row decoder is an area between an edge of a semiconductor chip on which the memory cell array is disposed and the connection part, and the connection part has MOS transistors constituting a circuit for controlling the sense amplifier block. Only one NMOS transistor is placed.

According to the present invention, the degree of integration can be improved without degrading the characteristics of the control drivers for the sense amplifiers of the memory cell array.

Hereinafter, the present invention will be described in detail through examples.

3 is a layout view of MOS transistors of an equalizing transistor control driver for a sense amplifier of a semiconductor memory device according to the present invention. The semiconductor memory device shown in FIG. 3 includes a plurality of connections 31 disposed on the semiconductor chip 30, sense amplifier blocks 39 disposed at lower ends of the connection portions, and a right side of the connection portions 31. The row decoder 37 is arranged, the row decoder adjacent area 305 on the right side of the row decoder 303 and the chip edge 301 on the left side of the connections 31.

NMOS transistors 35 of the control drivers controlled by the equalizing signals EQi, EQiB, EQj, and EQjB are disposed at each of the connections 31, and adjacent to the chip edge 301 and the row decoder. In the region 305, PMOS transistors 33 of the control drivers are arranged. The NMOS transistors are responsible for equalizing i block arrays or j block arrays of sense amplifiers. An equalizing power source EVcc is used as a power source of the PMOS transistors 33.

Only one NMOS transistor of the control drivers is placed in each connection, and the PMOS transistors of the control drivers are distributed in the peripheral area, i.e., the chip edge and the row decoder adjacent area, so that the density increases and the area of the connections is reduced. Devices can be placed in the same area without

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.

As described above, according to the present invention, chip usage efficiency is improved by distributing PMOS transistors of the control drivers in the chip edge and the row decoder region. Therefore, even if the memory capacity is increased and the connection area is reduced, all the control drivers for the sense amplifier of the memory cell array can be arranged.

Claims (3)

A memory cell array, one end of sense amplifiers sensing data stored in the memory cell array, and a sense amplifier block disposed adjacent to the memory cell array in a row, and controlling the sense amplifier block adjacent to the sense amplifier block. A semiconductor memory device having a connection portion at which one end of a circuit is disposed and a row decoder disposed at a row end of the memory cell array to control the memory cell array. Some NMOS transistors of the MOS transistors constituting the circuit for controlling the sense amplifier block are disposed in the connection portion, and some PMOS transistors are located adjacent to the row decoder and opposite the row decoder as a row termination of the memory cell array. A semiconductor memory device, wherein the semiconductor memory device is distributed in a region. The semiconductor memory device of claim 1, wherein an area opposite to the row decoder is an area between an edge of a semiconductor chip on which the memory cell array is disposed and the connection portion. The semiconductor memory device of claim 1, wherein only one NMOS transistor of each of the MOS transistors constituting the circuit for controlling the sense amplifier block is disposed in the connection unit.