JPH0447464B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory cell arrangement of a storage circuit of a read-only memory (ROM) integrated circuit. Among other things, the present invention provides a read-only memory integrated circuit (hereinafter referred to as series-parallel connection) in which the memory circuit portion is constructed by serial and parallel connections (hereinafter referred to as series-parallel connections) of memory elements (hereinafter referred to as memory cells) consisting of MOS transistors. (hereinafter referred to as ROM).

[Prior Art and Problems to be Solved by the Invention] The recent development of large-scale integrated circuits (LSI) has been remarkable, and remarkable progress has been made in increasing the performance of microprocessors and increasing the speed and density of semiconductor memories.
Under these circumstances, many microprocessor-applied products have been developed, and as a result, there has been a demand for smaller, larger-capacity ROMs.

The configuration of a typical ROM is shown in FIG.
In the figure, 1 is an address signal input terminal, 2 is an address buffer, 3 is an address column decoder, 4 is an address row decoder, 5 is a memory cell matrix array section (hereinafter referred to as cell array), and 6 is an address signal input terminal. Column selector and sense up section, 7 is output buffer, 8
is the output terminal of the output signal.

Among these, the part that occupies the most area of the ROM chip is the cell consisting of memory cells.
This is array 5. Therefore, when increasing the memory capacity, it is required to reduce the area of this cell array.

Conventional ROM basically uses address signals as
The ROM chip is divided into two parts and decoded into a row selection signal and a column selection signal, and the 1-bit data fixed in the memory cell MOS transistors placed at each intersection of the matrix of the cell array is sent to the row selection signal and column selection signal. A method is used in which selection is performed using a selection signal.

FIG. 2 shows a cell array consisting of one basic memory cell and one contact portion. In the figure, 1 is the metal that becomes the readout line (column line), 2 is the polysilicon that is the row selection line, 3 is the contact part,
4 is a diffusion layer, 6 is a field portion, and 5 is a memory cell size. In this cell array, one contact portion is used for each memory cell, so the number of contacts with the same capacity as the memory cells is required, and the area of the cell array is large.

FIG. 3 shows a case where two memory cells are connected in parallel to one contact. In the figure, 1 is the metal that will be the readout line (column line), 2 is the polysilicon that will be the row selection line, 3 is the contact part, 4 is the diffusion layer, 6 is the field part, and 5 is the memory cell size. It shows. This cell array is
The area of the contact portion in one memory cell size is half that of the cell array of FIG. 2, and the area of the cell array is smaller than that of FIG. Furthermore, since one memory cell MOS transistor is connected in parallel to the contact, the access time is fast. However, memory
It has the disadvantage that half the number of contacts as the number of cell capacities is required, and the chip area is still large.

On the other hand, FIG. 4 shows a case where memory cells are connected in series to one contact. In Figure 4, 1 is the metal that will be the readout line (column line), 2 is the polysilicon that will be the row selection line, 3 is the contact part, 6 is the field part, and 5 is the memory cell size. .

The number of series-connected memory cell MOS transistors is generally 2 ⁿ stages (n=1,
2, 3, ...), and the area occupied by the contact portion for one memory cell size is 1/2 ⁿ . Therefore, if the number of series stages is increased, the area occupied by the contact portion can be almost ignored relative to the memory cell size, and this series connection method has a smaller memory cell size than the parallel connection method shown in FIG. The smaller size allows large amounts of ROM data to be integrated at high density. However, it has the disadvantage that the access time depends on the number of series stages of MOS transistors, and becomes slower as the number of series stages increases.

The present invention solves the above-mentioned drawbacks of the conventional ROM, and provides a ROM memory cell array that can increase the density of the memory cell array, reduce the chip size, and increase access time. It is something to do.

[Means for Solving the Problems] The present invention provides a read-only memory integration in which a plurality of memory cell groups each having a plurality of memory cell MOS transistors and a selection MOS transistor connected in series are arranged in a matrix to form an array. In the circuit, the array is configured of four memory cell groups as one unit block, and the four memory cell groups are selected by the selection MOS transistors and coupled to a common wiring, and the block is configured as described above. It has first, second, third, and fourth memory cell groups as four memory cell groups, and the first and second memory cell groups are diffused to form the MOS transistors connected in series. the third and fourth groups of memory cells are arranged in a second column adjacent to the first column, the third and fourth groups of memory cells are arranged in a second column adjacent to the first column to form the MOS transistors connected in series; two memory cell groups of the first and third memory cell groups and two memory cell groups of the second and fourth memory cell groups;
Each of the memory cell groups includes the memory cell
A plurality of row selection wirings for selecting MOS transistors are shared in common, and two group selection wirings for selecting the memory cell group are shared in common and are arranged to extend in the row direction of the array. The memory cell MOS transistors are formed in the intersection areas of the row selection wiring and the first and second columns, respectively, and the group selection wiring and the first and second columns are arranged to extend in the row direction of the array. The selection MOS transistors are formed in the intersection regions of two columns, and each of the diffusion layers forming the MOS transistors connected in series of the first, second, third, and fourth memory cell groups is One end forms a common diffusion layer;
It is characterized in that it is connected to the common wiring made of metal through one contact hole formed in the common diffusion layer.

[Example] Fig. 5 shows the cells and cells of the serial-parallel ROM according to the present invention.
It is an array.

In the figure, 1 is a metal (common wiring) that becomes a readout line (column line), 2 and 15 are polysilicon (row selection wiring) that become row selection lines for selecting memory cell MOS transistors, 3 and 4 is polysilicon (group selection wiring) that serves as a group selection line for selecting a memory cell group of memory cell MOS transistors connected in series, 5 to 9 are diffusion layers of MOS transistors, and 10 and 11 are contact portions. (contact hole), 12 is a depletion type MOS transistor (selection MOS transistor), 13 is an enhancement type MOS transistor (selection MOS transistor), and 13 is an enhancement type MOS transistor (selection MOS transistor).
(transistor), 14 indicates a field section.

In FIG. 5, memory cell MOS transistors are formed in the intersection regions of diffusion layers 6, 7, 8, 9 formed in the column direction and polysilicon 2, 15 arranged in the row direction; A selection MOS is placed in the intersection area with polysilicon 3 and 4 to be placed.
A transistor is formed. Thereby, eight memory cell MOS transistors are connected in series,
Further, two selection MOS transistors are connected in series to form four memory cell groups. One end of the diffusion layers 6, 7, 8, and 9 of this memory cell group constitutes a common diffusion layer at a contact portion 10, and is connected to the contact 10 in parallel. In other words, FIG. 5 shows a ROM cell array with 4 parallel and 8 stages connected in series.

a diffusion layer 6 connected in parallel to the contact 10;
The memory cell groups formed at 7, 8 and 9 are selected by group selection lines 3 and 4. For example, for selection
If the MOS transistor 12 is a depletion type and the selection MOS transistor 13 is an enhancement type, when the group selection line 3 is set to the selected state,
Since the group selection MOS transistor 13 on the diffusion layer 6 side is off and the group selection MOS transistor 13 on the diffusion layer 7 side is on, the memory cell group on the diffusion layer 7 side is connected to the power source 5. It will be in the selected state. Therefore, when the row selection line 15 and the group selection line 3 are selected, the memory cell group formed in the diffusion layer 7 is selected and connected to the contact 10.

Next, we will discuss memory and cell arrays.

The channel width (corresponding to the width of each diffusion layer) and metal width of the MOS transistors that make up the memory cell are equal, but the metal width of the contact part is wider than the channel width because a contact hole is made there. Become. Considering the row spacing of the cell array, the channel width can be reduced, but
It is difficult to make the contact portion small because it requires a margin for alignment between the diffusion layer and the metal, and the spacing is determined by the metal width of the contact portion. This also applies to Figures 2, 3, and 4 of the conventional example.
The same applies to FIG. 5 of the present invention. In the conventional example, only one diffusion layer was formed in the column direction for the width of one contact portion, resulting in wasted space. However, in the present invention, two diffusion layers are arranged adjacent to each other in the column direction with respect to the width of one contact portion, so that the space of the cell array can be efficiently utilized to achieve high density.

In addition, in Figure 5, 4 x 8 with 4 parallel 8 stages connected in series
One contact exists for each MOS transistor, and the area occupied by the contact portion is extremely small relative to the memory cell size. In particular, as shown in Figure 5, the area of the memory cell size can be reduced without increasing the number of series stages.
Both faster access time and higher density can be achieved.

Furthermore, the conventional example and the present invention have the same capacity (the same number of memory cell MOS transistors).
Since the number of contacts required for the ROM is much smaller in the present invention, the area of the cell array can be made very small, resulting in a very dense cell array.

In addition, the number of series stages of memory cells required to configure a ROM with the same area as the conventional example shown in FIG.
If the number in Figure 4 is 16, the number in Figure 5 of the present invention is 8 (however, since two selection MOS transistors are added, the actual number is 10), and the number of series stages is reduced, making the access time faster. .

Furthermore, the present invention is characterized in that four memory cell groups formed in two adjacent columns are connected to one contact.
For comparison, let us consider, for example, a configuration in which eight memory cell groups are connected. Since the memory cells are formed above and below the four columns, the common diffusion layer in which the contacts are formed has a width of four diffusion layers. Furthermore, four selection MOS transistors are connected in series to each memory cell group. In this case, compared to the present invention, the number of series stages increases and the parasitic capacitance of the contact portion increases, so the access time becomes slower. On the other hand, the area does not become much smaller. Therefore, as in the present invention, 2
The configuration in which four groups of memory cells in two adjacent columns are connected to one contact is the optimal memory cell arrangement for achieving high density cell arrays without slowing down access time.

[Effects of the Invention] As described above, by using the series-parallel connected memory cell array according to the present invention, a ROM cell array with a large capacity can be realized without slowing down the access time.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a block diagram of a general ROM. 1...Address signal input terminal, 2...Address buffer, 3...Address string decoder, 4...
Address row decoder, 5...Memory cell matrix arrangement section, 6...Column selector and sense amplifier section, 7...Output buffer, 8...Output signal output terminal, Figure 2 shows each memory cell. contact 1
FIG. 2 is a diagram illustrating a basic memory cell array. 1...Metal (column line), 2...Polysilicon (row selection line), 3...Contact section, 4...Diffusion layer, 5...Memory cell size, 6...Field section. FIG. 3 is a diagram showing a memory cell array in which two memory cells are connected in parallel to one contact. 1...Metal (column line), 2...Polysilicon (row selection line), 3...Contact section, 4...Diffusion layer, 5...Memory cell size, 6...Field section. FIG. 4 is a diagram showing a memory cell array in which memory cells are connected in series to one contact. 1...Metal (column line), 2...Polysilicon (row selection line), 3...Contact section, 4...Diffusion layer, 5...Memory cell size, 6...Field section. FIG. 5 is a diagram showing a series-parallel memory cell array. 1... Metal (column line), 2, 15... Polysilicon (row selection line), 3, 4... Polysilicon (memory cell group selection line), 5... Diffusion layer (source side), 6, 7, 8, 9...diffusion layer, 10, 11...
...Contact part, 12...Depression type MOS
Transistor (MOS transistor for selection), 13
...Enhancement type MOS transistor (selection MOS transistor), 14...Field section.

Claims (1)

[Scope of Claims] 1. A read-only memory integrated circuit in which a plurality of memory cell groups each having a plurality of memory cell MOS transistors and a selection MOS transistor connected in series are arranged in a matrix to form an array, wherein the array comprises four memory cell groups. The memory cell group is configured as one unit block, and the four memory cell groups are selected by the selection MOS transistor and connected to a common wiring, and the block is configured as the four memory cell groups. first, second, third, and fourth memory cell groups, wherein the first and second memory cell groups are connected in series, and a diffusion layer for forming the MOS transistor is connected to the first memory cell group in the array. the third and fourth memory cell groups are each arranged in a second column adjacent to the first column, and diffusion layers for forming the MOS transistors are connected in series; two memory cell groups, the first and third memory cell groups; and two memory cell groups, the second and fourth memory cell groups.
Each of the memory cell groups includes the memory cell
A plurality of row selection wirings for selecting MOS transistors are shared in common, and two group selection wirings for selecting the memory cell group are shared in common and are arranged to extend in the row direction of the array. The memory cell MOS transistors are each formed in an intersection region of the row selection wiring and the first and second columns,
The selection MOS transistors are formed in the intersection areas of the group selection wiring extending in the row direction of the array and the first and second columns, and the selection MOS transistors are formed in the first, second, third, and third columns. One end of each of the diffusion layers forming the series-connected MOS transistors of the fourth memory cell group forms a common diffusion layer;
A read-only memory integrated circuit, characterized in that it is connected to the common wiring made of metal through one contact hole formed in the common diffusion layer.