KR100206704B1 - Method of forming the array of semiconductor memory device - Google Patents

Abstract

The present invention relates to a semiconductor memory device, and an object of the present invention is to provide a method of configuring an array of semiconductor memory devices capable of suppressing current consumption while achieving high integration. According to an aspect of the present invention, there is provided an array configuration method of a semiconductor memory device including a plurality of subarrays having a plurality of memory cells arranged in a matrix form of rows and columns, and a plurality of banks including the subarrays, Arrays of the plurality of sub-arrays included in at least one of the banks and the remaining second banks are different from each other.

Description

Method for configuring an array of semiconductor memory devices

The present invention relates to a method of configuring a memory cell array disposed in a semiconductor memory device.

Generally, as the semiconductor memory device begins to be developed, a technique for storing a large amount of information on a small area has been developed. High integration through miniaturization due to the development of process and shortening of input / output time by improvement of transistor performance have been achieved. In design aspect, high integration and shortening of access time have been achieved through new circuit implementation and new layout method. As a result of such high integration, initially, the area occupied by the peripheral circuit among the area of the memory cell array and the area of the peripheral circuit in the semiconductor memory device was large, but the area occupied by the memory cell array gradually increased. As this high integration progresses, the increase in the package size does not increase in proportion to the degree of integration. Accordingly, it is a major concern to achieve high integration and low power consumption according to new circuit technology, configuration method, and new configuration method.

FIG. 1 is a view showing the arrangement of a memory cell array according to an embodiment of the prior art, and FIG. 2 is a specific configuration diagram of the sub-array B1 shown in FIG.

1 is a configuration of a 128 cell / bit line or a 128 cell / bit line out of a 256 cell / bit line configuration which is mainly adopted in a semiconductor memory device. This refers to the number of cells connected to one bit line in the memory cell array.

In the array configuration of FIG. 1, the memory cell array is largely divided into four banks 101 and 104, and each of the banks 101 and 104 is again composed of a plurality of subarrays B1B16. Such an array configuration can be modified differently depending on the degree of integration. In addition, the data in each sub-array B1B16 is accessed by the system control signal. Each of these subarrays B1B16 has a bit line sense amplifier area.

When the size of each of the subarrays B1B16 is m (the number of word lines WL in the row direction) × N (the number of bit lines BL in the column direction), the size of the m has a great influence on the characteristics of the semiconductor memory device . As shown in FIG. 2, the sub-array B1 includes m word lines and N bit line pairs. This configuration is a typical example of a folded bit line.

Therefore, m / 2 cells are connected to one bit line. As the semiconductor memory device becomes highly integrated, it is effective to reduce the memory cell array occupying the largest area in the chip in order to reduce the chip size. As a result, when the sub-arrays B1B16 are configured to have 128 cells / bit lines as shown in FIG. 1, the number of bit line sense amplifier areas is increased, which leads to an increase in chip size. In addition, when the sub-arrays are configured to have 256 cells / bit lines, eight sub-arrays are required, which is superior to the 128 cells / bit line in terms of reducing the chip size, but a specific word line is selected Information stored in the cell is applied to the bit line and the bit line sense is performed through the bit line sense amplifier, so that the parasitic capacity of the bit line is increased and the array current is increased. Therefore, as the chip becomes highly integrated, a reduction in the chip size and a method of suppressing the current consumption occurring in the chip operation are becoming big problems.

For example, a memory cell array of 16M diram can be divided into 4096 word lines (A0A11, 12 row addresses, Where N is the number of addresses) and 4096 columns (A0A11, 12 column addresses, , Where N is the number of addresses and wherein one column is a pair of bit lines), such a memory cell array is a bit line sense amplifier for sensing data stored in a memory cell after a particular word line is selected Area. In order to ensure the characteristics of the bit line sense amplifier, the memory cell array is divided into a plurality of banks. When the configurations of the banks 101 and 104 are adopted as the configuration of the 128 cells / bit line, the number of the subarrays B1B16 in the banks 101 and 104 is 16 and the number of the bit line sense amplifiers is 17 . When the configuration of the banks 101 and 104 is adopted as the configuration of 256 cells / bit lines, there are eight sub-arrays in the memory cell array blocks 101 and 104 (not shown) Since the area of the bit line sense amplifier is nine, it is advantageous in terms of chip size rather than the structure of the 128 cell / bit line. However, the current consumed in the operation of the bit line sense amplifier after the word line is enabled is increased. Briefly, the reason for this is limited to a case where the subarray has a configuration of 128 cells / bit line or 256 cell / bit line. In both cases, the number of bit line sense amplifiers enabled when a specific word line is selected is 4096 Do. Here, the case of the redundant cell will be omitted. However, the parasitic capacitance per bit line in both cases is different. That is, the parasitic capacitance of the bit line in the sub-array is doubled as compared with the case of the configuration of the 256-cell / bit line of 128-cell / bit line. Therefore, in the bit line sensing operation, the current consumption for shifting the bit line to the ground voltage VSS and the power supply voltage VCC (referred to as a high level or a restore level) becomes much larger in the case of the 256 cell / bit line. Such current consumption is becoming a big problem as high integration is achieved.

Therefore, an object of the present invention is to provide a method of configuring an array of semiconductor memory devices capable of suppressing current consumption while achieving high integration.

It is another object of the present invention to provide a method of constructing an efficient memory cell array.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows an array constructed in accordance with a prior art embodiment;

Fig. 2 is a schematic view showing the arrangement of the array block shown in Fig. 1. Fig.

Figure 3 shows an array constructed in accordance with an embodiment of the present invention.

Fig. 4 is a schematic view showing the arrangement of the array block shown in Fig. 3; Fig.

According to an aspect of the present invention, there is provided a semiconductor memory device including a plurality of subarrays having a plurality of memory cells arranged in a matrix of rows and columns, and a plurality of banks including the subarrays, Wherein the number of the first sub-arrays of the first banks and the number of the second sub-arrays of the second banks are different from each other.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. It should be noted that the same components and parts of the drawings denote the same reference numerals as far as possible.

In order to explain the present invention, M and m represent the number of word lines per memory cell array block, and N represents the number of bit lines. That is, M represents 512 for a 256-cell / bit line, and m represents 256 for a 128-cell / bit line.

FIG. 3 is a layout diagram of a memory cell array constructed in accordance with an embodiment of the present invention, and FIG. 4 is a view showing a schematic configuration of a sub-array B1 of the sub-arrays B1 to B16 shown in FIG.

Referring to FIG. 3, the arrangement of the memory cell array and the bit line sense amplifier region is the same as that of the prior art. However, the biggest difference is that the number of word lines WL in the subarrays B1 to B16 is different for the banks 101 to 104. [ The operation description will be described by using 16M DRAM as an example.

In the case of a 16M DRAM, it typically consists of four banks, each consisting of 4096 word lines and 1024 bit line pairs. In the embodiment of the present invention, the banks 101 and 102 arranged on the left side of the chip are composed of 256 cells / bit lines, and the banks 103 and 104 arranged on the right side of the chip have 128 cells / Bit lines. That is, the banks 101 and 102 are divided into eight sub-arrays B1 to B8 and have nine sense amplifier regions, and the banks 103 and 104 are divided into sixteen sub-arrays B1 B16 and has 17 sense amplifier areas.

Therefore, the chip size is larger than that in the case where the entirety of the banks 101 to 104 is composed of 256 cells / bit lines, but is smaller than that in the case of 128 cells / bit lines. In general, when a chip is enabled, one or two word lines in the banks 101 to 104 are simultaneously activated. Therefore, in terms of the operation current, the total of the banks is smaller than that of 256 cells / bit lines, which is larger than that of 128 cells / bit lines. That is, assuming that the array current in the case where the entire banks are composed of 256 cells / bit lines is 1, the array current in the case where the entire banks are composed of 128 cells / bit lines is 1/2, Designed as in the example, the array current is 3/4. As a result, the present invention enables middle selection between 128 cells / bit line and 256 cell / bit line in terms of array current and chip size. In addition to the embodiments of the present invention, a chip having the characteristics of the middle of 128 cells / bit line and 256 cell / bit line may be considered as the entirety of the banks as 192 cells / bit lines. However, since the coding is complicated, Hard. However, in the case of the embodiment of the present invention, the circuit implementation is simple and has the above-described effects.

As described above, according to the present invention, there is an advantage that current consumption can be suppressed while achieving high integration.

Claims (6)

A method of configuring an array of semiconductor memory devices having a plurality of subarrays having a plurality of memory cells arranged in a matrix of rows and columns and a plurality of banks including the subarrays, Wherein the number of each of the sub-arrays included in at least one of the first and second banks is differently set. 2. The method of claim 1, wherein the number of sub-arrays in the first banks is half of the number of sub-arrays in the second banks. 3. The method of claim 2, wherein each of the first banks and the second banks comprises the same number of rows and columns. 3. The method of claim 2, wherein the number of memory cells connected to each column of subarrays in the first banks and the number of memory cells connected to each column of subarrays in the second banks differ from each other. How to configure. A method for configuring an array of semiconductor memory devices having first, second, third, and fourth banks each including a plurality of subarrays having a plurality of memory cells arranged in a matrix form of rows and columns, Wherein the number of subarrays in the first and second banks is one half of the number of subarrays in the third and fourth banks. 6. The method of claim 5, wherein the subarrays in the first banks are connected to 256 memory cells in each column, and the subarrays in the second banks are connected to 128 memory cells in each column How to configure the array.