JPS6386186A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the cell area and to contrive to form a high integration a dynamic RAM possible by separating a raw decoder word line driving circuit into two systems and arranging them on both ends of a cell array. CONSTITUTION:A row decoder and word line driving circuit 4 is separated into two systems and arranged alternately on both ends of the work line 2 of a memory cell 1. By this constitution, consistency is given to the layout of the circuit 4 the contrivance to attain high integration can be realized even if the cell area is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor memory device, a patent, and a dynamic memory.

(Prior art) In a semiconductor memory device that integrates transistors (MOS),
In particular, mass production of 1M bit dynamic RAM (hereinafter referred to as DRAM) having a memory cell with one transistor and one capacitor has already begun. Furthermore, prototype production of a 4Mbit DRAM that integrates more than 8 million microscopic elements with a minimum processing size of 1 μm or less has begun. The reason behind this high degree of integration is the reduction in memory cell area. In cells using conventional planar capacitors, as the cell area is reduced, it is difficult to accumulate a sufficient amount of charge. A so-called trench type cell has been proposed. On the other hand, regarding the cell layout, a folded bill line method with a high noise margin is adopted.

In this configuration, as shown in FIG. 3, bit line pairs (BL, BL) on which signals from memory cells appear are arranged close to each other in parallel, and each of the word lines (WLo-WLn-1) B
A memory cell is arranged only at one of the intersections of L and BL. In this method, it is necessary to pass two word lines through one memory cell area, but as shown in Figure 4, the aspect ratio of the memory cell is approximately 1 in the current cell.
= 2, so there is no problem in terms of area.

However, the word line selection row decoder (hereinafter referred to as R/D) and the word line driving circuit (hereinafter referred to as WLdriver) placed at the end of the word line are arranged at the word line pitch as shown in FIG. Because of the necessity, even at this stage, the layout is in an extremely difficult situation.

Furthermore, in recent years, many new memory cells have been proposed for the purpose of increasing density and integration, but these generally have cells configured in two or three dimensions.

When cells are made multidimensional in this way, the aspect ratio of the memory cell approaches 1:1 from 1:2. If you do this, the memory cells and the R/D mentioned above will not be consistent with WLdrfver, and the pitch of the memory cells will be different from the R/D.
is limited by the pitch of In other words, even if we aim to reduce the number of memory cells and increase the density, if the area is below a certain level, the R/D
The memory cell area is determined by the layout area of the memory cell, which does not lead to radically higher integration.

(Problems to be Solved by the Invention) As described above, as the conventional layout method and cell area are reduced, R/D, WL driver
There was a problem in that the layout area of the two was extremely reduced, making it impossible to maintain consistency between the two.

It is an object of the present invention to provide a semiconductor memory device that has high integration density and has high integration.

[Structure of the invention]

(Means for Solving the Problems) The present invention provides R/D for selecting or driving word lines.
The WLdriver is separated into two lines and placed at both ends of the word line.

(Function) According to the present invention, it is possible to double the layout area of a conventional R/D WLdriver, and even if the cell area is reduced in the future, the layout of the R/D WLdriver can be sufficiently matched. This is effective for increasing the density of DRAM.

Furthermore, R/D WL driver f, configuring MO
8') A sufficiently large transistor can be used, improving the reliability of the transistor and, by extension, the reliability of the DRAM, resulting in an integrated circuit with a large operating margin.

(Example) The present invention will be described in detail below. FIG. 1 shows one embodiment of the present invention, and shows a word line of a memory cell and a
This shows the relationship between WL drivers.

R/D WLdrive separated into two lines as shown in the figure
er is placed at both ends of WL, and WL l −W L n
The R/D WL drIver for selective driving is arranged alternately at the upper end and lower end of the WL in the figure. This method doubles the layout area of the DWL driver compared to the conventional method. In other words, the cell area is the same as the conventional A
It is now possible to layout a D/D WL driver up to K, and higher integration can be achieved by simply reducing the cell area.

Note that the present invention is sufficiently effective even when cells are miniaturized and only one word line can run within one cell area, if combined with the K open Bit Line method as shown in FIG. 2, for example. .

〔Effect of the invention〕

As described above, according to the present invention, even when increasing cell density by reducing the cell area, it is possible to sufficiently match the layout area of the R/D WII driver for word line selection or driving. This has a sufficient effect on increasing the integration density of 5DRAM and also improving its reliability.

[Brief explanation of the drawing]

FIG. 1 is a conceptual diagram of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a diagram for explaining an example of its application, FIG. 3 is a conceptual diagram of a conventional device, and FIG. 4 is an example thereof. FIG. 1...Memory cell 2...Word M (WL)3...
...Bit, 75 (BL, BL)4...
... Row decoder (R/D), word line drive circuit (WLdriver)

Claims (2)

[Claims] (1) In a semiconductor memory device in which a plurality of memory cells each having one transistor and one capacitor are arranged in a matrix on a semiconductor substrate, and word lines, which are access signal lines to the memory cells, are arranged in parallel, the word lines A semiconductor memory device characterized in that the selection and driving can be performed from both ends of the cell array by dividing the selection or driving circuit into two lines and placing them separately at both ends of the cell array. . (2) The semiconductor memory device according to claim 1, wherein the selection/drive circuits for two adjacent word lines are always arranged at both ends of the cell array.