GB2239540A

GB2239540A - Semiconductor memory array with staggered word line drivers

Info

Publication number: GB2239540A
Application number: GB9004056A
Authority: GB
Inventors: Dong-Il Shu; Su-In Cho; Dong-Sun Min; Young-Rae Kim
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1989-12-29
Filing date: 1990-02-22
Publication date: 1991-07-03
Also published as: FR2656727A1; IT9048184A0; GB9004056D0; KR910013263A; KR930001738B1; JPH03203892A; IT1241519B; CN1052965A; IT9048184A1; DE4005990A1

Abstract

A memory cell array comprising an orthogonal array of intersecting word lines WL and bit lines BL, with memory cells at the intersections, in which alternate word line drivers 10 are located on opposite sides of the memory cell array. Row decoders 20 may be provided on both sides of the array having word line drivers, or on one side only, connections parallel to the word lines being connected to the word line drivers on the other side. Staggering the word line drivers allows denser packing of the memory cell array since more chip area is provided for each word line driver. <IMAGE>

Description

SEMICONDUCTOR MEMORY ARRAY The present invention relates to semiconductor memory arrays, and is concerned particularly with word line drivers thereof.

As higher packing densities of memory cells have been introduced to semiconductor memory devices, the design layouts of memory device circuits have adopted smaller and smaller dimensions.

To solve the problems caused by a high packing density of memory cells, semiconductor memory devices and their operation must be improved to reduce overall power consumption.

In order to accomplish a more effective layout of a memory device in a limited area, it is necessary to consider a complete array of components in the memory device. Particularly, as integrated circuit memory devices having a higher number of memory cells and a higher packing density include more decoders than integrated circuit memory devices having a lower number of memory cells, layout of the individual elements within the high packing density memory device becomes difficult.

In general, in a known semiconductor memory device, word line drivers are used for driving word lines selected by row address decoders. The word line drivers in a conventional semiconductor memory array are shown schematically in Figure 1 of the accompanying diagrammatic drawings. The memory array illustrated in Figure 1 includes a plurality of bit lines BLO to BLj, each pair of bit lines being connected to a respective sense amplifier SA, a plurality of word lines WL1 to WLn arranged across the bit lines, a plurality of memory cells arranged in rows and columns, and a plurality of word line drivers 1, each word line driver being connected to several word lines. The word line drivers, which are coupled to row address decoders 2, are all arranged on one side of the memory array.The maximum number of word line drivers per unit distance in a direction parallel to the bit lines, hereinafter referred to as the pitch of the word line drivers, depends on the area occupied by each word line driver.

Therefore since each word line driver is attached to a fixed number of bit lines, if it is required that the spacing between each bit line is reduced in order to increase the packing density of the memory cells, an increase in the pitch of the word line drivers is required. This requires a corresponding reduction in the area occupied by each of the word line drivers, which can lead to complications and difficulties in the patterning of the memory array.

Preferred embodiments of the present invention aim to provide improved design margins in the layout of a semiconductor memory array.

According to a first aspect of the present invention, there is provided a semiconductor memory array comprising a plurality of memory cells, a plurality of word lines and a plurality of word line drivers, said word line drivers being divided into first and second sets, wherein said first set is arranged on one side of said memory array and said second set is arranged on another side of said memory array.

Preferably each word line driver is connected to a plurality of said word lines.

Preferably said word line drivers number 2n and a number 2k of said word lines correspond to each said word line driver, where n and k are each integer numbers, n is greater than zero, and n is greater than k.

Preferably said first set comprises a number of word line drivers which is equal to the number of word line drivers in said second set.

Preferably the semiconductor memory array further comprises at least one row decoder arranged to activate said word line drivers.

Preferably the number of said row decoders is equal to the number of said word line drivers and each said word line driver is assigned to a respective said row decoder.

Preferably the row decoder(s) is or are arranged on one or more sides of the memory array.

The semiconductor memory array may comprise a plurality of said row decoders, which are divided into a first group arranged on one side of said memory array and a second group arranged on another side of said memory array.

According to another aspect of the present invention there is provided a semiconductor memory array comprising a plurality of said row decoders which are arranged only on said one side of said memory array, said word line drivers on said other side of the memory array being driven by means of lines arranged from the output side of the row decoders in a direction parallel to said word lines.

The present invention includes a semiconductor memory device incorporating a semiconductor memory array as described hereinabove.

For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, by way of example, to Figure 2 of the accompanying diagrammatic drawings, which shows a semiconductor memory array having an interdigitated word line structure according to a preferred embodiment of the present invention.

Referring to Figure 2, a section of memory array includes a plurality of bit lines BLO to BLk, each pair of bit lines being connected to a respective sense amplifier SA, a plurality of word lines WL arranged across the bit lines, a plurality of memory cells arranged in rows and columns and a plurality of word line drivers 10. The respective word line drivers 10 are arranged alternately on upper and lower sides of the memory array and are connected to the word lines. Half of the total number of word line drivers are arranged to be on one side of the memory array, and #the remaining half of the total number of word line drivers are arranged to be on another opposite side of the memory array. If the number of word lines in the memory array is 2n, the number of the word lines employed by each word line driver is 2k (where n > k > o, and n, k are each integer numbers).The number of word line drivers arranged on one side of the memory array is half of the total number of word line drivers.

In this preferred embodiment, a method of arranging the word line drivers has been described. The method of arrangement may also be applied to other components of the memory. For example, respective row address decoders 20 can be arranged over, or adjacent to, the respective word line drivers which are arranged as above.

In another example, the row address decoders can be arranged on only one side of the memory array in an arrangement similar to the layout of a conventional row address decoder array. In this case, word line drivers may be arranged on the other side of the memory array to the row address decoders and driven by means of lines from an output side of the row address decoders and arranged in the direction of the word lines.

As described hereinabove, preferred embodiments of the present invention may have the feature that by effectively increasing the pitch of the word line drivers, increased design margins may be allowed in the layout of the memory cells, and in the layout of the memory array or device in general.

Although specific constructions and procedures of a preferred embodiment of the invention have been illustrated and described herein, it is not intended that the invention be limited to the elements and constructions disclosed. One skilled in the art will easily recognize that the particular elements or subconstructions may be used without departing from the scope and spirit of the invention.

The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims

1. A semiconductor memory array comprising a plurality of memory cells, a plurality of word lines and a plurality of word line drivers, said word line drivers being divided into first and second sets, wherein said first set is arranged on one side of said memory array and said second set is arranged on another side of said memory array.

2. A semiconductor memory array according to Claim 1, wherein each word line driver is connected to a plurality of said word lines.

3. A semiconductor memory array according to Claim 1 or 2, wherein said word line drivers number 2n and a number 2k of said word lines correspond to each said word line driver, where n and k are each integer numbers, n is greater than zero, and n is greater than k.

4. A semiconductor memory array according to Claim 1, 2 or 3, wherein said first set comprises a number of word line drivers which is equal to the number of word line drivers in said second set.

5. A semiconductor memory array according to any of Claims 1 to 4, further comprising at least one row decoder arranged to activate said word line drivers.

6. A semiconductor memory array according to Claim 5, wherein the number of said row decoders is equal to the number of said word line drivers and each said word line driver is assigned to a respective said row decoder.

7. A semiconductor memory array according to Claim 5 or 6, wherein the row decoder(s) is or are arranged on one or more sides of the memory array.

8. A semiconductor memory array according to Claim 7, comprising a plurality of said row decoders, which are divided into a first group arranged on one side of said memory array and a second group arranged on another side of said memory array.

9. A semiconductor memory array according to Claim 7, comprising a plurality of said row decoders which are arranged only on said one side of said memory array, said word line drivers on said other side of the memory array being driven by means of lines arranged from the output side of the row decoders in a direction parallel to said word lines.

10. A semiconductor memory array substantially as hereinbefore described with reference to Figure 2 of the accompanying drawings.

11. A semiconductor memory device incorporating a semiconductor memory array according to any one of the preceding Claims.