CN1052965A - Semicondctor storage array - Google Patents
Semicondctor storage array Download PDFInfo
- Publication number
- CN1052965A CN1052965A CN90106620A CN90106620A CN1052965A CN 1052965 A CN1052965 A CN 1052965A CN 90106620 A CN90106620 A CN 90106620A CN 90106620 A CN90106620 A CN 90106620A CN 1052965 A CN1052965 A CN 1052965A
- Authority
- CN
- China
- Prior art keywords
- word line
- line driver
- storage array
- array
- semicondctor storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 238000005457 optimization Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
A kind of semiconductor storage unit contains a plurality of memory cells of array, many word line WL, multiple bit lines BL, a plurality of word line drivers 10 that are connected on the word line, and a plurality of row address decoder 20 that is used for encouraging word line driver.Word line driver is arranged at the relative both sides of memory cell array.The present invention relates to the problem of optimization layout in semiconductor storage unit.
Description
The present invention relates to semicondctor storage array, and be specifically related to its word line device.
Because the memory cell than high assembled density is introduced semiconductor storage unit, the layout of memory device circuit also adopts more and more littler size thereupon.
For solving, must improve semiconductor storage unit and operation thereof to reduce total power consumption by the caused variety of issue of the High Density Packaging of memory cell.
In order in limited area, to reach the more efficient layout of memory device, must pay attention to the complete array of element in memory device.Specifically, because have more memory cell and the integrated circuit memory devices more less than memory cell than the integrated circuit memory devices of high assembled density contains more code translator, so that in the high assembled density memory device layout of the discrete component difficulty that becomes.
Usually, in the known semiconductor memory device, word line driver is used for driving by the selected word line of row address decoder.In Fig. 1 of accompanying drawing, be shown schematically in the word line driver in a kind of general semiconductor memory array.Memory array shown in Fig. 1 comprises: multiple bit lines BL
0To BL
k(every pairs of bit line is connected to sensor amplifier SA separately), many word line WL that cross described bit lines
1To WL
n, a plurality of memory cells that line up rows and columns, and a plurality of word line driver 1.Each word line driver and some word lines link.The word line driver that is coupled to row address decoder 2 all is arranged in a side of memory array.Be referred to as hereinafter the word line driver pitch, the maximum numbers of per unit range word line drive depend on the area that each word line driver is shared on the bit line direction being parallel to.Because each word line driver is to receive on the bit line of fixed strip number, therefore, the packing density that increase memory cell just need reduce the interval between every pairs of bit line, and the pitch of increase word line driver.Each word line driver area occupied also needs to reduce accordingly, and this makes the difficulty of the complicacy of bringing memory array wiring pattern aspect.
Most preferred embodiment purpose of the present invention is to provide a kind of semicondctor storage array layout aspect improved design margin.
According to a first aspect of the present invention, the semicondctor storage array that is provided comprises: a plurality of memory cells, many word lines and a plurality of word line driver, described word line driver is divided into first and second covers, wherein, described first cover is arranged in a side of described memory array, and described second cover is arranged on the opposite side of described memory array.
Preferably each word line driver is connected on described many word lines.
Described word line driver number is preferably 2
n, and the described word line number corresponding with each described word line driver is preferably 2
k, herein, n and k respectively are integer, n is greater than zero and greater than k.
The contained word line driver of described first cover, quantity preferably equals the word line driver number in described second cover.
Described semicondctor storage array preferably also comprises a line decoder for encouraging described word line driver to dispose.
Described line decoder number preferably equals described word line driver number, and each described word line driver is assigned to separately described line decoder.
Preferably line decoder is arranged in a side or many sides of memory array.
This semicondctor storage array can contain a plurality of described line decoders, and these code translators are divided into first group of being arranged in described memory array one side and are arranged on the described memory array opposite side second group.
According to another kind of aspect of the present invention, the semicondctor storage array that is provided comprises: a plurality of described line decoders that only are arranged in the described side of described memory array, the described word line driver on the described opposite side of this memory array drives by the circuit that starts from the described word-line direction arrangement of being parallel to of line decoder outgoing side.
The present invention includes and be contained in the semiconductor storage unit of semicondctor storage array as mentioned above.
For better being understood and illustrate, the present invention how to realize being illustrated the present invention with reference to accompanying drawing 2, Fig. 2 illustrates the semicondctor storage array that has interdigitated word line structure according to most preferred embodiment of the present invention below by example.
With reference to Fig. 2, a zone of memory array comprises: multiple bit lines BL
0To BL
k, every pairs of bit line is connected to sensor amplifier SA separately, many cross the word line WL of described bit lines, a plurality of memory cell that lines up rows and columns, and a plurality of word line driver 10.Corresponding word line driver 10 alternately is arranged in the upside and the downside of memory array and is connected to each word line.Half word line driver of sum is arranged at a side of memory array, and second half then is arranged at the relative opposite side of memory array.If the word line number is 2 in the memory array
n, then the employed word line number of each word line driver is 2
k(n＞k 〉=0, and n herein, k is integer).The word line driver number that is arranged in memory array one side is half of word line driver sum.
In this most preferred embodiment, the aligning method of word line driver has been described.Also this aligning method can be applied to other elements of storer.For example, corresponding row address decoder 20 can be arranged in the top or the adjoiner of the respective word driver of as above arranging.
In another example, row address decoder only can be arranged in a side of memory array with the distribution form that is similar to common row address decoder array.In this case, word line driver can be arranged in memory array and list opposite side, and drive by the circuit that is parallel to word-line direction that starts from the row address decoder outgoing side with respect to row address decoder.
As mentioned above, most preferred embodiment of the present invention can have following feature, promptly by increasing the pitch of word line driver effectively, generally speaking can increase design margin aspect the layout of the layout of memory cell and memory array or device.
Although illustration and described the ad hoc structure and the process of most preferred embodiment of the present invention in this, and do not mean that and make the present invention be confined to disclosed element and structure.To easily consider under the principle of scope and spirit of the present invention, to be to use specific element or minor structure to the people who is familiar with the one's own profession technology.
The reader it should be noted that with all papers and with this instructions simultaneously or the file of formerly submitting to, these files are disclosed to public's examination of the application's book, the full content of these papers and file here gives in conjunction with as a reference.
The Overall Steps of disclosed whole features in the application's book (claim, summary and the accompanying drawing that comprise appendix) and/or disclosed any method like this or technology, except those wherein have some feature and/or step at least is the inconsistent combination, can be made up by any way.
Disclosed in this manual each feature (comprise any appended claim, summary and accompanying drawing), unless clearly regulation is arranged in addition, that available another kind plays is identical, the feature of equivalence or similar effect is replaced.Thereby unless clearly regulation is arranged in addition, disclosed each feature only is an example that belongs to serial equivalence or similar characteristics together.
The present invention is not limited to the details of previous embodiment.The present invention expands to arbitrary new a kind of feature of disclosed feature in the application's book (comprising claims, summary and accompanying drawing), or arbitrary new combination, or expand to the arbitrary new step of disclosed either side like this or processing step or arbitrary new combination.
Claims (11)
1, a kind of semicondctor storage array that comprises a plurality of memory cells, many word lines and a plurality of word line drivers, described word line driver is divided into first and second covers, it is characterized in that described first cover is arranged in a side of described memory array, and described second cover is arranged on the opposite side of described memory array.
2,, it is characterized in that each word line driver is connected on many described word lines according to the semicondctor storage array of claim 1.
3,, it is characterized in that described word line driver number is 2 according to the semicondctor storage array of claim 1 or 2
n, and with the corresponding described word line number of each described word line driver device be 2
K, n and k respectively are integer herein, n is zero and greater than k.
4, according to claim 1,2 or 3 semicondctor storage array, it is characterized in that described first cover comprises some word line drivers, its number equals the word line driver number that comprised in described second cover.
5, according to each semicondctor storage array in the claim 1 to 4, it is characterized in that also containing at least one line decoder for encouraging described word line driver to dispose.
6,, it is characterized in that described line decoder number equals described word line driver number, and each described word line driver is assigned to separately described line decoder according to the semicondctor storage array of claim 5.
7,, it is characterized in that line decoder is arranged in a side or many sides of memory array according to the semicondctor storage array of claim 5 or 6.
8, the semicondctor storage array according to claim 7 contains a plurality of described line decoders, it is characterized in that these line decoders are divided into first group of being arranged in described memory array one side and are arranged on the described memory array opposite side second group.
9, the semicondctor storage array according to claim 7 contains a plurality of described line decoders that only are arranged on the described side of described memory array, and the described word line driver on the described opposite side of this memory array drives by the circuit that is parallel to described word-line direction that starts from the line decoder outgoing side.
10, with reference to accompanying drawing 2 semicondctor storage array as the aforementioned basically.
11, be equipped with according to semiconductor storage unit at each described semicondctor storage array of preceding each claim.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR20104/89 | 1989-12-29 | ||
| KR1019890020104A KR930001738B1 (en) | 1989-12-29 | 1989-12-29 | Word-line driver array method of semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1052965A true CN1052965A (en) | 1991-07-10 |
Family
ID=19294145
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN90106620A Pending CN1052965A (en) | 1989-12-29 | 1990-07-31 | Semicondctor storage array |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JPH03203892A (en) |
| KR (1) | KR930001738B1 (en) |
| CN (1) | CN1052965A (en) |
| DE (1) | DE4005990A1 (en) |
| FR (1) | FR2656727A1 (en) |
| GB (1) | GB2239540A (en) |
| IT (1) | IT1241519B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102270490A (en) * | 2011-03-29 | 2011-12-07 | 西安华芯半导体有限公司 | Large-capacity DRAM chip memory array structure |
| CN112464502A (en) * | 2020-12-28 | 2021-03-09 | 深圳市芯天下技术有限公司 | Optimization and acceleration memory simulation verification method and device, storage medium and terminal |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10049730B2 (en) | 2014-07-31 | 2018-08-14 | Hewlett Packard Enterprise Development Lp | Crossbar arrays with shared drivers |
| CN116264087A (en) | 2021-12-15 | 2023-06-16 | 长鑫存储技术有限公司 | Memory device |
| CN116264089A (en) | 2021-12-15 | 2023-06-16 | 长鑫存储技术有限公司 | Memory device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6059677B2 (en) * | 1981-08-19 | 1985-12-26 | 富士通株式会社 | semiconductor storage device |
| JPS59124092A (en) * | 1982-12-29 | 1984-07-18 | Fujitsu Ltd | Memory device |
| JPS60167193A (en) * | 1984-02-09 | 1985-08-30 | Fujitsu Ltd | Semiconductor storage device |
| US4700328A (en) * | 1985-07-11 | 1987-10-13 | Intel Corporation | High speed and high efficiency layout for dram circuits |
| JPH01119987A (en) * | 1987-11-04 | 1989-05-12 | Hitachi Ltd | Semiconductor memory |
| JP2547615B2 (en) * | 1988-06-16 | 1996-10-23 | 三菱電機株式会社 | Read-only semiconductor memory device and semiconductor memory device |
-
1989
- 1989-12-29 KR KR1019890020104A patent/KR930001738B1/en not_active IP Right Cessation
-
1990
- 1990-02-22 GB GB9004056A patent/GB2239540A/en not_active Withdrawn
- 1990-02-26 DE DE4005990A patent/DE4005990A1/en not_active Withdrawn
- 1990-02-28 FR FR9002487A patent/FR2656727A1/en active Pending
- 1990-04-13 JP JP2096598A patent/JPH03203892A/en active Pending
- 1990-07-31 IT IT48184A patent/IT1241519B/en active IP Right Grant
- 1990-07-31 CN CN90106620A patent/CN1052965A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102270490A (en) * | 2011-03-29 | 2011-12-07 | 西安华芯半导体有限公司 | Large-capacity DRAM chip memory array structure |
| CN112464502A (en) * | 2020-12-28 | 2021-03-09 | 深圳市芯天下技术有限公司 | Optimization and acceleration memory simulation verification method and device, storage medium and terminal |
Also Published As
| Publication number | Publication date |
|---|---|
| KR930001738B1 (en) | 1993-03-12 |
| IT9048184A1 (en) | 1992-01-31 |
| GB9004056D0 (en) | 1990-04-18 |
| GB2239540A (en) | 1991-07-03 |
| JPH03203892A (en) | 1991-09-05 |
| FR2656727A1 (en) | 1991-07-05 |
| IT9048184A0 (en) | 1990-07-31 |
| KR910013263A (en) | 1991-08-08 |
| IT1241519B (en) | 1994-01-17 |
| DE4005990A1 (en) | 1991-07-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C01 | Deemed withdrawal of patent application (patent law 1993) | ||
| WD01 | Invention patent application deemed withdrawn after publication |