JPH01119987A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To make the capacity of a dynamic type RAM, etc., larger by successively and alternately arranging the unit circuit of a circumferential circuit provided according to a word line or a data line, which consists of a memory array, on both sides of the memory array. CONSTITUTION:The unit circuits of the circumferential circuits such as row address decoders RDU and RDB provided according to word lines W0-Wm or data lines D0-Dm, which consist of a memory array, sense amplifiers SAL and SAR, column address decoders CDL and CDR are successively and alternately arranged on both sides of the word lines W0-Wm or the data lines D0-Dm. Consequently, the unit circuits of the respective circumferential circuits can be arranged in the layout area of the two word lines W0-Wm or the data lines D0-Dm with sufficient room. Thus, the layout of the unit circuit of the circumferential circuit can be made efficient, and the capacity of the dynamic type RAM, etc., can be made larger.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and relates to a technique that is particularly effective when applied to, for example, a dynamic RAM.

(Prior Art) There is a dynamic RAM that includes a memory array and peripheral circuits such as a row address decoder, a column address decoder, and a sense amplifier. Each peripheral circuit is provided corresponding to a word line or a data line of the memory array. It includes a plurality of unit circuits such as word line drive circuits, unit precharge circuits, unit amplifier circuits, etc.

The dynamic RAM is described, for example, in "Nikkei Electronics," published by Nikkei McGraw-Hill, June 3, 1985, pages 209 to 231.

[Problem that the invention seeks to solve]

In the conventional dynamic RAM described above, peripheral circuits such as a row address decoder, a column address decoder, and a sense amplifier are arranged on one side of the corresponding memory array.

Therefore, the unit circuits constituting each of the two peripheral circuits are arranged in accordance with a relatively small layout pitch of word lines or data lines.

However, as dynamic RAMs and the like become larger in capacity, and as storage elements become smaller by using three-dimensionally structured memory cells such as stacked capacitor cells and trench cells, the peripheral circuits mentioned above become smaller. It has become difficult to arrange unit circuits in accordance with the layout pitch of word lines or data lines.

An object of the present invention is to provide a semiconductor memory device such as a dynamic RAM in which unit circuits of peripheral circuits are efficiently laid out. Another object of the present invention is to promote increased capacity of semiconductor memory devices such as dynamic RAMs.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the attached drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, unit circuits of peripheral circuits provided corresponding to word lines or data lines constituting a memory array are sequentially and alternately arranged on both sides of the word lines or data lines.

[For production]

According to the above-mentioned means, the unit circuits of each peripheral circuit can be arranged in the layout area of two word lines or data lines with a margin, so the layout of the unit circuits of each peripheral circuit can be made more efficient, and the layout of the unit circuits of each peripheral circuit can be made more efficient. can further promote larger capacity.

C Embodiment] Figure 2 shows a dynamic type RA to which this invention is applied.
A block diagram of one embodiment of M is shown. Also, the third
The figure shows a circuit diagram of a partial embodiment of the memory array and peripheral circuits of the dynamic RAM shown in FIG. An overview of the configuration and operation of the dynamic RAM of this embodiment will be explained based on these figures. Note that the circuit elements constituting each block of the dynamic and block-type RAM of this embodiment are formed on a single semiconductor substrate such as single crystal silicon using known semiconductor integrated circuit manufacturing techniques, although not particularly limited thereto. Ru. In addition, in Fig. 3, MOSFEs with arrows added to the channel (back gate) part
T is a P-channel type and is shown to distinguish it from an N-channel MO3FET, which is not marked with an arrow.

The dynamic RAM of this embodiment is based on a large-capacity memory array MARY in which three-dimensionally structured memory cells such as stacked capacitor cells, trench cells, etc. are arranged in a lattice pattern, although there are no particular limitations. composition. This memory array MARY includes m+1 word lines and n+1 sets of complementary data lines, and the input/output nodes and control terminals of each memory cell are commonly coupled to the corresponding word line and complementary data line, respectively. Memory array MARY
There are no particular restrictions on the upper and lower portions of (m+1), respectively.
/2(II) unit circuits, ie, row address decoders RDU and RDB including word line drive circuits are provided. Each word line of the memory array MARY is sequentially and alternately connected to the corresponding word line drive circuit of the row address decoder RDU or RDB. Similarly, memory array MAR
On the left and right sides of Y, there are sense amplifiers SAL and SAR each including (n+1)/2 unit circuits, that is, a unit amplifier circuit and a unit precharge circuit, and column switches CSL,
, C3R, and (n+1)/2fljJ unit circuits, ie, data line selection circuits, are arranged as column address decoders CDL and CDR.

Each complementary data line of the memory array MARY is sequentially and alternately coupled to the corresponding unit amplifier circuit and unit precharge circuit of the sense amplifier SAL or SAR. In other words,
In the dynamic RAM of this embodiment, each unit circuit of a row address decoder, a sense amplifier, and a column address decoder provided corresponding to the word line and complementary data line of the memory array MARY is connected to two of the word line and data line. They are sequentially and alternately arranged on both sides of the memory array MARY with a double pinch. Therefore, memory array MA
Even though the RY is composed of memory cells with a three-dimensional structure and the layout pitch of word lines and complementary data lines is extremely fine, the unit circuits of each peripheral circuit are efficiently arranged with plenty of margin, making it a dynamic type. This promotes increasing the capacity of RAM.

In FIG. 2, the memory array MARY has m+1 word lines WO to W arranged in parallel in the vertical direction of the figure.
m, n+1 sets of complementary data lines DO-Do to Dn·11 arranged in parallel in the horizontal direction, and (m+1)X arranged in a grid at the intersections of these word lines and complementary data lines.
(n+1) dynamic memory cells.

Each memory cell of the memory array MARY includes an information storage capacitor Cs and an address selection MO3FETQm, as exemplarily shown in FIG. Memory array M
The gates of the address selection MO5FETQm of the n + 1 ([lJ) memory cells arranged in the same row of the memory array MARY are commonly coupled to the corresponding word lines W0 to Wm, respectively. m Alternately coupled to lines DO to Dn with a predetermined regularity.For information storage in each memory cell.

A predetermined cell plate voltage Vp is commonly supplied to the other electrode of the capacitor Cs.

Row address decoders RDU and RDB are provided above and below the memory array MARY. These row address decoders each have (m+1)/2 word line drive circuits WDO, WD, as exemplarily shown in FIG.
2 to WDm-1 or WDI, WD3 to WDm, and are provided corresponding to four word line drive circuits (m+
1)/8 unit row address decoders URDO, UR
D2 to URDP-1 or URDI, and URD3 to URDp.

The unit row address decoders URDO-URDP of the row address decoders RDU and RDB include, but are not particularly limited to, 1-21 P-channel MO3FETs Q5 to Q7 and N-channel MO3FEs connected in series and parallel, respectively.
The basic configuration is an i-2 human-powered Nant gate circuit consisting of TQI 5 to Q17. Supported P channel MOS
The gates of the FETs and the N-channel MOS FETs are commonly coupled, and inverted internal address signals ax3-axi or non-inverted internal address signals ax3-axi are supplied in a predetermined combination from a row address buffer RAB, which will be described later. As a result, the level of the output node nO of each Nant gate circuit is set to a high level like the power supply voltage Vcc of the normal circuit, and the corresponding inverted internal address signals ax3 to ax or non-inverted internal address signals ax3 to axi are all When it is set to high level, it is selectively set to low level like the ground potential of the circuit.

The word line drive circuits W D O = W D m of the row address decoders RDU and RDB each include an N-channel type drive MO3FETQ, 23, although this is not particularly limited. Among these, drive M of word line drive circuits WDO, WD2 to WDm-1 of row address decoder RDU
The source of O5FETQ23 is the word line WO, W2 to Wm of the corresponding even address of the memory array MARY.
-1 respectively. In addition, these driving MO3
The drain of FETQ23 receives corresponding word line selection timing signals XO, X2 . X4 and X6 are each supplied sequentially. Similarly, the word line drive circuits WDI, WD3 to WDm of the row address decoder RDH are driven! )1MO
The source of the 3FET Q23 is connected to the corresponding odd address word line W1. of the memory array MARY. They are coupled to W3 to Wm, respectively. In addition, these driving MO5FET
The drain of Q23 has a Brillo address decoder PR.
Corresponding word line selection timing signals XI, X3 from D
．． X5 and X7 are each supplied sequentially. As will be described later, the word line selection timing signals X0-X7 are complementary internal address signals ax0 to ax2 of the lower three pins (here, for example, the non-inverted internal address signal axQ and the inverted internal address signal axQ are combined to form the complementary internal address signal It is alternatively set to a high level according to the following:

The /C level of these word line selection timing signals is set to a boost level higher than the power supply voltage Vcc of the circuit by more than the threshold voltage of the MO3FETQm for address selection of the memory cell.

The gate of the drive MO3FETQ23 of each word line drive circuit is coupled to the source of the corresponding cut MO3FETQ24. The gates of these cut MO3FETs Q24 are coupled to the circuit power supply voltage Vcc, and their drains are
4('), and is further coupled to the output terminal of the inverter circuit N1 of the corresponding unit row address decoders URDO to URDp.
The input terminal of is the output node nO of the Nant gate circuit.
is combined with On the other hand, drive MO3 of each word line drive circuit
A corresponding reset MO3FETQ is connected between the sources of the FETs, that is, the word lines WO to W, and the circuit ground potential.
25 are provided. These reset MO3FETQ2
The gates of No. 5 are commonly coupled every four, and are further coupled to the output node no of the Nant gate circuit of the corresponding unit row address decoders URDO to URDp.

From these facts, word line W of memory array MARY
O~Wm are corresponding unit row address decoders URDO~URDp of the row address decoder RDU or RDB.
The output signal of the Nant gate circuit is set to a low level, and at the same time, the corresponding word line selection timing signals XO to X7 are set to a high level, thereby alternatively being brought into a selected state.

When the output signal of the corresponding unit row address decoder is set to a high level or the corresponding word line selection timing signal is set to a low level, the word lines WO to Wm of the memory array MARY are set to a low level and non-selected state.

In FIG. 2, the pre-row address decoder PRD receives complementary internal address signals axO to ax2 of the lower three bits from the row address buffer RAB, although this is not particularly limited.
is supplied. In addition, a timing generation circuit TO, which will be described later,
A timing signal φX is supplied from.

The pre-row/res decoder PRD is selectively brought into operation when the timing signal φX is set to a high level. In this operating state, the pre-row address decoder PRD outputs the complementary internal address signal axO-a.
x2 is decoded, and the corresponding word line selection timing signals XO to X7 are temporarily set to high level. That is, the word line selection timing signals XO-x7 are selectively set to the H/F level in synchronization with the timing signal φX and according to the lower three bits of the complementary internal address selection xO-ax2.

Row address buffer RAB receives X address fΔ No. AXO- which is supplied time-wise via external terminals AO to Ai
AXI is taken in and held in accordance with the timing signal φar supplied from the timing generation circuit TG. Also,
The complementary internal address signals axQ-xL are formed based on these X address signals AXO-AXi.

On the other hand, on the left and right sides of the memory array M A RY are sense amplifiers SAL and SAR, and column switches C3L and C3R.
and column address decoder CDL.

A CDR is provided.

As exemplarily shown in FIG. 3, the modules SAL and SAR each include (n+1)/2 unit circuits, that is, unit precharge circuits UPGo, UPC2 to UPCn-1 or UPCI.

UPC3 to UPCn and unit amplifier circuit USAO, U
SA2 or US An-1 or USAI, U, SA
3 to USAn.

Unit precharge circuit UPGO of sense amplifier SAL,
UPC2 to UPCn-1 are, but are not particularly limited to, complementary data ilo/DO, D2/D2 to Dn-1 of even column addresses of the memory array (MARY).
・N-channel MO3FET Q20 and Q2 provided in series between the non-inverting signal line and the inverting signal line of Dn-1
Similarly, a unit precharge circuit UP of the sense amplifier SAH includes 1 and an N-channel MO3FETQ22 provided in parallel with these Mos FETs.
C.I.

UPC3 to UPCn are similar three N lines provided in series between the non-inverted signal lines and the inverted signal lines of the complementary data lines D1, Dl, D3, lower row or Dn-Dn of the odd column addresses of the memory array MARY. Channel Mo5
MO3FETQ20-Q2 of unit precharge circuits UPCO-UPCn, including FETQ20-Q22, respectively
All of the gates of No. 2 are commonly coupled, and a timing signal φpc is supplied from a timing generation circuit TG. The timing signal φpc is set to a high level when the dynamic RAM is in a non-selected state, and is set to a low level at a predetermined timing when the dynamic RAM is in a selected state. MO3FETQ20 of each unit precharge circuit
The commonly coupled nodes of Q21 and Q21 have a power supply voltage Vc
A predetermined voltage HV that is 1/2 of c, that is, a half precharge level, is commonly supplied.

For these reasons, when the dynamic RAM is in the non-selected state and the timing signal φpc is set to the zero level, the MO3FETs Q20 to Q22 of each unit precharge circuit of the sense amplifiers SAL and SAR are turned on all at once, and the memory array MARY+7) Complementary data &J
The non-inverted signal lines and inverted signal lines of jDO.DO to Dn-Dn are all set to the no-fubricharge level. The dynamic RAM is in the selected state and the timing signal φpc is applied.
When becomes low level, MO of each unit precharge circuit
The 3FETs Q20 to Q22 are turned off, and a minute read signal according to the data stored in the memory cell connected to the selected word line is output to the complementary data lines DO, lower 0-Dn, and Dn.

Unit amplifier circuit US for sense amplifier SAL and SAR
A O = U S A n are P channel MO3FETQ3 and N channel M
O3FETQI 3 and P channel MO3FETQ4
and N-channel MO3FETQI 4
These inverter circuits, including MOS inverter circuits, have their input and output terminals cross-connected to each other,
It is assumed to be a latch type.

The input/output node of each unit amplifier circuit of the sense amplifier SAL is the corresponding unit precharge circuit UPGO.

Complementary data line DO of even column address of memory array MARY is connected via UPC:2 to U P Cn-1.
- Connected to the non-inverting signal line or inverting signal line of Clove, D2-1 to Dn-1-Dn-R, respectively. Similarly,
The input/output nodes of each unit amplification circuit of the sense amplifier SAR are connected to the complementary data lines D1, D3, D3, D3, D3, D3, D3, D3, D3, D3, D3, D3, D3, D3, D3, Dn, etc. of the memory array MARY through the corresponding unit precharge circuits UPC1, UPC3 to UPCn, the input/output nodes of each unit amplifier circuit of the sense amplifier SAR - Connected to the Dn non-inverted signal line or inverted signal line, respectively. High level power supply terminal of CMOS inverter circuit of each unit amplifier circuit, that is, P channel MO3F
ETQ3 and Q4(7)'/-, 2. are commonly coupled to a common source line SP. In addition, the CMO of each unit amplifier circuit
The low level power supply terminal of the S inverter circuit, that is, the sources of the N channel MO3FETs Q13 and Q14 are commonly coupled to the common source line SN. Although not particularly limited, a precharge circuit similar to the unit precharge circuit described above is provided between these common source lines SP and SN.

Further, between the common source line SP and the circuit power supply voltage Vcc and between the common source line SN and the circuit ground potential, there is a P channel whose gate receives an inverted signal of the timing signal φpa or a non-inverted timing signal φpa. MO3FE
T and N channel MO3FETs are provided respectively. Therefore, the common source lines SP and SN are connected to the timing signal φpc when the dynamic RAM is in a non-selected state.
When is set to high level, both are set to half precharge level as described above. When the dynamic RAM is selected and the timing signal φpa is set to high level, the common source lines SP and SN are supplied with the power supply voltage Vcc and the ground potential of the circuit, respectively.

For these reasons, each unit amplification circuit of sense amplifiers SAL and SAR is selectively brought into operation according to the timing signal φpa. In this operation, each unit amplifier circuit connects the corresponding complementary data line DO-D from the selected memory cell.

~Dn The minute readout signal outputted via -Dn is amplified and made into a high level/low level binary readout signal.

Input/output nodes of each unit amplifier circuit of sense amplifier SAL, that is, complementary data lines DO·n, D2-D2 to Dn-1 of even column addresses of memory array MARY
- Dr+-1 are each coupled to the corresponding switch MOSFET pair of column switch C3L. Similarly, the input/output nodes of each unit amplifier circuit of the sense amplifier SAH, that is, the complementary data lines D1 and D1 of the odd column addresses of the memory array MARY. D3, clove or Dn, bottom 1 is
Corresponding switch MOSFET of column switch CSR
each coupled in pairs.

Column switches C3L and C3R are (n+1)/2 pairs of switch MOS FETs, such as N-channel MO3FETs Q18 and Q19, as exemplarily shown in FIG.
The other of the (n+1)/2 pair of switch MOSFETs forming column switch C3Lt-, each including ET, is commonly coupled to complementary common data lines CDL and CDL.

Similarly, (n+1)/
The other of the two pairs of switches MO3FET is commonly coupled to complementary common data lines CDR-CDH. Column switch C
The gates of each pair of switch MOSFETs 3L and C3R are commonly coupled, and corresponding data line selection signals SO to Sn are supplied from the corresponding column address decoder CDL or CDR, respectively. These data line selection signals are normally at low level and are used in dynamic RA
When M is in the selected state, it is alternatively set to a high level at a predetermined timing.

For these reasons, each switch MO3FET of the column switches C3L and C3R receives the data line selection signal 5 (1-
3n is alternatively set to high level, it is alternatively turned on, and the input/output node of the corresponding unit amplifier circuit of the sense amplifier SAL or SAR, that is, the memory array MA
RY's corresponding complementary data line and complementary common data line CDL
- Selectively connect CDL or CDR-CDR.

The column address decoder CDL corresponds to (n+1)/2 data line selection circuits DSO, DS2 to DSn-1 and four data line selection circuits provided corresponding to each switch MO3FET of the column switch C3L. Unit column address decoders UCDO and UC provided in
Similarly, a column address decoder CDR including D2 to UCDq-1 is provided corresponding to each pair of switch MO3FET of the column switch CSR (n+
1)/2 data line selection circuits DSI, DS3 to D
Sn, and unit column address decoders UCDI, UCD3 to UCDq provided corresponding to four data line selection circuits.

Each unit column address decoder of column address decoders CDL and CDH includes an i-2 manual Nant gate circuit NAG1, respectively, as exemplarily shown in FIG. The structure is similar to the Nant gate circuit provided in each unit row address decoder of decoders RDL and RDR, and its input terminal receives a non-inverted internal address signal ay3 from the column address buffer CAB excluding the lower three pins.
~ayi or inverted internal address signals ay3~a)T1 are each supplied in a predetermined combination. As a result, the output signals of each Nant gate circuit NAG1 etc. are normally set to high level, and the corresponding non-inverted internal address signals ay3 to ayi or inverted internal address signals 11 to ay
By setting all i's to high level, they are selectively set to low level.

Although not particularly limited, each data line selection circuit of the column address decoders CDL and CDH is a P channel MO3.
A CMOS inverter circuit consisting of FETQ2 and N-channel MOSFETQ12, and an N
channel MO3FETQI 1, respectively.

Corresponding data line selection timing signals YO, Y2 . Y4 and Y
6 or Yl, Y3°Y5 and Yl are sequentially supplied. Furthermore, the high level power supply voltage terminals of these CMOS inverter circuits are commonly coupled four by four, and are further connected to the corresponding unit column address decoders UCDO, UCD2 to UCDn-1 or UCDI, UCD3 to UCDn.
The circuit's ai
The gate of MO3FETQI of each unit column address decoder is coupled to the source voltage VCC, and the gate of MO3FETQI of each unit column address decoder is coupled to the output terminal of the corresponding Nant gate circuit NAG1. The gates of MO3FETQII of each data line selection circuit are commonly coupled by 41[1, and further coupled to the output terminal of the Nant gate circuit NAG1 of the corresponding unit column address decoder. The output signal of the CMOS inverter circuit of each data line selection circuit is the data line selection signal 5O1S2 to 5n-1 or 31. As S3 to Sn, the corresponding switch MO3 of the column switches CSL and C3H
Each is supplied to the gate of the FET.

For these reasons, the output signals of column address decoders CDL and CDH, that is, data line selection signals SO to Sn
When the corresponding combinations of non-inverted internal address signals ay3 to ayi or inverted internal address signals ay3 to ayt are simultaneously set to high level, the output signal of the Nant gate circuit NAGI of the corresponding unit column address decoder is set to low level. At the same time, the corresponding data line selection timing signals YO to Y7 are set to a high level, thereby alternatively being set to a high level.

In FIG. 2, the column address decoder PCD is supplied with a complementary internal address signal ayOxay2 of the lower three bits from the column address buffer CAB, and is supplied with a timing signal φy from the timing generation circuit TG.

The virtual column address decoder PCD is selectively put into an operating state when the timing signal φy is set to a high level. In this selected state, the Bricolumn address decoder PCD outputs the complementary internal address signal a y
O to a y 2 are decoded, and the corresponding data line selection timing signals YO to Y7 are set to an alternative high level.

Column address buffer CAB connects external terminals AO to At
Y address signal AYO- supplied in a time-division manner via
AYI is taken in and held in accordance with the timing signal φac supplied from the timing generation circuit TG. Also,
The complementary internal address signals ayQ-ayi are formed based on these Y address signals AYO-AYi.

Complementary common data line CDL - CDL and CDR/CDR
are respectively coupled to one input/output terminal of the corresponding main amplifiers MAL and MAR. The other input/output terminals of main amplifiers MAL and MAR are commonly coupled and further coupled to data input/output circuit 10. Main amplifier M
AL and MAR are commonly supplied with timing signals φw6 and φma from timing generation circuit TG, and are supplied with inverted internal address signal ax2 and non-inverted internal address signal az2 from column address buffer CAB, respectively.

Main amplifiers MAL and MAR are dynamic type RA
When M is in the write operation mode, the timing signal φwe is set to a high level and the corresponding inverted internal address signal ax2 or non-inverted internal address signal ax2 is set to a high level, so that it is selectively put into the operating state. Ru. In this operating state, main amplifiers MAL and MA
R is the data input/output circuit! The complementary write signal supplied from 10 is connected to the corresponding complementary common data line CDL/CDL.
or CDR to CDR. On the other hand, main amplifier M
AL and MAR are connected to the timing signal φmm when the dynamic RAM is in the read operation mode and the corresponding non-inverted internal address signal a.
When x2 or the inverted internal address signal ax2 is set to high level, it is selectively activated. In this operating state, the main amplifiers MAL and MAR further amplify the binary read signal received from the corresponding complementary common data line from the selected memory cell, and the data input/output circuit I10
to communicate.

The data input/output circuit I10 includes, but is not particularly limited to, a data manual buffer and a data output buffer. The input terminal of the data port of the data input/output circuit I10 is coupled to the data input/output terminal DIO, and its output terminal is commonly coupled to the other input/output terminal of the main amplifiers MAL and MAR.

On the other hand, the input terminal of the data output buffer of the data input/output circuit I10 is commonly coupled to the other input/output terminal of the main amplifiers MAL and MAR, and its output terminal is commonly coupled to the data input/output terminal DIO. A timing signal φOe is supplied from the timing generation circuit TG to the data output buffer of the data input/output circuit I10.

The data manual buffer of the data input/output circuit I10, when the dynamic RAM is in the write operation mode,
The write data supplied via the data input/output terminal DIO is used as a complementary write signal, and the main amplifier MA
Convey to L and MAR. On the other hand, data input/output circuit I1
The data output cover 7 of 0 receives the timing signal φ when the dynamic RAM is in the read operation mode.
It is selectively activated according to Oe. In this operating state, the data output buffer is connected to the main amplifier M
The read data output from AL or MAR is sent to the outside via the data input/output terminal DIO.

The timing generation circuit TO receives a row address strobe signal, an R-area column address strobe signal CAS, and a write enable signal WE, which are supplied as control signals from the outside.
Based on this, the various timing signals mentioned above are formed and supplied to each circuit of the dynamic RAM.

FIG. 1 shows a layout diagram of an embodiment of the memory array and peripheral circuits of the dynamic RAM shown in FIG.

In FIG. 1, a memory array M A RY is arranged in most of the central region of a semiconductor substrate where a dynamic RAM is formed.

In the dynamic RAM of this embodiment, the dynamic memory cells forming the memory array M A RY each include the information mail capacitor C3 and the address selection MO3FETQm, as described above. For these memory cells, memory cells having a three-dimensional structure such as stacked capacitor cells, trench cells, etc. are used. Therefore, the word lines and complementary data lines of the memory array are laid out in very 331 patches.

Row address decoders RDU and RDB are arranged above and below the memory array M A RY, respectively. Of these, the row address decoder RDU is (
m+1 > / 2 ill word line drive circuit WDO
, WD2 to WDm-1 and (m+1)/13111
unit row address decoder URDO or URDp-
1, word line drive circuits WDO, WD2 to W
Dtn-1 is coupled to words 1aWO, W2 to Wm-1 at even row addresses of memory array MAR'Y, respectively. Similarly, the row address decoder RDB is
It includes (m+1)/2 word line drive circuits WDI, WD3 to WDm and (m+1)/8 unit row address decoders URDI to URDp. Word line drive circuits WDI, WD3 to W D m are respectively coupled to word lines WI, W3 to Wm at odd row addresses of memory array MARY.

In the dynamic RAM of this embodiment, each word line drive circuit of the row address decoders RDU and RDB respectively extends over the corresponding word line of the memory array M A RY and its adjacent word line, that is, layerer +- region x of the two word lines. Placed. Further, each unit row address decoder of row address decoders RDU and RDB is arranged over the layout area of four corresponding word line drive circuits. For this reason, even though the word lines WO to Wm of the memory array M A RY are arranged at a very fine pitch, the word line drive circuit of the row address decoder provided corresponding to these word lines is It can be arranged efficiently and with sufficient margin.

On the other hand, on the left side of the memory array MARY, as described above, the sense amplifier SAL, the column switch C3L, and the column address decoder CDL are arranged. Further, on the right side of the memory array MARY, a sense amplifier SAR, a column switch C3R, and a column address decoder CDR are arranged. Of these, the sense amplifier SAL is connected to the complementary data lines DO-Do, D2.D2 to Dn-1.
(fl+1)/2 unit precharge circuits UPGO, UPC2 to UPCn provided corresponding to Dn-1
-1 and unit amplifier circuit USAO, USA2 or US
An-1, and also a column address decoder C
DL is (n+1)/2 provided corresponding to each unit precharge circuit and unit amplifier circuit of the sense amplifier SAL.
data line selection circuits DSO, DS2 to DSn-1
and (n) provided corresponding to the four data line selection circuits.
+1)/8 unit column address decoders UCDO,
Similarly, sense amplifiers SAR including UCD2 to UCDq-1 are provided corresponding to complementary data lines DI-Di, D3 and Dn-1 at odd column addresses of the memory array MARY (n+1). /2 unit precharge circuits UPCI.

UPC3 to UPCn and unit amplifier circuit USA1, U
A column address decoder CDR including SA3 to USAn is provided corresponding to each unit precharge circuit and unit amplifier circuit of the sense amplifier SAH (n
+1)/2(t& data line selection circuits 0S1.DS3 to DSn and (n+1) 78 unit column address decoders UCD1, UCD3 to UCDQ provided corresponding to the 4(t& data line selection circuits). .

In the dynamic RAM of this embodiment, each unit precharge circuit and unit amplifier circuit of sense amplifiers SAL and SAR, and column address decoders CDL and CDH
Each data line selection circuit is arranged over a layout area of a corresponding complementary data line of memory array MARY and an adjacent complementary data line, that is, two sets of complementary data lines. In addition, column address decoder CDL
Each unit row address decoder of CDH and CDH is arranged over the layout area of four corresponding data line selection circuits. Therefore, even though the complementary data lines DO/DO to Dn-Dn of the memory array MARY are arranged with very fine pinches, the unit precharge circuit of the sense amplifier provided corresponding to these complementary data lines is The unit amplifier circuit and the data line selection circuit of the column address decoder can be efficiently arranged with a relatively large margin.

As described above, the dynamic RAM memory array MARY of this embodiment uses memory cells with a three-dimensional structure such as stacked capacitor cells and trench cells to achieve miniaturization of storage elements and large capacity. will be promoted. Word lines and complementary data lines to which each memory cell is coupled are arranged at very fine pitches as these storage elements become smaller. Therefore, in the dynamic RAM of this embodiment, the word line drive circuits of the row address decoders RDU and RDH provided corresponding to the word lines are as follows:
They are arranged sequentially and alternately above and below the memory array MARY and over the layout area of the two word lines. In addition, a sense amplifier SA provided corresponding to the complementary data line
The L and SAR unit precharge circuits, unit amplifier circuits, and the like are sequentially and alternately arranged on the left and right sides of the memory array MARY, and over the layerer 1 region of the two sets of complementary data lines. Therefore, each unit circuit is efficiently arranged with a comparative margin even though the corresponding word line or complementary data line is arranged with a fine pinch. This increases the degree of freedom in layout design on the semiconductor substrate, making it possible to promote miniaturization and increased capacity of dynamic RAMs and the like.

As shown in the above embodiment, the following effects can be obtained by applying the present invention to a semiconductor memory device such as a dynamic RAM.

That is, by alternately arranging the unit circuits of the peripheral circuits provided corresponding to the word lines or data lines constituting the +11 memory array on both sides of the word line or data line, the unit circuits of each peripheral circuit are It is possible to efficiently arrange two word lines or data lines over the layout area, in other words, with twice the pinch of the word lines or data lines, with a margin.

(2) According to the above item (1), the degree of freedom in layout design of a dynamic RAM or the like is increased, and as a result, miniaturization of memory elements can be promoted.

(3) The above-mentioned items (1) and (2) have the effect of suppressing the increase in the size of semiconductor substrates such as dynamic RAMs and promoting the increase in their capacity.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without advancing the gist of the invention. For example, in the layout diagram of FIG. 1, each peripheral circuit may be placed on either the top, bottom, left or right of the memory array MARY, and the placement order of word lines and complementary data lines is the same as in this embodiment. Furthermore, the unit circuits of each peripheral circuit may include, for example, row address decoders RDU and RDB or only sense amplifiers SAL and SAR in the memory array MA.
At least one unit row address decoder and one or more unit column address decoders may be disposed distributed on both sides of the memory array MARY, such as disposed on both sides of the memory array MARY, for example, eight or more word line drive circuits or data It may also be provided corresponding to a line selection circuit or the like. In the block diagram of FIG. 2, the memory array MARY may be composed of a plurality of memory mats; in this case,
A unit row address decoder and a unit column address decoder can be shared by two adjacent memory mats. In the circuit diagram of FIG. 3, memory array M
The memory cells that make up the ARY do not need to be stacked capacitor cells or trench cells, and the
The circuit configurations of the IHA operating circuit, unit precharge circuit, unit amplifier circuit, etc. are arbitrary. Furthermore, the arrangement of the memory array MARY and each peripheral circuit shown in FIG. 1, the block configuration and address signal/control signal combinations of the dynamic RAM shown in FIG. 2, and the memory array MARY and Various embodiments can be adopted, such as the specific circuit configuration of each peripheral circuit.

The above explanation will mainly focus on the dynamic type RA, which is the application field that is the background of the invention made by the present inventor.
The present invention has been described for the case where it is applicable to M, but it is not limited thereto, and can also be applied to, for example, a dual boat memory whose basic configuration is a dynamic memory cell and various semiconductor memory devices. It has word lines or data lines arranged at a pitch, and a plurality of δ lines provided corresponding to these word lines or data lines.
The present invention can be widely used in semiconductor memory devices having peripheral circuits including unit circuits and digital devices incorporating such semiconductor memory devices.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, by sequentially and alternately arranging the unit circuits of the peripheral circuits provided corresponding to the word lines or data lines constituting the memory array on both sides of the memory array, the unit circuits of each peripheral circuit are divided into two word lines. In other words, the lines or data lines can be arranged at a pitch twice that of the word line or data line with a margin, which allows for miniaturization of storage elements such as dynamic RAM, and It is possible to promote larger capacity such as

[Brief explanation of the drawing]

Figure 1 shows a dynamic RAM to which this invention is applied.
FIG. 2 is a layout diagram showing one embodiment of a memory array and its peripheral circuit, and FIG.
FIG. 3 is a circuit diagram showing an example of the memory array of the dynamic RAM of FIG. 2 and its peripheral circuits. MARY...Memory array, MC...Memory cell,
WO~Wm...word line, DO/DO~Dn-Dn-
Complementary data lines, RDU, RDB...Row address decoder, URDO~URDp...Unit row address decoder, WDO~WDrn・-, word line drive circuit, SA
L, SAR...Sense amplifier, UPCO~UPCn・
・Unit precharge circuit, USAO~USAn...
Unit amplification circuit, C5L, C3R...column switch,
CDL, CDR...Column address decoder, UCD
O~UCDq...Unit column address decoder, DS
O~DSn...Data line selection circuit. PRD...Brillo address decoder, PCD...
Bri column address decoder, RAB... row address buffer, CAB... column address buffer, M
AL, MAR...main amplifier, Ilo...data input/output circuit, TG...timing generation circuit. Cs... Capacitor for information storage, Qm... MOS FET for address selection %Q1-Q6... P channel MO3FET, Ql 1~Q25...N
Channel MO5FET, Nl...inverter circuit,
NAGI...Nant gate circuit.

Claims (1)

[Claims] 1. Unit circuits of peripheral circuits provided corresponding to word lines and/or data lines are sequentially and alternately arranged on both sides of the word lines and/or data lines. Semiconductor storage device. 2. The unit circuit includes a word line drive circuit of a row address decoder provided corresponding to the word line, a data line selection circuit of a column address decoder provided corresponding to the data line, and a unit amplifier circuit of a sense amplifier. 2. The semiconductor memory device according to claim 1, further comprising at least one of a unit precharge circuit and a unit precharge circuit. 3. The semiconductor memory device according to claim 1 or 2, wherein the semiconductor memory device is a dynamic RAM.