JPH0713860B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory (hereinafter referred to as DRAM) that combines a high speed access function in a static column mode and a nibble mode. It is about.

[Prior Art] In recent years, semiconductor memory devices have made remarkable progress, and various high-speed access functions have been developed for DRAMs. As a typical example of such a high-speed access function of DRAM,
There are static column mode and nibble mode.

FIG. 3 is a block diagram showing an example of a conventional 1M DRAM which realizes the above-mentioned static column mode.

Referring to FIG. 3, the memory cell array 1 has 1024
(= 2 ¹⁰ ) word lines and 1024 pairs of bit lines are arranged so as to intersect with each other, and a memory cell is provided at each intersection thereof. Address buffer 10
An external address signal is externally applied to 0, and the timing generator 200 receives the row address strobe signal (hereinafter, ▲ ▼ signal) and the column address strobe signal (hereinafter, ▲ ▼ signal) from the outside and receives the DRAM.
It generates various timing signals for controlling the operation of each part. Row decoder circuit 2 receives row address signals RA0 to RA9 from address buffer 100 and selects one of 1024 word lines, for example word line 3. Further, the column decoder circuit 4 constituted by a known static type circuit is provided with the column address signals CA0 to CA from the address buffer 100.
In response to the command 9, one of 1024 pairs of bit lines, for example, the pair of bit lines 5 is selected. The information read from each memory cell onto the bit line is amplified by the sense amplifier 6. The read information on the bit line selected by the column decoder circuit 4 is further amplified by the preamplifier 7 and then output via the output buffer circuit 8 and the output terminal 9.

Next, FIG. 4 is a timing chart for explaining the operation of the conventional 1M DRAM shown in FIG. The high speed access function in the static column mode of the DRAM shown in FIG. 3 will be described with reference to FIG.

In Fig. 4, the ▲ ▼ signal changes from "H" level to "L".
When the level is changed (FIG. 4 (a)), the row address signals RA0 to RA9 (FIG. 4 (c)) are taken into the semiconductor chip, and these row address signals RA0 to RA9 cause The row decoder circuit 2 in FIG. 3 operates. This gives 1024
One of the word lines, for example word line 3 in FIG.
Is selected and information is read out from 1024 memory cells connected to the word line 3 on 1024 pairs of bit lines. The information read onto each bit line pair is amplified by the sense amplifier 6.

Next, ▲ ▼ when the signal changes to "L" level from "H" level "(FIG. 4 (b)), the column address signals CA 0 ₁
~CA9 ₁ (Fig. 4 (c)) is taken into the chip, these column address signals CA0 _{1 ~CA9 1,} the column decoder circuit 4 of FIG. 3 operates. As a result, one of the 1024 pairs of bit lines, for example, the bit line pair 5 in FIG. 3 is selected, and the information read on the selected bit line pair is amplified by the preamplifier 7 and output buffer. It appears as output data Q1 (FIG. 4 (d)) on the output terminal 9 via the circuit 8.

Next, the column address signal, CA 0 ₂ ～CA9 When ₂ was changed to the column decoder circuit 4 composed of a static type circuit
Operates again according to the change in the column address signal, and selects a different bit line pair while deselecting the bit line pair that has been selected so far. Then, the information read on the newly selected bit line pair is output to the output data Q2 on the output terminal 9 via the preamplifier 7 and the output buffer circuit 8.
Appears as (Fig. 4 (d)).

In this way, the read information on the 1024 pairs of bit lines connected to the same word line 3 is sequentially selected according to the change in the column address signal (FIG. 4 (c)), and the output data Q3, Q4 is selected. , ...
(Fig. 4 (d)) is output.

As described above, in the static column mode shown in FIGS. 3 and 4, the row decoder circuit 2 and the sense amplifier 6 are restarted after operating once at the falling edge of the signal (FIG. 4 (a)). The state is maintained without operating, while only the column decoder circuit 4 is operated again according to the change of the column address signal to output the read information. That is, in static column mode,
▼ Since the signal input is omitted and different memory cells are accessed only by changing the column address signal, the read time and the cycle time are remarkably shorter than that of the normal read, for example, about 1 / It can be shortened to about 2.

Next, FIG. 5 shows a conventional nibble mode that realizes the above-mentioned nibble mode.
It is a block diagram showing an example of 1M DRAM.

5, row decoder circuit 2 receives row address signals RA0-RA9 from address buffer 100 and outputs one of 1024 word lines, as in row decoder circuit 2 of FIG.
The book, for example, the word line 3 is selected, but the column decoder circuit 14 differs from the column decoder circuit 4 of FIG. 3 in that it receives the column address signals CA0 to CA9 from the address buffer 100 and outputs 1
Four of the 024 pairs of bit lines, for example, bit line pair 5 are selected. The column decoder circuit 14 shown in FIG. 5 is not a static type circuit like the column decoder circuit 4 shown in FIG. 3, but is constructed so as not to restart even if the address input signal changes. The information on the four pairs of bit lines selected by the example decoder circuit 14 is applied to and stored in the first to fourth registers 21, 22, 23 and 24, respectively. Between each register and the output buffer circuit 8, the first
To fourth switching elements 25, 26, 27 and 28, respectively.
On / off of 28 is controlled by nibble decoders 29, 30, 31 and 32, respectively. The output buffer circuit 8 and the output terminal 9 correspond to the output buffer circuit 8 and the output terminal 9 of FIG. 3, respectively.

FIG. 6 is a waveform diagram for explaining the operation of the 1M DRAM of FIG. Next, referring to FIG. 6, the DR shown in FIG.
The high-speed access function in AM nibble mode is explained.

First, in FIG. 6, when the signal ▲ ▼ changes from "H" level to "L" level (FIG. 6 (a)), the row address signals RA0 to RA9 (FIG. 6 (c)) are transferred to the chip. The row decoder circuit 2 shown in FIG. 5 operates in response to these row address signals RA0 to RA9. As a result, one of the 1024 word lines, for example, the word line 3 in FIG. 5 is selected, and information is respectively output from the 1024 memory cells connected to this word line 3 onto the 1024 bit line pairs. Is read. The information read onto each bit line pair is amplified by the sense amplifier 6.

Next, when the ▲ ▼ signal changes from "H" level to "L" level (Fig. 6 (b)), the column address signals CA0 to C
A9 (FIG. 6 (c)) is taken into the chip, and CA0 to CA7 of these column address signals CA0 to CA9 operate the column decoder circuit 14 of FIG. As a result, four of the 1024 pairs of bit lines are selected, and the information read on the selected pair of bit lines is input to the first to fourth registers 21, 22, 23 and 24. Amplified and retained.

Next, of the input column address signals CA0 to CA9, the remaining signals CA8 and CA9 are input to the nibble decoders 29 to 32, and one of them is selected accordingly. Now, assuming that the nibble decoder 29 is selected, the switching element 25 becomes conductive, the information held in the first register 21 is transferred to the output buffer circuit 8, and as a result, the output data Q1 appears at the output terminal 9. (FIG. 6 (d)). Then, it is assumed that the ▲ ▼ signal once becomes the "H" level and then becomes the "L" level again while keeping the ▲ ▼ signal at the "L" level (Fig. 6 (a)) (Fig. 6 (b)). )). In this case, since the signal ▼ is kept at "L" level, the same word line 3 is continuously selected, and the sense amplifier 6 also holds the previous state. On the other hand, the column decoder circuit 14 is not a static type circuit as described above, and does not restart even if the input address signal changes and is reset by the ▲ ▼ signal. While being held at the L "level, the column decoder circuit 14 is not reset and maintains the previous state. That is, the data stored in the registers 21 to 24 is maintained as it is while the signal ▲ ▼ is held at "L" level. Here, the nibble mode compatible DRAM of FIG.
In this case, since the nibble decoders 29 to 32 are configured to operate as shift registers,
Once the signal ▼ goes to "H" level as shown in FIG. 6B, the nibble decoder 29 is deselected, and the nibble decoder 30 is selected at the next falling edge of the signal ▼. In response to this, the switching element 26 becomes conductive, the information held in the second register 22 is transmitted to the output buffer circuit 8,
As a result, output data Q2 appears at the output terminal 9 (FIG. 6 (d)). In this way, by changing the ▲ ▼ signal from "H" level → "L" level → "H" level → "L" level while keeping the ▲ ▼ signal at "L" level, the nibble decoder 29 ~ 32 operates as a shift register as a whole, and the switching elements conducted by this shift sequentially. As a result, the data held in the registers 21 to 24 are sequentially selected and output as output data (FIG. 6 (d)).

As described above, in the nibble mode shown in FIGS. 5 and 6, 4-bit data selected by the input address signals RA0 to RA9 and CA0 to CA7 is read at high speed by toggling the signal. It That is, the fifth
By operating the nibble decoder as a shift register as described above, the 1MDRAM shown in the figure further shortens the read time and the cycle time to, for example, about 1/2 of that of the 1MDRAM in the static column mode shown in FIG. It is possible.

[Problems to be Solved by the Invention] The conventional high-speed access function is configured as described above, but in the static column mode as shown in FIG. 3, higher-speed access is possible than in the normal mode. However, it cannot be said that it is still sufficient. On the other hand, in the nibble mode as shown in FIG. 5, although it is satisfactory in terms of speed, there are only 4 bits of read information, which is less than the 1024 bits of the static column mode. However, there are many restrictions on usage.

Also, in recent years, a new mode called serial mode has been introduced.
Introduced in DRAM. This is an extension of the above-mentioned nibble mode, in which a register for 1024 bits is provided instead of the data register for 4 bits as shown in FIG. For such serial mode,
For example, IEEE International Sol, February 19, 1988
id-State Circuit Conference DIGEST OF TECHNI
S. Watanabe e on pages 248 and 249 of CAL PAPERS
“An Experimental 16Mb CMOS DRAM by t al.
Chip with a 100MHz Serial Read / Write Mode "
Are disclosed in. According to this serial mode, the advantages of both the static column mode and the nibble mode can be taken into consideration, but on the other hand, it is necessary to provide 1024 registers, which causes a problem that the chip area increases significantly. .

An object of the present invention is to solve the above-mentioned problems, and to realize a semiconductor memory device capable of continuously reading a large number of bits like a serial mode by high-speed reading like a nibble mode without causing a large increase in chip area. Is to provide.

[Means for Solving the Problems] A semiconductor memory device according to the present invention includes a memory cell array composed of memory cells arranged in a two-dimensional array of a plurality of rows and a plurality of columns, a means for receiving an external address signal, and an external address signal A row decoder means for selecting a desired row in accordance with the row address signal, and a plurality of memory cells of the plurality of memory cells forming the selected desired row in accordance with the column address signal of the external address signal. A column decoder means for selecting a plurality of registers, a first register group including a plurality of registers for temporarily holding read information from the selected plurality of memory cells, and the same number as the first register group. Second register group consisting of the first register group, the first register group and the second register group
The same number of transfer gate groups as the first register group, the data output means connected to each register constituting the second register group, and the second register group. Shift register means for sequentially selecting the registers and outputting the data of each register via the data output means, and control means for temporarily bringing the transfer gate group into conduction after the output of the data from the second register group is completed. The column address signal changes before the output of the data from the second register group is completed, and the column decoder means changes the plurality of memory cells each time the column address signal changes. It is to select again.

[Operation] In the semiconductor memory device according to the present invention, data of a plurality of selected memory cells is stored in a group of shift registers, and while the data is sequentially selected and read, a new column address signal changes the data. Multiple static memory cells are selected and stored in another shift register group, and the next data is transferred to the previous register group after the data read from the previous register group is completed. It is possible to combine the high-speed access function of the Nibble mode and the high-speed access function of the nibble mode, and to realize continuous reading of many bits in the high-speed mode like the nibble mode and in the static column mode without increasing the chip area. You can

[Embodiment] FIG. 1 is a block diagram showing a 1M DRAM which is an embodiment of the present invention. The DRAM shown in FIG. 1 is the same as the DRAM capable of nibble mode shown in FIG. 5 except for the following points. That is, the column decoder circuit 114 in FIG. 1 is a static decoder circuit like the column decoder circuit 14 shown in FIG. 3, unlike the column decoder circuit 14 in FIG. Also, the 4-bit register 21 or
In addition to 24, 4-bit registers 33 to 36 are further provided, and four transfer gates 37 to 40 are provided between the registers 21 to 24 and the registers 33 to 36. Further, there is provided a control signal generation circuit 300 which detects the rising of the signal and provides the control signal φ commonly to the transfer gates 37 to 40.

FIG. 2 is a timing chart for explaining the operation of the embodiment shown in FIG. Next, the operation of the embodiment shown in FIG. 1 will be described with reference to FIG.

First, in FIG. 2, when the signal ▲ ▼ changes from the "H" level to the "L" level (FIG. 2 (a)), the row address signals RA0 to RA9 (FIG. 2 (c)) are transferred in the chip. The row decoder circuit 2 shown in FIG. 1 is operated by these row address signals RA0 to RA9. As a result, one of the 1024 word lines, for example, the word line 3 in FIG. 1 is selected. Information is read from 1024 memory cells connected to the word line 3 onto 1024 pairs of bit lines. The information read onto each bit line pair is amplified by the sense amplifier 6.

Next, at time T ₁ , when the signal ▲ ▼ changes from the “H” level to the “L” level (FIG. 2 (b)), the column address signals CA0 _{1 to} CA9 ₁ (FIG. 2 (c)). ) is taken in the chip, CA 0 ₁ of these column address signals CA 0 ₁ to CA ₉
.About.CA71 causes the column decoder circuit 114 of FIG. ₁ to operate. As a result, four of the 1024 bit line pairs are selected, and the information read from the memory cells 41 to 44 on the selected bit line pair is stored in the first to fourth registers.
Input to 21,22,23 and 24, amplified and held.

Here, at time T ₁ , the control signal φ (FIG. 2 (d))
Is at the "H" level, the four transfer gates 37 to 40 are in the conductive state. Therefore, the data in the registers 21 to 24 are directly registered via the transfer gates 37 to 40.
Transferred to 33-36.

Next, to the remaining signal CA8 _1, CA9 ₁ no 4 nibbles decoder 29 of the column address signals CA0 ₁ ~CA9 ₁ input 32
, And one of them is selected accordingly. If, for example, the nibble decoder 29 is selected, the switching element 25 becomes conductive, the information held in the register 33 is transmitted to the output buffer circuit 8, and as a result, the output data Q1 appears at the output terminal 9 (second Figure (e)). Then, it is assumed that the ▲ ▼ signal once becomes the "H" level and then becomes the "L" level again while keeping the ▲ ▼ signal at the "L" level (Fig. 2 (b)) (Fig. 2 (b)). )). In this case, as in the case of the nibble mode shown in FIGS. 5 and 6, the four nibble decoders 29 to 32 function as a shift register as a whole, so that the nibble decoder 29 is not activated by the rising of the signal. The selection is made, and the nibble decoder 30 is selected at the next falling edge of the signal. In response to this, the switching element 26 becomes conductive, the information held in the register 34 is transmitted to the output buffer circuit 8, and as a result, the output data Q2 appears at the output terminal 9 (FIG. 2 (e)).

In this way, by switching the ▲ ▼ signal while keeping the ▲ ▼ signal at the "L" level, the switching elements that are made conductive are sequentially shifted, and as a result, the data held in the registers 35 and 36 is changed. Are sequentially selected and output as output data Q3 and Q4 (FIG. 2 (e)).

On the other hand, control signal φ attains an “L” level at any time after the first data Q1 is read, for example at time T ₂ , and transfer gates 37 to 40 are rendered non-conductive. Then, when the subsequent output data Q1~Q4 any previous output all, for example, at time T _3, the external address signal CA
0 ₂ ~CA9 shall be changed to _2. In the embodiment shown in FIG. 1, since the column decoder circuit 114 is formed of a static type circuit like the DRAM for the static column mode shown in FIG. 3, new column address signals CA0 ₂ ...
CA7 ₂ in response to, selects a bit line pair of four different pairs before. That is, information read from different memory cells 51 to 54 connected to the same word line 3 is stored in the register 21.
Held to 24. At this time, since control signal φ is at "L" level, transfer gates 37 to 40 are rendered non-conductive, and therefore the data read to registers 21 to 24 are not transferred earlier. Then, a counter circuit (not shown) built in the control signal generating circuit 300, which is separately provided, counts the rising of the ▲ ▼ signal when the ▲ ▼ signal is at the "L" level and detects the fourth rising. if as the control signal φ becomes "H" level when, after a 4-bit data corresponding to the previous column address signals CA0 ₁ ~CA7 ₁ is output from all registers 33 to 36, to no register 21 24 data transfer gates 37 or
Transferred via 40 to registers 33-36. And
From the next falling ▲ ▼ signal, the column address signal
4-bit data corresponding to CA0 _{2 to} CA7 ₂ are sequentially read from the registers 33 to 36, and output data Q5, Q6, Q7 and Q8.
Is output as.

Therefore, each time the external column address signal changes,
By repeating the toggle operation of the signal {circle around (1)} as described above, the information of 1024 memory cells connected to one word line 3 can be continuously read out at a high speed like nibble mode.

Although the embodiment of FIG. 1 applies the present invention to 1M DRAM, the present invention is also applicable to 1M or less DRAM or 1M or less DRAM.

As described above, according to the present invention, by combining the high speed access function of the static column mode and the high speed access function of the niobium mode, it is possible to achieve the same level as the nibble mode without increasing the chip area. In the high speed mode, it is possible to continuously read a large number of bits as in the static column mode.

[Brief description of drawings]

FIG. 1 is a block diagram showing a 1M DRAM which is an embodiment of the present invention. FIG. 2 is a timing chart for explaining the operation of the DRAM shown in FIG. Figure 3 shows
FIG. 11 is a block diagram showing an example of a conventional 1M DRAM that realizes a static column mode. FIG. 4 is shown in FIG.
3 is a timing chart for explaining the operation of the 1M DRAM. FIG. 5 is a block diagram showing an example of a conventional 1M DRAM which realizes the nibble mode. FIG. 6 is a timing chart for explaining the operation of the DRAM shown in FIG. In the figure, 1 is a memory cell array, 2 is a row decoder circuit, 3 is a word line, 5 is a bit line pair, 6 is a sense amplifier, 8 is an output buffer circuit, 9 is an output terminal, 21, 22, 23, 2
4, 33, 34, 35 and 36 are registers, 29, 30, 31 and 32 are nibble decoders, 37, 38, 39 and 40 are transfer gates, 100 is an address buffer, 114 is a column decoder circuit, 200 is a timing generator, Reference numeral 300 indicates a control signal generation circuit. In each drawing, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A memory cell array consisting of memory cells arranged in a two-dimensional array of a plurality of rows and a plurality of columns, means for receiving an external address signal, and a desired row according to a row address signal of the external address signals. Row decoder means for selecting, and a column decoder means for selecting a plurality of memory cells of the selected desired row according to a column address signal of the external address signal, A first register group including a plurality of registers for temporarily holding read information from the selected plurality of memory cells, and a second register including the same number of registers as the first register group. Group, transfer gate groups provided between the first register group and the second register group, the number being the same as that of the first register group, and each constituting the second register group. Data output means connected to the registers, shift register means for sequentially selecting the registers constituting the second register group and outputting the data of each register via the data output means, the second register group Control means for temporarily conducting the transfer gate group after the output of the data from the second register group is finished, the column address signal changes before the output of the data from the second register group is finished, The column decoder means
A semiconductor memory device in which a plurality of memory cells are selected again each time the column address signal changes.