JPH0213394B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improving the performance of a MOS dynamic memory, particularly a multi-address type memory.

In a so-called multi-address type semiconductor dynamic memory, which divides address input signals into two groups, row selection and column selection, and inputs them in different time periods using the same pin group, the effective access time In order to shorten the cycle time, a function called page mode is provided in which the memory is operated by continuously changing only the column selection address while keeping the row selection address fixed. However, in order to operate dynamically, conventional memory requires a so-called precharge period to return the memory circuit to its initial state after memory operation, even in the page mode, and the cycle time is approximately twice the access time. Therefore, it had the drawback that it could not take full advantage of its functions.

The present invention aims to significantly improve performance in page mode by making all circuits operating in page mode static type circuits, making the cycle time and access time almost the same.

FIG. 1 shows an embodiment of the present invention.

In the figure, 1R and 1C are external control clocks, the former mainly controlling the row selection operation, and the latter controlling the column selection operation. Hereinafter, symbols with the suffix R in the drawings will refer to row selection operations, and symbols with the suffix C will refer to column selection operations. 2R and 2C are 1R and 1C respectively
This is a circuit that receives input from the memory and generates multiple timing pulses necessary for internal memory operations. In the figure, only typical output lines are shown, and the others are omitted. Mainly, the output of 2R is sent to the row selection operation circuit,
Needless to say, it is supplied to the 2C output column selection operation circuit. 3 is an address input. Normally, there are multiple inputs, but for simplicity, only one input is shown here. The row selection address is input in synchronization with 1R, and the column selection address is input in synchronization with 1C. This input is input to address buffer circuits 4R, 4C, and 12R, 12C, respectively.
Follow the control of 14R (confirmation), 14 (denial),
It is output to 14C, 14. 14R, 14 are row decoders involved in row selection operations, word lines W ₀ ,
It is supplied to block 5R consisting of a drive circuit for _W1, etc., and 14C and 14 are column decoders and column selectors.
The signal is supplied to block 5C, which includes a drive circuit for the control line 15 of MOS Q ₃ and Q ₄ . 100 is a memory cell array section, which includes bit lines B ₀ , B ₀ (other bit lines are omitted) and word lines W ₀ , W ₁ (other word lines,
For example, a memory cell MC of 1MOS type is arranged at the intersection of the dummy word lines (dummy word lines are omitted). 6R
is a detection circuit for detecting minute signals from MC,
It consists of Q ₁ and Q ₂ and operates according to instructions from 13R. The signal detected and amplified by 6R is Q ₃ ,
It is transmitted to the input/output data line I/O through _Q4 and output to the output terminal 8 via the amplifier 7C. On the other hand, to write data, data input 9
The data input from the data input buffer 10
It is connected to I/O via C, and is performed through the reverse path to the above-mentioned reading.

Now, of the operations described above, it can be said that roughly up to the detection amplification operation by 6R is related to the row selection operation, and the subsequent operations are related to the column selection operation.

In the present invention, among the above circuits, the circuits related to the column selection operation with the suffix C are operated in a static manner. The biggest obstacle in this staticization is the transmission and reception of signals between the bit line and the input/output data line, that is, the transmission and reception of signals between the bit line B ₀ ,
The purpose is to statically take out the signal on B ₀ to the I/O without destroying it, and to correctly transfer the signal from the I/O to B ₀ and B ₀ during writing.

FIG. 2 shows the configuration of a well-known 6MOS type static memory cell. 1 in the same figure
03 and 104 are bit lines, 105 is a word line,
106 indicates a power line. As is clear from comparing Figures 1 and 2, Q ₁ −Q ₁ ′, Q ₂ −Q ₂ ′,
Q ₃ −Q ₃ ′, Q ₄ −Q ₄ ′, 101−B ₀ , 102− ₀ ,
103-I/O and 104- are in a corresponding relationship. Therefore, Q ₁ , Q ₂ , Q ₃ ,
If the constant of _Q4 is designed in the same way as the conventionally known memory cell shown in FIG. 2, static signals can be exchanged.

That is, this is one of the most important points of static type memory cells. The on-resistance ratios of Q ₃ /Q ₁ and Q ₄ /Q ₂ may be set to 1 to 2 so as not to cause an inversion phenomenon of stored information during a read operation. Note that since this value is closely related to the parasitic capacitance of the circuit, the signal voltage, etc., it goes without saying that it may be set to be slightly different from the above value.

The designs of other peripheral circuits 5C, 7C, 10C, etc. can also be easily realized using conventional static type circuit technology.

In Fig. 1, Q ₅ , which is the load MOS in Fig. 2,
Although there is no equivalent to Q ₆ , by adding a high-level compensation circuit that is commonly used these days as shown in Figure 3, Q ₇ and Q ₈ can function equivalent to Q ₅ and Q ₆ . The operation is also stable.

Note that the memory cell design method described in Figure 2 is already publicly known, and is known in the Y.
et al: A 40−as 144−Bitn−channel MOS−
LSI Memory: IEEE Journal of Solid-State
Ciranits, Vol.SC-4, No.5, Oct: 69”.

FIG. 4 shows operating waveforms of the main parts of the embodiment described above. An outline of the operation of the present invention will be explained below. First, when the row selection clock 1R is input,
A plurality of clocks necessary for internal operations, 12R clock shown here as a representative clock, is generated, and the signal of the part shown by the address signal 3 from the outside is taken inside and outputted as 14R and 14. Since the memory here is a multi-address system,
Address signals for rows and columns are multiplexed and input into 3 for each time period, and 3 is for row selection, ,
, , are column selection address signals to be described later. The hatched portions indicate the switching time periods of these signals, and the memory operation is not affected no matter what the signals are.

When 14R, 14 is output, 5R in Figure 1
operates and one of the word lines, for example _W0 , is selected and a signal is output. Next _, a minute signal is read out from the MC to B _0,0 . When 13R becomes low potential,
The detection circuit 6R operates and the small signals of B ₀ and ₀ are amplified. As mentioned earlier, this operation essentially completes the row selection operation.

On the other hand, when the column selection clock 1C is input, a plurality of clocks necessary for internal operations, 12C shown here as a representative, are generated as before. The subsequent operation is related to the present invention and is different from the row selection operation described above.

That is, when 3, , , . 5C then operates and multiple 15
(One of them is shown as a representative in FIG. 1) is selected. That is, 14C, 14
A signal is output to each of the 15 corresponding to , , , , , , , , , , , , , , , , , , . As a result, B ₀ , ₀ and I/O,
MOSTQ ₃ and Q ₄ are connected to each other, data is transferred, and this signal is transmitted to output 8 through 7C. is output as follows.

The above is a read operation, but the write operation is similarly performed continuously through the path 9→10C→I/O→B ₀ .

Conventional page mode operation was performed by keeping 1R input, turning 1C ON/OFF, and inputting an address in synchronization with this, but in the present invention described above, both 1R and 1C are input. It now operates in the same way as a so-called normal static memory in which only the addresses are switched sequentially, and as mentioned earlier, the cycle time can be made almost the same as the access time, resulting in a significant performance improvement. Improvements are possible.

Although the memory cell array shown in FIG. 1 is shown in a so-called folded bit line format in which the bit lines are folded, there are other types of memory cell arrays, such as bit lines on the left and right with the detection circuit 6R in between. It goes without saying that the present invention can be applied as is to any method in which the Furthermore, although the address multi-method in which the address is input divided into two has been described here, the idea of the present invention can be applied as is to a case where the number of divisions is even larger.

Now, it is generally known that static memory consumes more power than dynamic memory. In the former case, the main reason for this is that the memory cell itself consumes power, but another reason is that the peripheral circuitry also consumes a large amount of power. This is because static memories do not receive any external control clock, and therefore cannot take various measures to reduce power consumption. A problem similar to this occurs in the present invention, but since the present invention has fewer parts that perform static operations, this problem does not become as big as the one described above. In the present invention, there are the following methods for further reducing power consumption. In other words, in order to solve this problem, there is a method of automatically generating a control clock internally for use in reducing the power consumption of the circuit. An example will be described below.

In the page mode of the memory according to the present invention, the main change in the input signal is the address input, and it is only necessary to start a new operation when the address input changes. Therefore, it is sufficient to detect the changing portion of the address input and use this as the control clock.

FIG. 5 shows this embodiment. The address input may change from a low potential ("0") to a high potential ("1") or vice versa, and the configuration shown in the figure is such that both are detected.

In the figure, 3 is an address input, 201 is a delay circuit,
202 is an exclusive OR circuit, and 203 is an OR circuit. Although a plurality of circuits 201 and 202 are provided corresponding to the number of address input pins, they are omitted for simplicity. The operation is as shown in FIG. That is, input 3 is delayed by time τ by 201 and output to 204.
Since the exclusive OR outputs a signal only when the inputs are different, there are 3 in 205 as shown in the figure.
A signal appears when the signal changes. The pulse width at that time is approximately equal to τ, but this value is determined as appropriate depending on the operating speed of the memory. 2
03 outputs an output signal (2) when each address input changes.
05), and therefore, if even one of the address inputs changes, a signal will appear at 206. By using this output as a control clock, it is possible to reduce power consumption, and this pulse can also be used as a timing pulse for other speed-up purposes.

The exclusive OR and OR circuits used in FIG. It is also possible to configure the inverter circuit by connecting the inverter circuits in multiple stages.

The embodiments described above can be used not only in the present invention but also in ordinary static type memories.

[Brief explanation of drawings]

1 to 5 are explanatory diagrams of embodiments of the present invention.

Claims (1)

[Claims] 1 A first dynamic circuit having a dynamic memory cell for selecting a row in response to a first address, and a first dynamic circuit for selecting a row in response to a second address inputted with the row selected. The circuit to select and
A semiconductor memory comprising a circuit for reading or writing to a memory cell located at an intersection of a selected row and column, and operating in a page mode by switching the second address, the column selection circuit and the read or write circuit. A semiconductor memory characterized in that a circuit for the purpose of the invention is constructed using a static circuit.