JPS5829195A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To keep a cycle time and an access time almost equal and to improve the performance at page mode, by constituting a column selecting circuit and a circuit for readout or write with a static circuit. CONSTITUTION:The 1st dynamic circuit 5R having a dynamic memory cell to make row selection in response to the 1st address, a circuit 5C making column selection in response to the 2nd address inputted at the row selection, and a circuit which reads out a memory cell at cross points of the selected column and row and writes a data in the memory cell, are provided and the said 2nd address is changed over for the operation at the page mode. The column selection circuit 5C and the circuit for readout or write in the semiconductor memory like this are constituted with static circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION The invention relates to improving the performance of MO8 dynamic memories, particularly address multi-type memories.

A memory that divides the address input signal into two groups, all row selection and column selection, and inputs them for different time periods using the same bin group;
In the so-called Atsys multi-type semiconductor dynamic memory, the row selection address is fixed at 11 and only the column selection address is continuously changed to operate the memory in order to effectively shorten the access time and cycle time. It has a feature called ``Page Mode''. However, in order to perform dynamic operation, conventional memory requires a so-called precharge period to return the memory circuit to its initial state after memory operation, even in page mode, and the cycle time is approximately twice the access time. It had the disadvantage that it could not take full advantage of its functions.

The present invention aims to significantly improve performance in page mode by making all circuits operating in page mode static type, making the cycle time and access time almost the same.

FIG. 1 shows an embodiment of the present invention.

In the figure, IR, IC are external control clocks, and the former mainly controls row selection operations, and the latter controls column selection operations. Hereinafter, in the drawings, symbols with the suffix ``C'' will refer to the row selection operation, and symbols with the suffix ``C'' will refer to the column selection operation. 2R and 2C receive inputs from IR and IC, respectively, and are connected to a plurality of ties i7.2 which are necessary for internal operation of the memory. This is a circuit that generates pulses. In the figure, only typical output lines are shown, and the others are omitted. Mainly, the output of 2R is supplied to the row selection operation circuit, and the output of 2C is supplied to the output column selection operation circuit! not.

3 is input at Ato Vs. Normally, multiple inputs are required, but here, for simplicity, it is shown as being done by one person. It is input in synchronization with the row selection address 'FilR, and the column selection address is input in synchronization with the IC. This input is input to the atto V spatula circuits 4R and 4C, which are 12R and 12R, respectively.
Following the control of 120, 14R [Confirmation], 14a (Negation).

It is output at 14C, 14. 14R, 14R are row decoders and word lines Wo related to row selection operations.

The drive circuit of Ws, etc. is supplied to the unblocked 5R,
On the other hand, 14C and 14C are column decoders and column selection M OS Q
m-Q4 is supplied to a block 5C consisting of a control circuit 1Ij15 and a drive circuit. 100 is a part of the memory cell array, and a memory cell MC of, for example, IMO8 format is arranged at the intersection of the word 1iJWo -Wt (the bit lines Bo and Bol are omitted) and the word 1iJWo -Wt (the dummy word line of other words IIl is omitted). has been done. 6R is a detection circuit for detecting minute signals from the MC, which is composed of Ql*Qt and operates according to instructions from 13R. The signal detected and amplified by 6R is transmitted to input/output data #I10°Ilo through Qs = Q-, and then to amplifier 7C? The signal is output to the output terminal 8 via the signal line. Writing of 10,000 data is performed through the reverse path to the above-mentioned reading, with the data input from the data driver 9 being connected to Ilo and Ilo via the data driver 10C'i.

Now, of the operations described above, it can be said that roughly up to the detection amplification operation by 6R is related to the row selection operation, and the subsequent operations are related to the column selection operation.

The present invention is to statically operate the circuit related to the column selection operation with the subscript C in the above description. The biggest obstacle in making this static is the transmission and reception of signals between the bit line and the input/output data line, that is, the static transfer of Ilo and Ilo without destroying the signal on the bit line B0°B0 during read operation. In addition, when writing, it is possible to correctly transfer signals from Ilo and Ilo to B(+, Bo).

The 1FEZ diagram shows the configuration of a well-known 6MO8 type static memory cell. 103.1 in the same figure
04 is the bit line, 105 is the word line, 106 is the power supply 1
st-showing. As is clear from comparing Figures 1 and 2, Qs Qs ' * QtQt' * Qs
-Qs'eQ, a Q4'l 101Be
, 102 Be , 103 Ilo, 104-I
They are both compatible with loFi. Therefore, if the constants Qw -Q--Qs-Q- in FIG. 1 are designed in the same way as the conventionally known memory cell shown in FIG. 2, static signals can be sent and received.

In other words, the most important point of a static memory cell is −°
Tsururu. In order to prevent the inversion phenomenon of stored information from occurring during a read operation, the on-resistance ratio of Qs/Qr-Q-/Q, t may be set to 1 to 2. In addition,
Since this value is closely related to the amount of parasitic i in the circuit, the signal voltage, etc., it goes without saying that it is often possible to set it to be slightly different from the above value.

The design of other peripheral circuits 5C, 7C, IOC, etc. can also be easily realized using conventionally used static type circuit technology.

In FIG. 1, there is no equivalent to QssQ, which is the load MO8 in FIG.
, Qa corresponds to Qs - Qa, and the operation is stable.

Note that the memory cell design method described in FIG. 2 is already known, and is known as "Y.

TARUI etal :A 4O-as 1
44-Bitn-channel MC8-LSI
Memory: IEEE Journal o
f5olid-,3tateCiranits,
vol, 8C-4, No, 5. QCl: Familiar with 69J etc.

FIG. 4 shows operating waveforms of the main parts of the above-mentioned actual 1s example. An outline of the uninvented operation will be explained below. First, when the row selection clock IR is input, multiple clocks necessary for internal operations, 12H clock shown here as a representative, are generated, and all the signals of the 9 parts indicated by ■ of address signal 3 from the outside are internally and outputs 14R and 14Rt. Since the memory here is of the multi-address type, -3 is input with the address signal of row 0 column son (Jn divided into time zones and multiplexed), nl [F] is row selection, and (2).

■, ■, ■ are column selection address signals to be described later. The hatched portion indicates the switching time period of these signals, and no matter what kind of signal it is, it does not affect the memory operation.

When 14R and 14R are output, 5R in FIG. 1 is activated and one of the word lines, for example, Wo, is selected and output from the signal tube. Next, minute signals are read out from the MC to Bo and Bo. When 13R becomes a low potential, the detection circuit 6R operates and the minute signal of %Be*BO is amplified. As mentioned earlier, this operation essentially completes the row selection operation.

When the column selection clock IC is inputted, as before, a plurality of clocks necessary for internal operations, here representatively shown as 912C, are generated. The subsequent operation is related to the present invention and is different from the row selection operation described above.

In other words, if 3 ■, ■, ■, ■, ..., ■ are input continuously, 14C, 14C will correspond to ■, ■, ■, ■, ... ..., ■ are output continuously. Next, 5C operates, and 1 out of a plurality of 15 (1 out is shown as a representative in FIG. 1) is selected. That is, 14C, 14C ■, ■, ■, ■,...
..., each of the 15 corresponding to ■, ■, ■, ■,
・・・・・・A signal is sent to ■.

By this, Bow claw, Ilo, Ilo are MO8TQ
s = Connected via Q4, data is transferred, and this signal is transferred to output 8 through 7Ct- to the data stored in the location corresponding to the address signal of 3,
, . . . , ■ are output continuously.

Although the above is a read operation, the write operation is similarly performed continuously through the entire path 9→10C→I10→Bo.

Conventional page mode operation is
CtONloff This was done by inputting an address in synchronization with this, but in the present invention described above, it is all the same as a so-called normal static type memory in which only the address is sequentially switched up to 1 inputted in both 11'L and IC. As mentioned above, the cycle time can be made almost the same as the access time, which can significantly improve performance.

The nine memory cell array shown in FIG. Although the cylindrical housing of the present invention is shown in a folded form, that is, a so-called folded B-1ine type, other types of memory cell arrays, such as a type in which bit lines are arranged on the left and right sides across the detection circuit 6R1, can be used. There is no need to say that this is applicable. In addition, here we will discuss the address multi-method in which the address is divided into two parts and input.
Furthermore, even when the number of divisions is large, the idea of non-invention can be applied to the case.

Now, it is generally known that static memory consumes more power than dynamic memory. In the former case, the main reason for this is that the memory cell itself consumes power, but another reason is that the peripheral circuitry also consumes a large amount of power. This problem is caused by the fact that in static memory, no control clock is input from the outside, so various measures to reduce power consumption cannot be taken. A similar problem arises in non-invention,
In non-inventive devices, there are only a few parts that operate statically, so traps do not pose such a big problem as described above.

In the present invention, there are the following methods for further reducing power consumption. That is, in order to solve this problem, there is a method of automatically generating a control clock internally for use in reducing the power consumption of the circuit. An example will be described below.

#i in the page mode of the memory according to the present invention.

The main thing that changes in the input signal is the address input, and a new operation only needs to be started when the address input changes. Therefore, it is sufficient to detect the changing part of the address input and use it as the control clock.

FIG. 5 shows this embodiment. Address input changes from low potential (@0") to high potential (@1'), and
Although there are cases where the opposite is true, the configuration shown in the figure is such that both cases are detected.

In the figure, 3 is an address input, 201 is a delay circuit, 202 is an exclusive OR circuit, and 203 is an OR quotient. 201
, 202 are provided corresponding to the number of address input bins, but this is simply omitted.

The operation can be seen as shown in Figure (b). That is, the input of 3 is delayed by time r by 201 and output to 204. Since the exclusive OR outputs a signal only when the inputs are different, a signal appears in 205 when the signal 3 changes, as shown in j in the figure. The pulse width at that time is approximately equal to T, but this value is determined as appropriate depending on the operating speed of the memory. 203 takes the logical sum of the output signals (corresponding to 205) when each address input changes, so if even one of the address inputs changes, 2
A signal begins to appear at 06. By using this output as a control clock, it is possible to reduce power consumption, and this pulse can also be used as a timing pulse for other speed-up purposes.

The exclusive OR and OR circuits used in FIG. It is also possible to configure the inverter circuit by connecting ordinary inverter circuits in multiple stages.

The embodiments described above can be used not only in the invention but also in ordinary static type memories.

[Brief explanation of drawings]

Claims (1)

[Claims] 1. A ninth first dynamic circuit that has a dynamic memory cell and selects a row in response to a first address, and a ninth dynamic circuit that selects a row in response to a first address; A circuit that selects a column and a circuit that reads or writes to a memory cell at the intersection of the selected row and column? 1. A semi-integral memory comprising: a half-integral memory which operates in page mode by switching the second address, wherein a column selection circuit and a reading or writing circuit are constructed of static circuits.