JPH0528765A - Memory control circuit - Google Patents

Memory control circuit

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Publication number
JPH0528765A
JPH0528765A JP3202276A JP20227691A JPH0528765A JP H0528765 A JPH0528765 A JP H0528765A JP 3202276 A JP3202276 A JP 3202276A JP 20227691 A JP20227691 A JP 20227691A JP H0528765 A JPH0528765 A JP H0528765A
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circuit
data
address
operation
memory
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JP3202276A
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Japanese (ja)
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Yasuhiro Kawakami
康弘 川上
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Nec Home Electron Ltd
日本電気ホームエレクトロニクス株式会社
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Priority to JP3202276A priority Critical patent/JPH0528765A/en
Publication of JPH0528765A publication Critical patent/JPH0528765A/en
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Abstract

PURPOSE:To attain the high speed of a read.modifying.write operation of a DRAM with only a write access. CONSTITUTION:In the DRAM 1, the memory cell 9 designated by an address data from an address bus 17 is electrically connected to an internal data bus 3. The internal bus 3 is connected to an output buffer circuit 5 and to an arithmetic circuit 19. On a write time, the operation circuit 19 performs a logical operation for the external data from an input buffer circuit 7 and the operation result data is outputted on the internal bus 3 and it is written-in the same memory cell 9 on the DRAM 1 to control.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明はメモリ制御回路に係り、 The present invention relates to relates to a memory control circuit,
特に、ダイナミック・ランダム・アクセス・メモリ(以下DRAMと略す)から読み出したデータを演算加工して再びDRAMへ書込むメモリ制御回路の改良に関する。 Particularly to an improvement of the dynamic random access memory (hereinafter referred to as DRAM) to read data from the arithmetic processing writes again written to the DRAM memory controller.

【0002】 [0002]

【従来の技術】従来、この種のメモリ制御回路としては、例えば図4に示すように、メモリ回路としてのDR Conventionally, as a memory control circuit of this kind, for example, as shown in FIG. 4, DR as a memory circuit
AM1と、このDRAM1からの読み出しデータやDR And AM1, read data and DR from the DRAM1
AM1への書込みデータを伝送する内部データバス3 Internal data bus 3 to transmit the write data to AM1
と、DRAM1からの読み出しデータを外部の図示しないI/O回路へ出力する出力バッファ回路5と、そのI When an output buffer circuit 5 outputs the read data from the DRAM1 to the outside of the not-shown I / O circuitry, the I
/O回路からの書込みデータを内部データバス3へ入力する入力バッファ回路7を有して形成されていた。 / O write data from the circuit have been formed with an input buffer circuit 7 to be inputted to the internal data bus 3. DR DR
AM1は、コンデンサを主体とした記憶素子としての読み書き可能な多数のメモリセル9を有し、このメモリセル9に縦方向のアドレスデータを出力するロウデコーダ11を接続するとともに、そのメモリセル9へ横方向のアドレスデータを出力するカラムデコーダ13をセンスアンプ15を介して接続した一般的な構成を有している。 AM1 has a readable and writable large number of memory cells 9 as a storage element consisting mainly of capacitors, as well as connect the row decoder 11 for outputting a vertical address data to the memory cell 9, into the memory cell 9 the column decoder 13 for outputting a horizontal address data via the sense amplifier 15 has a general configuration in which connection.

【0003】このようなメモリ制御回路では、図5に示すように、アドレスバス17にアドレスデータが加えられ、ロウデコーダ11へのRAS(行アドレス・ストローブ)をアクティブ状態にしてからCAS(列アドレス・ストローブ)をアクティブ状態にすると、そのアドレスデータに基づきロウデコーダ11およびカラムデコーダ13で指定されたアドレスのデータが内部データバス3へ出力され、出力バッファ回路5へのリード・イネーブル(アウトプット・イネーブル)OEをアクティブにすると、内部データバス3から読み出しデータがI/O [0003] In such a memory control circuit, as shown in FIG. 5, the address data is added to the address bus 17, CAS (column address RAS (row address strobe) from the active state to the row decoder 11 strobe) and when in the active state, data of the address designated by the row decoder 11 and column decoder 13 based on the address data is outputted to the internal data bus 3, the read enable (output to the output buffer circuit 5 When the enable) OE active, read data from the internal data bus 3 is I / O
回路へ出力され、図示しないCPUの内部レジスタに取込んでから論理演算される。 Is output to the circuit, is logically calculated from at ipecac in an internal register of the CPU (not shown). その後、RASおよびCA Then, RAS and CA
Sがアクティブ状態のうちに入力バッファ回路7へのライト・イネーブルWEをアクティブ状態にすると、CP When S is a write enable WE to the input buffer circuit 7 in the active state to an active state, CP
UからI/O回路を介して入力された演算結果データが内部データバス3へ出力され、DRAM1の同じアドレスに書込まれる。 Operation result data inputted through the I / O circuit from U is outputted to the internal data bus 3, it is written to the DRAM1 the same address. この動作は一般的にリード・モディファイ・ライト動作と言われる。 This operation is generally referred to as read-modify-write operation. なお、上述したRAS、 In addition, RAS described above,
CAS、アウトプット・イネーブルOEおよびライト・ CAS, output enable OE and write
イネーブルWEは、図では各々負論理で示されているが、明細書では便宜上負論理の表示を省略する。 Enable WE is shown respectively in the negative logic in FIG omitted display convenience of negative logic in the specification.

【0004】 [0004]

【発明が解決しようとする課題】しかしながら、上述したメモリ制御回路では、リードサイクルでDRAM1から読み出したデータを出力バッファ回路5およびI/O [SUMMARY OF THE INVENTION However, in the memory control circuit described above, the output buffer circuit data read from the DRAM1 a read cycle 5 and I / O
回路を介してCPUの内部レジスタに取込み、CPUで論理演算した後、演算結果データをライトサイクルで入力バッファ回路7から内部データバス3を介してDRA After logical operation uptake in an internal register of the CPU, the CPU via the circuit, the operation result data from the input buffer circuit 7 at the write cycle through the internal data bus 3 DRA
M1の同じアドレスに書込むから、DRAM1に対してリードおよびライトの2回のアクセスが必要となり、出力バッファ回路5やCPUにおける動作分が遅延要素となってメモリ処理速度を低下させる難点がある。 Since writing to M1 same address, two accesses of read and write with respect DRAM1 is required, the operation amount of the output buffer circuit 5 and the CPU has a drawback of reducing the memory processing speed becomes delay element. なお、 It should be noted that,
図5において、アウトプット・イネーブルOEがノン・ 5, the output enable OE is non-
アクティブになってからライト・イネーブルWEがアクティブになるまでの期間tがCPUの動作期間である。 Period t from becoming active until the write enable WE is active is the operation period of the CPU.

【0005】本発明者は、DRAM1の動作について注意深く観察検討を行なった結果、DRAM1ではRAS [0005] The present inventor has conducted careful observation discussed DRAM1 operation, DRAM1 the RAS
およびCASをアクティブ状態にすると、アドレスデータに基づいて指定されたアドレスが内部データバス3に電気的に接続され、格納データが読み出しデータとして内部データバス3へ出力され、この状態で内部データバス3上へ書込データを加えると読み出しデータと書込データが衝突するものの、書込データでDRAM1の同じアドレス内を置き換え可能である点に着目して本発明を完成させた。 And when the CAS is active, the address specified on the basis of the address data is electrically connected to the internal data bus 3, stored data is outputted to the internal data bus 3 as read data, the internal data bus 3 in this state although impinging read data and write data the addition of write data onto, and completed the present invention by paying attention to the point it is possible replace the DRAM1 in the same address in the write data. 本発明はこのような従来の欠点を解決するためになされたもので、読み出しデータを演算して再度メモリ回路へ格納する動作を、メモリ回路に対するライトアクセス動作のみで実行可能であり、処理速度の速いメモリ制御回路を提供するものである。 The present invention has been made in order to solve the conventional drawbacks, the operation of storing the re-memory circuit by calculating the read data is capable of executing only a write access operation to the memory circuit, the processing speed and it provides a fast memory control circuit.

【0006】 [0006]

【課題を解決するための手段】このような課題を解決するために本発明は、読み書きデータを伝送する内部データバスと、読み書き可能な多数のメモリセルを有しアドレスデータを与えることによって当該アドレスに対応するメモリセルがその内部データバスに電気的に接続されるメモリ回路と、書込時にアドレスデータに対応するメモリセルからその内部データバスへ出力された出力データを論理演算し、かつ演算結果データをその内部データバスを介して上記メモリセルへ書込み制御する演算回路とを有して構成されている。 SUMMARY OF THE INVENTION The present invention in order to solve such a problem, the address by providing an internal data bus for transmitting write data, the address data has a large number of memory cells that can be read and written a memory circuit in which memory cells corresponding to is electrically connected to the internal data bus, the output data output from the corresponding memory cell to its internal data bus to the address data and logical operation in writing, and the operation result data via the internal data bus is configured to have an arithmetic circuit for write control to the memory cell. また、本発明では、複数の論理演算素子を組合せてその演算回路を形成し、この論理演算素子の組合せを選択回路で切換え選択可能に構成するとよい。 In the present invention, it may be a combination of a plurality of logical operation element to form the arithmetic circuit configured to switchably select a combination of the logical operation element by the selection circuit.

【0007】 [0007]

【作用】このような手段を備えた本発明では、メモリ回路にアドレスデータを与えると、そのアドレスデータに対応するメモリセルが内部データバスに電気的に接続されて格納データが内部データバスに読み出され、この読み出しデータが演算回路で論理演算されて内部データバスに出力され、読み出しデータに代ってその演算結果データが同じアドレスのメモリセルに書込まれる。 According to the present invention provided with such means, given the address data to the memory circuit, it stores the data memory cell corresponding to the address data is electrically connected to the internal data bus to read the internal data bus issued, the read data is output is a logical operation on the internal data bus in the arithmetic circuit, the operation result data is written into the memory cell of the same address in place of the read data. また、 Also,
演算回路の論理演算素子を選択回路で切換え選択する構成では、複数の論理演算が切換え実施される。 In the configuration in which switching selecting the logical operation element of the arithmetic circuit by the selection circuit, a plurality of logical operation is switched performed.

【0008】 [0008]

【実施例】以下本発明の実施例を図面を参照して説明する。 Example will be described with reference to the drawings the following examples the present invention. なお、従来例と共通する部分には同一の符号を付す。 Incidentally, parts in common with the conventional example are denoted by the same reference numerals. 図1は本発明に係るメモリ制御回路の一実施例を示すブロック図である。 Figure 1 is a block diagram showing an embodiment of a memory control circuit according to the present invention. 図1においてDRAM1は、記憶素子としての読み書き可能な多数のメモリセル9を配列し、アドレスバス17からのアドレスデータに基づきそれらメモリセル9へ縦方向のアドレスデータを出力するロウデコーダ11と、アドレスバス17からのアドレスデータに基づきそのメモリセル9へ横方向のアドレスデータを出力するカラムデコーダ13と、カラムデコーダ13とメモリセル9の間に配置されたセンスアンプ15 DRAM1 In Figure 1, a row decoder 11 which a number of memory cells 9 arranged readable and writable, and outputs a vertical address data to those memory cells 9 on the basis of the address data from the address bus 17 as a storage element, address a column decoder 13 which outputs a horizontal address data to the memory cells 9 on the basis of the address data from the bus 17, a sense amplifier 15 which is disposed between the column decoder 13 and the memory cell 9
を有し、内部データバス3に接続されている。 It has are connected to an internal data bus 3. このDR The DR
AM1は、アドレスバス17にアドレスデータが加えられたとき、ロウデコーダ11へのRASをアクティブ状態にすると、ロウデコーダ11で指定されたアドレス行の格納データがセンスアンプ15へ出力され、このセンスアンプ15で増幅された格納データが同じアドレス行に再度書込まれ、CASをアクティブ状態にすると、アドレスデータに基づきカラムデコーダ13が指定アドレスのデータを内部データバス3へ出力する。 AM1 when the address data is added to the address bus 17, when the RAS to the row decoder 11 to the active state, the data stored in the address line designated by the row decoder 11 is output to the sense amplifier 15, the sense amplifier amplified stored data 15 is written again written to the same address line, when the CAS into an active state, the column decoder 13 based on the address data and outputs the data at the specified address to the internal data bus 3.

【0009】そして、アドレスバス17に加えられたアドレスデータによって指定されたアドレスの各メモリセル9は、ゲート回路(図示せず)が開放されて内部データバス3に電気的に接続されることになる。 [0009] Each memory cell 9 of an address designated by the address data applied to the address bus 17, to the gate circuit (not shown) is electrically connected to the internal data bus 3 is opened Become. 内部データバス3は、出力バッファ回路5および演算回路19に接続されている。 Internal data bus 3 is connected to the output buffer circuit 5 and the arithmetic circuit 19. 出力バッファ回路5は、アウトプット・ Output buffer circuit 5, Output
イネーブルOEをアクティブにすると、内部データバス3上の読み出しデータを図示しないI/O回路を介して例えばCPU(図示せず)へ出力するバッファである。 When the enable OE to the active, a buffer for output via the I / O circuit (not shown) reads the data on the internal data bus 3, for example to the CPU (not shown).
演算回路19は、内部データバス3上の読み出しデータを一時的にラッチして内部データバス3から切り離するとともに、そのラッチされた読み出しデータと後述する入力バッファ回路7からの外部データを論理演算し、その演算結果データを内部データバス3上に出力するものであり、詳細は後述する。 Arithmetic circuit 19, together with that detach from the internal data bus 3 temporarily latching the read data on the internal data bus 3, the external data from the input buffer circuit 7 to be described later the latched read data and logic operations , and it outputs the operation result data on the internal data bus 3, details of which will be described later.

【0010】入力バッファ回路7は、演算回路19で演算させる外部データをCPUからI/O回路を介して入力するバッファであり、ライト・イネーブルWEをアクティブ状態にしたとき、実際に演算回路へその外部データが出力される。 [0010] Input buffer circuit 7, the external data to be computed by the computing circuit 19 is a buffer for input from the CPU via the I / O circuit, when the write enable WE is active, the actual to the arithmetic circuit external data is output. 演算回路19には例えば数ビットのレジスタからなり、選択回路21へ接続されているが詳細は後述する。 Consists of several bit register, for example, in the arithmetic circuit 19, are connected to the selection circuit 21 will be described in detail later. 演算回路19は、例えば図2に示すように、内部データバス3および入力バッファ回路7からの信号が並列的に加えられる2入力ORゲート19aおよびANDゲート19bと、ORゲート19aの出力が接続されたスリーステートバッファ19cと、ANDゲート19bの出力が接続されたスリーステートバッファ1 Arithmetic circuit 19, for example, as shown in FIG. 2, a two-input OR gate 19a and the AND gate 19b to which a signal from the internal data bus 3 and the input buffer circuit 7 is applied in parallel, the output of the OR gate 19a is connected a three-state buffer 19c has, three-state buffer 1 output of the aND gate 19b is connected
9dで形成されてなり、スリーステートバッファ19 It will be formed in 9d, three-state buffer 19
c、19dの出力が共通して内部データバス3に接続されている。 c, the output of 19d is connected to the internal data bus 3 in common.

【0011】内部データバス3に出力した演算結果データによって演算回路19が自己発振しないよう、演算回路19内にはラッチ回路を設けるが、図示を省略した。 The arithmetic circuit 19 by the calculation result data output to the internal data bus 3 is not to self-oscillating, providing the latch circuit in the arithmetic circuit 19, but not shown.
選択回路21は、I/O回路を介してCPUから入力された選択データを格納する例えば4ビットのレジスタであり、各ビットが演算回路19の論理演算素子の切換え端子となっている。 Selection circuit 21 is a register for example 4 bits for storing the input selected data from the CPU via the I / O circuits, each bit has a switching terminal of the logical operation element of the arithmetic circuit 19. 図2では、先頭の2ビットがスリーステートバッファ19c、19dの制御端に接続され、 In Figure 2, first two bits are connected three-state buffer 19c, to the control end of the 19d,
制御端が「H」レベルになったスリーステートバッファ19cの出力端が開放され、スリーステートバッファ1 The output terminal of three-state buffers 19c control terminal becomes "H" level is opened, three-state buffer 1
9dからの信号が内部データバス3へ出力するようになっている。 Signal from 9d is adapted to output to the internal data bus 3.

【0012】例えばレジスタ内が「1000」となるときには、図2の演算回路19のスリーステートバッファ19dの出力端が開放される。 [0012] When for example the register is "1000", the output terminal of the three-state buffer 19d of the arithmetic circuit 19 in FIG. 2 is opened. なお、図2はDRAM1 It should be noted that FIG. 2 is DRAM1
のある特定メモリセルからのデータについての演算処理を図示したものであり、DRAM1からの読み出しデータビット分の回路構成があることは言うまでもない。 There is an illustration of the calculation processing for data from a particular memory cell, there are also the circuit configuration of the read data bits from the DRAM1 of. 次に、上述した本発明のメモリ制御回路の動作を簡単に説明する。 Next, briefly described the operation of the memory control circuit of the present invention described above. 図5に示すようなアドレスデータが図1のアドレスバス17に加えられ、ロウデコーダ11へのRAS Address data as shown in FIG. 5 is applied to the address bus 17 of Figure 1, RAS to the row decoder 11
をアクティブ状態にしてからカラムデコーダ13へのC C and after the active state to the column decoder 13
ASをアクティブ状態にすると、ロウデコーダ11およびカラムデコーダ13で指定されたアドレスのデータが内部データバス3へ出力され、演算回路19内にラッチされる。 When the AS in the active state, data of the address designated by the row decoder 11 and column decoder 13 is outputted to the internal data bus 3, it is latched into the arithmetic circuit 19.

【0013】この状態で、RASおよびCASがアクティブ状態のうちに入力バッファ回路7へのライト・イネーブルWEをアクティブ状態にすると、CPUからI/ [0013] In this state, the RAS and CAS is the active state of the write enable WE to the input buffer circuit 7 in the active state, the CPU I /
O回路を介して入力された外部データが入力バッファ回路7から演算回路19へ加えられる。 External data input through the O circuits is applied from the input buffer circuit 7 to the calculation circuit 19. 演算回路19では、内部データバス3からの読み出しデータと入力バッファ回路7からの外部データが論理演算され、演算結果データが内部データバス3へ出力される。 The arithmetic circuit 19, external data from the read data and the input buffer circuit 7 from the internal data bus 3 is logic operation, operation result data are outputted to the internal data bus 3.

【0014】内部データバス3上では読み出しデータと演算結果データが衝突するが、読み出しデータは記憶素子としてのコンデンサにチャージされたデータであるから、演算回路19で駆動された演算結果データが打ち勝ち、DRAM1の同じアドレスに書込まれる。 [0014] While the read data and calculation result data on the internal data bus 3 collide, the read data is because a charge data in the capacitor as a storage element, the operation result data driven by the arithmetic circuit 19 overcomes, It is written to the DRAM1 of the same address. すなわち、リードモディファイライト動作がライトアクセスのみで実行される。 That is, the read-modify-write operation is performed only in a write access. このように、本発明のメモリ制御回路では、DRAM1に対してアドレス指定した後にリードアクセスするだけで、読み出しデータを論理演算した演算結果データをDRAM1の同じアドレスに書込めるから、DRAM1に対するアクセス回数が減少するし、出力バッファ回路5やCPUでの処理を必要としない分、 Thus, in the memory control circuit of the present invention, only read access after addressed to DRAM1, because put write the operation result data obtained by logical operation of the read data to the DRAM1 the same address, the number of accesses to the DRAM1 It decreases, amount that does not require processing in the output buffer circuit 5 CPU, Main
処理速度を高めることができる。 It is possible to increase the processing speed.

【0015】そして、CPUからの選択データを選択回路21に適当に変更格納すれば、演算回路19内での演算を切換え選択できる。 [0015] Then, if suitably modified stored in the selected circuit 21 to select data from the CPU, it can be selected to switch the operation in the arithmetic circuit 19. 上述した構成では、演算回路1 In the above-described configuration, the arithmetic circuit 1
9を複数の論理演算素子を組合せて形成し、選択回路2 9 was formed by combining a plurality of logical operation elements, the selection circuit 2
1に設定した選択データによってそれら論理演算素子を切換え選択する構成であったが、本発明では予め固定した回路構成の演算回路19を用いて選択回路21を省略することもできる。 Although a configuration of selecting switching them logical operation element by the selection data set to 1, the present invention may be omitted selecting circuit 21 by using an arithmetic circuit 19 of the pre-fixed circuit configuration. また、複数の論理演算素子を組合せて演算回路19を形成する場合にも、上述したORゲート19a、ANDゲート19b、スリーステートバッファ19c、、19d以外にも、NANDゲートやEX− Further, even when forming the operation circuit 19 by combining a plurality of logical operation elements, OR gate 19a as described above, the AND gate 19b, in addition to three-state buffer 19c ,, 19d, and NAND gate EX-
ORゲート等公知の論理演算素子を組合せて形成可能である。 It can be formed by combining OR gate such as a known logical operation element.

【0016】 [0016]

【発明の効果】以上説明したように本発明は、DRAM As described above, according to the present invention is, DRAM
等のメモリ回路に接続された内部データバスに演算回路を接続し、この演算回路では書込時にメモリ回路からその内部データバスへ出力された読み出しデータを論理演算し、その内部データバスを介してメモリセルへ書込み制御するようにしたから、読み出しデータを演算加工して再度メモリ回路へ格納する動作をライトアクセス動作だけで可能となる。 Connect the arithmetic circuit connected to an internal data bus in the memory circuit and the like, the read data output from the memory circuit in the write to the internal data bus in this arithmetic circuit a logic operation, via the internal data bus it is so arranged to write control to the memory cell, it is possible only by a write access operation to the operation of storing the re-memory circuit calculates processing the read data. そのため、メモリ回路に対するアクセス回数が減少し、処理速度を高めることができる。 Therefore, the number of accesses is reduced to the memory circuit, it is possible to increase the processing speed. また、複数の論理演算素子を組合せて演算回路を形成して選択回路で切換え選択する構成では、複数の論理演算を高速で切換え格納することができる。 Further, in the configuration in which switching selection by the selection circuit to form an arithmetic circuit by combining a plurality of logical operation element can be switched storing a plurality of logic operations at high speed.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明に係るメモリ制御回路の一実施例を示すブロック図である。 1 is a block diagram showing an embodiment of a memory control circuit according to the present invention.

【図2】図1中の演算回路および選択回路の一例を示す要部ブロック図である。 2 is a principal block diagram showing an example of an arithmetic circuit and a selection circuit in FIG.

【図3】図1のメモリ制御回路の動作を説明するタイムチャートである。 3 is a time chart for explaining the operation of the memory control circuit of Figure 1.

【図4】従来のメモリ制御回路を示すブロック図である。 4 is a block diagram showing a conventional memory control circuit.

【図5】図4のメモリ制御回路の動作を説明するタイムチャートである。 5 is a time chart for explaining the operation of the memory control circuit of Figure 4.

【符号の説明】 DESCRIPTION OF SYMBOLS

1 メモリ回路(DRAM) 3 内部データバス 5 出力バッファ回路 7 入力バッファ回路 9 記憶素子(メモリセル) 11 ロウデコーダ 13 カラムデコーダ 15 センスアンプ 17 アドレスバス 19 演算回路 19a 論理演算素子(ORゲート) 19b 論理演算素子(ANDゲート) 19c、19d 論理演算素子(スリーステートバッファ) 21 選択回路 1 memory circuit (DRAM) 3 Internal data bus 5 output buffer circuit 7 input buffer circuit 9 storage element (memory cell) 11 row decoder 13 column decoder 15 sense amplifiers 17 address bus 19 operation circuit 19a logical operation element (OR gate) 19b logical processing element (AND gate) 19c, 19d logical operation element (three-state buffer) 21 selection circuit

Claims (1)

  1. 【特許請求の範囲】 【請求項1】 読み書きされるデータを伝送する内部データバスと、 コンデンサを記憶素子とした読み書き可能な多数のメモリセルを有し、アドレスデータを与えることによって当該アドレスに対応する前記メモリセルが前記内部データバスに電気的に接続されるメモリ回路と、 書込時に前記アドレスデータに対応する前記メモリセルから前記内部データバスへ出力された出力データを論理演算し、演算結果データを前記内部データバスを介して前記メモリセルへ書込み制御する演算回路と、 を具備することを特徴とするメモリ制御回路。 Has an internal data bus for transmitting data to be [Claims 1] read and write, a number of memory cells that can be read and written in which the capacitor and the storage element, corresponding to the address by providing an address data wherein a memory circuit in which a memory cell is electrically connected to the internal data bus, the output data outputted to the internal data bus from the memory cell corresponding to the address data in the write logic operation, operation results for a memory control circuit, characterized by comprising an arithmetic circuit for write control to the memory cell via the internal data bus data. 【請求項2】 前記演算回路が複数の論理演算素子を組合せてなり、この論理演算素子の組合せを切換え選択する選択回路を有してなる請求項1記載のメモリ制御回路。 Wherein said arithmetic circuit is a combination of a plurality of logical operation elements, the memory control circuit of the logic combination of computing devices switching comprising a selection circuit for selecting claim 1.
JP3202276A 1991-07-18 1991-07-18 Memory control circuit Pending JPH0528765A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3202276A JPH0528765A (en) 1991-07-18 1991-07-18 Memory control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3202276A JPH0528765A (en) 1991-07-18 1991-07-18 Memory control circuit

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JPH0528765A true JPH0528765A (en) 1993-02-05

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