JPH0528765A - Memory control circuit - Google Patents

Abstract

PURPOSE:To attain the high speed of a read.modifying.write operation of a DRAM with only a write access. CONSTITUTION:In the DRAM 1, the memory cell 9 designated by an address data from an address bus 17 is electrically connected to an internal data bus 3. The internal bus 3 is connected to an output buffer circuit 5 and to an arithmetic circuit 19. On a write time, the operation circuit 19 performs a logical operation for the external data from an input buffer circuit 7 and the operation result data is outputted on the internal bus 3 and it is written-in the same memory cell 9 on the DRAM 1 to control.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control circuit,
In particular, the present invention relates to an improvement of a memory control circuit which processes data read from a dynamic random access memory (hereinafter abbreviated as DRAM) and rewrites the data in the DRAM.

[0002]

2. Description of the Related Art Conventionally, as a memory control circuit of this type, for example, as shown in FIG.
AM1 and read data and DR from this DRAM1
Internal data bus 3 for transmitting write data to AM1
And an output buffer circuit 5 for outputting read data from the DRAM 1 to an external I / O circuit (not shown) and its I / O circuit.
The input buffer circuit 7 for inputting write data from the / O circuit to the internal data bus 3 is formed. DR
The AM 1 has a large number of readable and writable memory cells 9 as storage elements mainly composed of capacitors. A row decoder 11 for outputting address data in the vertical direction is connected to the memory cells 9 and the memory cells 9 are connected to the memory cells 9. It has a general configuration in which a column decoder 13 that outputs address data in the horizontal direction is connected via a sense amplifier 15.

In such a memory control circuit, as shown in FIG. 5, address data is added to the address bus 17 to activate the RAS (row address strobe) to the row decoder 11 and then the CAS (column address). When the strobe) is activated, the data of the address specified by the row decoder 11 and the column decoder 13 is output to the internal data bus 3 based on the address data, and the read enable (output. (Enable) When OE is activated, read data from the internal data bus 3 becomes I / O.
The data is output to the circuit and is taken into an internal register of a CPU (not shown) and then logically operated. Then RAS and CA
When the write enable WE to the input buffer circuit 7 is activated while S is active, CP
The operation result data input from U via the I / O circuit is output to the internal data bus 3 and written in the same address of the DRAM 1. This operation is generally called a read-modify-write operation. In addition, the above-mentioned RAS,
CAS, output enable OE and write
Each of the enable WEs is shown in the negative logic in the drawing, but in the specification, the display of the negative logic is omitted for convenience.

[0004]

However, in the above-mentioned memory control circuit, the data read from the DRAM 1 in the read cycle is output to the output buffer circuit 5 and the I / O.
After being taken into the internal register of the CPU via the circuit and being logically operated by the CPU, the operation result data is DRA from the input buffer circuit 7 via the internal data bus 3 in a write cycle.
Since data is written to the same address of M1, it is necessary to access the DRAM 1 twice, that is, read and write, and the operation in the output buffer circuit 5 and the CPU becomes a delay element, which causes a problem of reducing the memory processing speed. In addition,
In FIG. 5, the output enable OE is non-
The period t from the activation to the activation of the write enable WE is the operating period of the CPU.

As a result of careful observation and examination of the operation of the DRAM 1, the present inventor found that the DRAM 1
When and CAS are made active, the address designated based on the address data is electrically connected to the internal data bus 3 and the stored data is output to the internal data bus 3 as read data. The present invention has been completed by noting that read data and write data collide when write data is added to the upper part, but the write data can replace the same address in the DRAM 1. The present invention has been made in order to solve such a conventional drawback, and the operation of calculating read data and storing it again in the memory circuit can be executed only by the write access operation to the memory circuit. A fast memory control circuit is provided.

[0006]

In order to solve the above problems, the present invention has an internal data bus for transmitting read / write data and a large number of readable / writable memory cells to provide address data. And a memory circuit electrically connected to the internal data bus of the memory cell and the output data output from the memory cell corresponding to the address data to the internal data bus at the time of writing, and the operation result And an arithmetic circuit for controlling writing of data to the memory cell via its internal data bus. Further, in the present invention, it is preferable that a plurality of logical operation elements be combined to form an operation circuit thereof, and that the combination of the logical operation elements be switched and selected by the selection circuit.

[0007]

In the present invention having such means, when address data is applied to the memory circuit, the memory cell corresponding to the address data is electrically connected to the internal data bus and the stored data is read to the internal data bus. The read data is logically operated by the operation circuit and output to the internal data bus, and the operation result data is written in the memory cell of the same address instead of the read data. Also,
In the configuration in which the logical operation element of the arithmetic circuit is switched and selected by the selection circuit, a plurality of logical operations are switched and implemented.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. The same parts as those in the conventional example are designated by the same reference numerals. 1 is a block diagram showing an embodiment of a memory control circuit according to the present invention. In FIG. 1, the DRAM 1 has a row decoder 11 that arranges a large number of readable and writable memory cells 9 as storage elements, outputs vertical address data to the memory cells 9 based on address data from an address bus 17, and an address decoder 11. A column decoder 13 that outputs horizontal address data to the memory cell 9 based on address data from the bus 17, and a sense amplifier 15 arranged between the column decoder 13 and the memory cell 9.
And is connected to the internal data bus 3. This DR
When the address data is applied to the address bus 17, the AM1 activates the RAS to the row decoder 11 to output the stored data of the address row designated by the row decoder 11 to the sense amplifier 15. When the stored data amplified in 15 is rewritten in the same address row and CAS is activated, the column decoder 13 outputs the data of the designated address to the internal data bus 3 based on the address data.

Each memory cell 9 of the address designated by the address data applied to the address bus 17 is electrically connected to the internal data bus 3 by opening the gate circuit (not shown). Become. The internal data bus 3 is connected to the output buffer circuit 5 and the arithmetic circuit 19. The output buffer circuit 5 is
It is a buffer that outputs read data on the internal data bus 3 to, for example, a CPU (not shown) via an I / O circuit (not shown) when the enable OE is activated.
The arithmetic circuit 19 temporarily latches the read data on the internal data bus 3 and disconnects it from the internal data bus 3, and logically operates the latched read data and external data from the input buffer circuit 7 described later. The calculation result data is output to the internal data bus 3, which will be described in detail later.

The input buffer circuit 7 is a buffer for inputting external data to be calculated by the arithmetic circuit 19 from the CPU via the I / O circuit, and when the write enable WE is activated, the input buffer circuit 7 actually outputs the data to the arithmetic circuit. External data is output. The arithmetic circuit 19 is composed of a register of several bits, for example, and is connected to the selection circuit 21. The details will be described later. As shown in FIG. 2, for example, the arithmetic circuit 19 is connected to a 2-input OR gate 19a and an AND gate 19b to which signals from the internal data bus 3 and the input buffer circuit 7 are applied in parallel, and an output of the OR gate 19a. Three-state buffer 1 connected to the output of AND gate 19b
The three-state buffer 19 is formed of 9d.
The outputs of c and 19d are commonly connected to the internal data bus 3.

A latch circuit is provided in the arithmetic circuit 19 so that the arithmetic circuit 19 does not self-oscillate due to the arithmetic result data output to the internal data bus 3, but the illustration is omitted.
The selection circuit 21 is, for example, a 4-bit register that stores selection data input from the CPU via the I / O circuit, and each bit serves as a switching terminal of a logical operation element of the operation circuit 19. In FIG. 2, the first two bits are connected to the control ends of the three-state buffers 19c and 19d,
The output end of the three-state buffer 19c whose control end has become "H" level is opened, and the three-state buffer 1
The signal from 9d is output to the internal data bus 3.

For example, when the register becomes "1000", the output terminal of the three-state buffer 19d of the arithmetic circuit 19 of FIG. 2 is opened. 2 shows the DRAM 1
Needless to say, there is a circuit configuration for data bits read from the DRAM 1, which is an illustration of the arithmetic processing for data from a specific memory cell. Next, the operation of the memory control circuit of the present invention described above will be briefly described. Address data as shown in FIG. 5 is added to the address bus 17 of FIG.
To the column decoder 13 after activating
When AS is activated, the data at the address designated by the row decoder 11 and the column decoder 13 is output to the internal data bus 3 and latched in the arithmetic circuit 19.

In this state, when the write enable WE to the input buffer circuit 7 is activated while RAS and CAS are active, the CPU outputs I / O.
External data input through the O circuit is added to the arithmetic circuit 19 from the input buffer circuit 7. In the arithmetic circuit 19, the read data from the internal data bus 3 and the external data from the input buffer circuit 7 are logically operated, and the operation result data is output to the internal data bus 3.

On the internal data bus 3, the read data and the operation result data collide with each other. However, since the read data is the data charged in the capacitor as the storage element, the operation result data driven by the operation circuit 19 overcomes, It is written to the same address in DRAM1. That is, the read modify write operation is executed only by the write access. As described above, in the memory control circuit of the present invention, the operation result data obtained by logically operating the read data can be written to the same address of the DRAM 1 only by addressing the DRAM 1 and then performing the read access. Since it does not require processing by the output buffer circuit 5 and the CPU,
The processing speed can be increased.

If the selection data from the CPU is appropriately changed and stored in the selection circuit 21, the operation in the operation circuit 19 can be switched and selected. In the configuration described above, the arithmetic circuit 1
9 is formed by combining a plurality of logical operation elements, and the selection circuit 2
Although the logic operation elements are switched and selected according to the selection data set to 1, the selection circuit 21 may be omitted by using the operation circuit 19 having a fixed circuit configuration in the present invention. Also, when the arithmetic circuit 19 is formed by combining a plurality of logical operation elements, in addition to the above-described OR gate 19a, AND gate 19b, three-state buffers 19c, and 19d, a NAND gate or EX-
It can be formed by combining well-known logical operation elements such as an OR gate.

[0016]

As described above, the present invention is a DRAM.
An arithmetic circuit is connected to an internal data bus connected to a memory circuit such as a logical circuit, and the arithmetic circuit logically operates read data output from the memory circuit to the internal data bus at the time of writing, and the arithmetic operation is performed via the internal data bus. Since the write control to the memory cell is performed, the operation of processing the read data and storing it in the memory circuit again can be performed only by the write access operation. Therefore, the number of accesses to the memory circuit is reduced and the processing speed can be increased. Further, in a configuration in which a plurality of logical operation elements are combined to form an arithmetic circuit and the selection circuit switches and selects, a plurality of logical operations can be switched and stored at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a memory control circuit according to the present invention.

2 is a principal block diagram showing an example of an arithmetic circuit and a selection circuit in FIG. 1. FIG.

FIG. 3 is a time chart explaining the operation of the memory control circuit in FIG.

FIG. 4 is a block diagram showing a conventional memory control circuit.

5 is a time chart explaining the operation of the memory control circuit of FIG.

[Explanation of symbols]

1 Memory Circuit (DRAM) 3 Internal Data Bus 5 Output Buffer Circuit 7 Input Buffer Circuit 9 Storage Element (Memory Cell) 11 Row Decoder 13 Column Decoder 15 Sense Amplifier 17 Address Bus 19 Operation Circuit 19a Logical Operation Element (OR Gate) 19b Logic Arithmetic element (AND gate) 19c, 19d Logical arithmetic element (three-state buffer) 21 Selection circuit

Claims (2)

[Claims] 1. An internal data bus for transmitting data to be read and written, and a large number of readable and writable memory cells each having a capacitor as a storage element, wherein the memory cell corresponding to the address by giving address data is the memory cell. A memory circuit electrically connected to the internal data bus and a logical operation of the output data output from the memory cell corresponding to the address data to the internal data bus at the time of writing, and the operation result data being the internal data bus. An arithmetic circuit for controlling writing to the memory cell via the memory control circuit. 2. The memory control circuit according to claim 1, wherein the arithmetic circuit is formed by combining a plurality of logical operation elements, and has a selection circuit for switching and selecting the combination of the logical operation elements.