JPH04105298A - Semiconductor memory integrated circuit - Google Patents

Abstract

PURPOSE:To enable high-speed writing operation by outputting information from a data register to an output buffer with a coincidence signal from an address comparing circuit. CONSTITUTION:This semiconductor memory integrated circuit is equipped with a switching circuit 9, a comparing circuit 10, an address register 11, and a data register 12. Then when a write signal is inputted, >=1 couple of an address input and a data input are inputted to the address register 11 and data register 12 and the address input at the time of a read is compared with inputted address information by a comparing circuit 10; and a data switching circuit 9 switches and outputs the information in the data register 12 to the output buffer 6 with the coincidence signal from the comparing circuit 10 instead of data from a cell 1. Consequently, the high-speed writing becomes possible.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor memory integrated circuits.

[Conventional technology]

The conventional semiconductor memory integrated circuit, as shown in FIG.
An X, Y address selection circuit 2-3 for selecting one memory cell in the memory cell array 1, and a write/write circuit 4 for reading the contents of the selected memory cell and writing input data. , a control circuit 5 for controlling the read/write circuit 4 based on an external control signal and switching between write and read operations, and an output buffer 6 for outputting data read from the memory cells to the outside. , X, and Y address buffers 7.8.

Furthermore, in bipolar memory integrated circuits, a circuit called a PNPN memory cell is generally used as a memory cell, but it takes a long time to write, and generally requires twice the access time for reading. .

[Problem to be solved by the invention]

In such conventional semiconductor memory integrated circuits, the data read from the memory cell is directly output from the data buffer, so when writing data, the written state is maintained until the contents of the memory cell are completely rewritten. I needed to. This is because the potential of the cell is not at a sufficient level immediately after the contents of the cell are inverted, so it cannot be read. In particular, in a memory using PNPN cells, writing requires twice as much time as reading. Therefore, in a system using this memory integrated circuit, there is a problem that the tl[ of the system is limited because the system is designed with read [IT] and write [2T] based on the read time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory integrated circuit which solves the above-mentioned problems and enables high-speed writing.

[Means to solve the problem]

The structure of the semiconductor memory integrated circuit of the present invention includes one or more sets of address registers and data registers that take in address input and data input when a write signal is input, and an address input at the time of read and an address taken into the register at the time of write. and a data switching circuit that outputs the information in the data register to the output buffer instead of the data from the memory cell in response to a match signal from the comparison circuit. .

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor memory integrated circuit according to an embodiment of the present invention.

In FIG. 1, the memo IJ I cell of this embodiment is PN
The memory cell is a PN memory cell, and the write time is 3 nsec until the cell potential is reversed and 5 nsec until the cell potential is stabilized.

In FIG. 1, the difference between this embodiment and the conventional one is the switching circuit 9. Comparison circuit 10. Address register 11. Data register 12. , and the other parts are the second
It is similar to the figure.

Now, when writing, the write control signal becomes active and passes through the read/write circuit 4 to the memory cell array 1.
Writing is performed to one selected cell inside. At the same time, an address is written to the address register 11 and data is written to the data register 12. The writing time for the register is determined so that writing is completed and reading becomes possible 5 nsec after the cell potential is reversed. 5ns
After ec, the write control signal becomes inactive, and the contents of the memory cell are read out through the read-write circuit 4 and input to the switching circuit 9. Further, since the address input is unchanged from the time of writing, the address of the contents of the register entered in the comparator circuit 10 and the address input match, and a signal indicating the match is input to the switching circuit 9. The switching circuit 9 outputs the input from the data register 12 to the output buffer 6 in response to the match signal.

As mentioned above, it appears from the outside that writing can be done in 3 nS. Conventional memory integrated circuits cannot be used with the same write time because the output is not determined until the cell stabilizes.

Furthermore, even if the memory cell at the address is to be read until the cell is stabilized, in this embodiment, by reading from the data register 2, the data can be read in the normal access time.

FIG. 3 is a block diagram of a semiconductor memory integrated circuit according to another embodiment of the present invention. In FIG. 3, in this embodiment, when a write signal is input into the control circuit 5' of the first embodiment, a control signal is activated after the cell is inverted until the cell is stabilized. A generating circuit is added, and this control signal is input to a comparison circuit 10 for comparison and a switching circuit 9, and the comparison circuit 10 and switching circuit 9 operate only while the cell is stable after inversion.

In this embodiment, memory cell
Even when the contents of an array or register are destroyed,
The possibility of malfunction is reduced.

In FIG. 3, the parts other than the control circuit 5' are the same as in FIG. 1, and are given the same numbers.

〔Effect of the invention〕

As described above, the present invention provides one or more sets of address registers and data registers that take in address inputs and data inputs when a write signal is input to a memory integrated circuit, and one or more sets of address registers and data registers that take in address inputs when reading and registers when writing. By providing a comparison circuit that compares the fetched address information and a data switching circuit that outputs information from the data register to the output buffer instead of data from the memory cell based on a match signal from the comparison circuit, By outputting the contents of the data register until the potential of the memory cell written by the short write signal stabilizes, the effect of high-speed writing when viewed from the outside is achieved.

9. Switching circuit, 10. Comparison circuit, 11. Address register, 12. Data register.

Claims (1)

[Claims] at least one set of address registers and data registers that store address inputs and data inputs in a write state; a comparison circuit that compares the contents of the address register and the address input in a read state; and an output from the data register and a memory. 1. A semiconductor memory integrated circuit comprising: a circuit for switching between an output from a cell and a match signal from the comparison circuit.