JP2509275B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device, and more particularly to a STRAM device configured to generate a write signal (pulse) in a chip in response to an external clock and a write command signal. A memory cell array and a read cycle and a write cycle of the memory cell array, which are operably connected to the memory cell array for the purpose of enabling the input / output terminals to be shared and reducing the circuit scale of the device. A first latch circuit that receives a control signal indicating one of them and latches the control signal in response to either a rising edge or a falling edge of an external clock signal, and is operably connected to the memory cell array. And receive the write data,
A second latch circuit that latches the write data in response to the other of the rising edge and the falling edge of the external clock signal, and is operably connected to the memory cell array and the first latch circuit. A write signal generating circuit that supplies a write signal to the memory cell array when the control signal latched by the latch circuit of FIG.
A write data input terminal and a read data output terminal, which are used for writing and reading data with the memory cell array, are commonly connected.

[Industrial applications]

The present invention relates to a semiconductor memory device, and more particularly to a self-timed random access memory (hereinafter referred to as a self-timed random access memory configured to generate a write signal (pulse) in a chip in response to an external clock and a write command signal. STRA
(Referred to as M) device.

A commonly known static RAM (SRAM) is a memory configured to write data to a memory cell selected by address data from the outside in response to a write signal (pulse) from the outside as well. Is. In this case, since the address data and the write pulse are applied asynchronously, it is necessary to adjust the application timing of the write pulse outside the chip when writing the data. However, in practice, it is relatively difficult to adjust such an application timing outside, and therefore it is generally performed to allow a certain time margin for the timing. Therefore, such an SRAM has a disadvantageous aspect when faced with a demand for higher speed. A device recently developed in view of such disadvantages is the above-mentioned STRAM.

[Conventional technology]

FIG. 6 shows an example of a conventional structure of the STRAM device described above, and FIG. 7 shows its operation timing.

In FIG. 6, 60 is a normal static memory cell array, 61 to 64 are address data ADD, a low active chip selection signal ▲ ▼, and a low active write command signal ▲ in response to an external clock CLK, respectively.
▼, register that latches write data D _IN , 65 is an AND gate that responds to the inverted signal of the output of register 62 and the output signal of register 63, 66 is the inverted signal of the output of register 62 and the inverted signal of the output of register 63 AND gate in response to and, 67 is a circuit for generating a write pulse WP in response to the clock CLK when the output signal WS of the AND gate 66 is at "H" level, and 68 and 69 are tristate buffers, It has a function of passing the write data D _IN and the read data D _OUT in response to the write pulse WP and the read control signal OE from the AND gate 65, respectively. Also, from T1
T4, T5a and T5b represent the terminals of the chip.

In the configuration shown in FIG. 6, the chip selection signal ▲
The STRAM device becomes active when ▼ changes to the "L" level and is latched in the register 62 due to the change in the level of the external clock CLK (the rising time in the example of FIG. 7). Write command signal ▲ ▼ simultaneously with chip selection signal ▲ ▼
Is input, the level change of the external clock CLK (7th
In the example shown in the figure, the register 63 corresponding to the write command signal ▲ ▼ is synchronized with the rising time) to the “H” level or the “L” level.
Level is latched. Specifically, write command signal ▲
Output signal OE of AND gate 65 when ▼ is “H” level
Becomes "H" level, the tri-state buffer 69 functions, and the read operation is performed. Conversely, write command signal ▲
Output signal WS of AND gate 66 when ▼ is “L” level
Becomes "H" level, the write pulse generation circuit 67 generates the write pulse WP, the tri-state buffer 68 functions, and the write operation is performed.

That is, external clock CLK and write command signal ▲
In response to .tau., The read cycle t _R and the write cycle t _W are automatically defined in the chip every cycle of the clock (see FIG. 7). The hatched portion in FIG. 7 means that the state is “undefined”.

[Problems to be Solved by the Invention]

In the conventional STRAM described above, at the end of the read cycle t _R , a command indicating that “reading is prohibited” at the time when the clock CLK rises (the AND gate 65 in the example of FIG. 6).
(Corresponding to the output signal OE of), the data output is actually invalid only after a slight delay from the rising time due to a slight delay in circuit operation (see FIG. 7). .

As a result, as shown in FIG. 7, the write cycle
At the time when the clock CLK rises at t _W (at the time t _{0 in} the example of FIG. 7), the state of data output is still maintained. In this case, the memory cell array 60
The data from is output to the terminal T5b via the buffer 69 and taken out to the outside. However, at the same time point t ₀ , external write data D
_IN is taken in via the terminal T5a.

That is, according to the conventional device of FIG. 6, when the clock CLK rises in the write cycle t _W (at time t ₀ ).
In this case, both the "data output" state and the "data input" state exist. Therefore, if the data input path (data input terminal T5a) and the data output path (data output terminal T5b) are made common, there is a disadvantage that the input data and the output data collide with each other. As shown in the configuration of FIG. 6, the data input terminal T5a and the data output terminal T5b have to be separated.

However, in a general semiconductor device having a chip form, it is known that the space occupied by the terminals on the chip is extremely larger than the space occupied by other integrated circuits on the chip. This means that the circuit scale as a device becomes large, which is not preferable. Therefore, if possible, it is preferable that the data input / output terminals can be made common without causing the inconvenience that the data input / outputs collide with each other.

The present invention was created in view of the above problems in the prior art, and an object of the present invention is to provide a semiconductor memory device in which data input / output terminals can be shared and the circuit scale as a device can be reduced. .

[Means for solving the problem]

The problem in the above-mentioned conventional technique is to devise the circuit configuration so that the state of “data output” and the state of “data input” do not exist at any time,
Can be resolved.

Therefore, according to the present invention, as shown in FIGS. 1 and 2, there is provided a semiconductor memory device for receiving an external clock signal (CLK) having a rising edge and a falling edge, the memory cell array (4, 20) and a control signal (▲ ▼) that is operably connected to the memory cell array and indicates either the read cycle or the write cycle of the memory cell array, and the rising edge and the falling edge of the external clock signal. A first latch circuit (1,23) for latching the control signal in response to one of the edges, and operably connected to the memory cell array for receiving write data (D _IN ) and receiving the external clock A second latch time for latching the write data in response to the other of the rising edge and the falling edge of the signal. (2,
6; 10,24), and the memory cell array and the first latch circuit are operably connected to the memory circuit when the control signal latched by the first latch circuit indicates the write cycle. A write signal generation circuit (3; 27, 28, 26) for supplying a write signal (WP) to the cell array, and a write data input terminal and read for writing and reading data with the memory cell array. There is provided a semiconductor memory device having a data output terminal commonly connected.

[Work]

According to the above configuration, the write command signal ▲ ▼
External clock level change in write cycle t _W ,
That is, when one of the rising and falling levels changes, t _A
(In the illustrated example, at the rising edge), while the write data D _IN is latched at the other level change t _B of the external clock in the write cycle t _W (in the illustrated example, the falling edge). It has become.

As a result, even if the data output state is still maintained when the write command signal ▲ ▼ is latched, the write data is still
Since D _IN is not latched, the input / output terminal 5 can be dedicated as “for output”. Since the state of data output is completed at the time when the write data D _IN is latched, the input / output terminal 5 can be dedicated for “input”. Therefore, the data input / output terminals can be made common without causing the inconvenience that the input data and the output data collide with each other. This contributes to the reduction of the circuit scale of the device.

The details of other structural features and operations of the present invention will be described with reference to the accompanying drawings and embodiments described below.

〔Example〕

FIG. 2 is a block diagram showing the structure of an STRAM device as an embodiment of the present invention.

In FIG. 2, T1 to T5 are terminals of the chip, and 20 is a normal static type memory cell array. Note that the memory cell array referred to here includes both an original cell array in which memory cells are arranged at intersections of a plurality of word lines and bit lines, and a peripheral circuit for accessing the memory cells. Shall be included. Address data ADD, low active chip select signal ▲ ▼, low active write command signal ▲ to terminals T1 to T4 respectively
▼, clock CLK is input. Further, the terminal T5 is used to read (read data D _OUT ) and write (write data) data with the memory cell array 20.
D _IN ) represents a common input / output terminal.

A register 21 is interposed between the terminal T1 and the memory cell array 20, and the register 21 has a function of latching the address data ADD in response to the clock CLK. Specifically, the clock CLK is "H". The address data at the time of the level is held and supplied to the memory cell array 20. A register 22 is connected to the terminal T2, and the register 22 has a function of holding and outputting the chip selection signal ▲ ▼ when the clock CLK is at "H" level. Similarly, register 23 is connected to terminal T3.
, And the register 23 has a function of holding and outputting the write command signal ▲ ▼ when the clock CLK is at the "H" level.

In addition, 2 is provided between the memory cell array 20 and the input / output terminal 15.
System, that is, for data writing and data reading,
Register 24 is connected to the system for data writing.
Also, a tri-state buffer 28 is interposed, and a tri-state buffer 29 is interposed in a data reading system. An inverter is connected between this register 24 and terminal T4.
The inverter 10 has a function of inverting the external clock CLK input from the terminal T4 into a negative-phase clock (). Therefore, the register 24 stores the write data when this negative phase clock ▲ ▼ is at "H" level.
D _IN is latched and supplied to the tri-state buffer 28. This tri-state buffer 28 has write data D _IN sent through the register 24 when a write pulse WP from a write pulse generating circuit 27 described later is at “H” level.
Is supplied to the memory cell array 20. Similarly, the tri-state buffer 29 reads the data read from the memory cell array 20 when the read control signal OE from the AND gate 25 described later is at the “H” level.
_It has the function of supplying to terminal T5 as _OUT .

25 is an AND gate that outputs the above-mentioned read control signal OE in response to the inverted signal of the output of the register 22 and the output signal of the register 23, and 26 is the inverted signal of the output of the register 22 and the inverted signal of the output of the register 23. In response to, an AND gate that outputs the write control signal WS is shown. Write pulse generation circuit 27
Means that when the write control signal WS is at the “H” level, the write pulse W described above is responded to in response to the rising edge of the reverse phase clock ▲ ▼ described above, that is, the falling edge of the external clock CLK.
It has the function of generating P.

Next, a third example of the configuration of the write pulse generation circuit will be described.
This will be described with reference to the drawings.

The write pulse generating circuit shown here includes a delay circuit 31 that delays the negative-phase clock ▲ ▼ by a predetermined time and outputs it as a signal S1, and an inverter that inverts the signal S1.
32 and an output of the inverter 32 and a reverse-phase clock ▲ ▼
And AND gate 33 which outputs a signal S2 in response to the signal S2 and an AND gate 34 which outputs a write pulse WP in response to the signal S2 and the above-mentioned write control signal WS.

Next, a specific configuration example of the data input / output unit in FIG. 2 will be described with reference to FIG. Note that FIG. 4 shows only the structure of one column of the memory cell array for the sake of simplification of description.

In FIG. 4, 41 is a peripheral circuit for row access that selects one of the word lines WL in response to the address data ADD, and 42 is a bit line pair BL, ▲ in response to the address data ADD.
A column access peripheral circuit for selecting any one of the pairs is shown. On the other hand, 50 is a memory cell having, for example, a flip-flop configuration, and 51 and 52 are the word lines.
Corresponding bit line ▲ ▼, BL and memory cell 5 when selecting WL
Transistor for transfer gate for reading / writing data from / to 0, 53 and 54 are transistors as load, and 55 and 56 are bit line ▲ by selecting control from the column access peripheral circuit respectively.
Between ▼ and data line ▲ ▼, bit line BL and data line DB
Transistors connecting between and are shown respectively. The memory cell 50 and the transfer gate transistor
One bit is composed of 51 and 52.

Transistors 57 and 58 that operate at the time of writing data are connected to the data lines ▲ ▼ and DB, respectively. That is, at the gate of the transistor 57, the write data D _IN input from the input / output terminal T5 is fed to the inverter 43,
It is supplied via the inverter 44 and the AND gate 28a (gate signal D _IN ), and the transistor 5
The write data D _IN input from the input / output terminal T5 is input to the gates of the inverters 43, 44 and 45.
And is supplied via the AND gate 28b (gate signal ▲ ▼). In addition, AND gate
28a and 28b are controlled by the aforementioned write pulse WP.

The data on the data line ▲ ▼, DB is the sense amplifier 59
At the input / output terminal T5 via the output buffer 60 and the tri-state buffer 29 as read data D _OUT .

The operation of the STRAM device shown in FIGS. 2-4 will now be described with reference to the timing diagram of FIG.

First, "L" level chip select signal ▲ ▼
And write command signal ▲ ▼ to terminal T3 in this state.
And the clock CLK is applied to the terminal T4, the read cycle t _R or the write cycle t _W is defined in synchronization with the rising edge of the clock CLK.

(1) At the read cycle t _{R When} the “H” level is input to the write command signal ▲ ▼ and the clock CLK rises, the output signal OE of the AND gate 25 goes to the “H” level. Buffer 29
Functions and the read operation is started. However, in reality, due to the delay in the operation of the memory read circuit, the data output becomes effective only when the clock CLK rises a little later (see FIG. 5).

At the end of the read cycle, that is, the start of the write cycle t _W (time t ₁ ), the state of data output is still maintained due to a slight delay in circuit operation. At this time, the data from the memory cell array 20 is output to the input / output terminal T5 via the buffer 29,
It is taken out. That is, the input / output terminal T5 is used as "for output".

(2) At write cycle t _W When “L” level is input to the write command signal ▲ ▼ and the clock CLK rises at time t ₁ , the output signal WS of the AND gate 26 becomes “H” level. However, since the reverse-phase clock ▲ ▼ is at the “L” level, the write pulse generating circuit 27 does not generate the “H” level write pulse WP. As a result, buffer 28 does not work and the write operation has not yet started.

Subsequently, when the clock CLK falls at the time (time t ₂ ) when a time sufficient for ending the above-described data output state has elapsed, the negative-phase clock ▲ ▼ exhibits the “H” level. As a result, the register 24 latches the write data D _IN from the input / output terminal T5, while the write pulse generation circuit 27 generates the “H” level write pulse WP. As a result, the buffer 28 functions and the write data D _IN latched in the register 24 is supplied to the memory cell array 20 via the buffer. This makes the data input valid (see FIG. 5).

At this time (at the time of t ₂ ), the state of data output has ended, so the input / output terminal T 5 can be dedicated as “for input”.

In this way, using both the rising edge and the falling edge of the external clock CLK, the timing of latching the write data D _IN (at the time of t ₂ ) and the write command signal ▲
By devising the circuit configuration so that the timing of latching ▼ (time point of t ₁ ) is different, it is possible to completely eliminate the inconvenience that the input / output of data collides even with the common terminal T5. That is, since the data input / output terminals can be made common, the circuit scale as a device can be reduced.

In the embodiment described above, the write command signal ▲ is generated at the rising edge of the external clock CLK in the write cycle t _W.
It is configured to latch ▼ and latch the write data D _IN at the falling edge of the clock CLK.
It can also be configured to latch at opposite edges.

〔The invention's effect〕

As described above, according to the semiconductor memory device of the present invention, the input / output terminals of data can be made common without causing the inconvenience that the input data and the output data collide with each other, and the circuit scale as a device can be reduced. Can be contributed to.

[Brief description of drawings]

FIG. 1 is a principle block diagram of a semiconductor memory device according to the present invention, FIG. 2 is a block diagram showing a configuration of an STRAM device as an embodiment of the present invention, and FIG. 3 is an example of a write pulse generation circuit in FIG. FIG. 4 is a circuit diagram showing a configuration example, FIG. 4 is a circuit diagram showing a concrete configuration example of the data input / output unit in FIG. 2, FIG. 5 is an operation timing diagram of the apparatus of FIG. 2, and FIG. FIG. 7 is a block diagram showing the structure of an STRAM device as an example, and FIG. 7 is an operation timing diagram of the device shown in FIG. (Explanation of symbols) 1 ... Cycle defining circuit, 2 ... Clock inverting means, 3
...... Write signal generation circuit, 4 ...... Memory cell array, 5
...... Input / output terminals, 6 …… Write data latch means, CLK
…… External clock, ▲ ▼ …… Reverse phase clock, D _IN
…… Write data, ▲ ▼ …… Write command signal, WS…
... write control signal, WP ... write signal, OE ... read control signal, t _A , t _B ... external clock level change point, t _R
…… Read cycle, t _W …… Write cycle.

Claims (1)

(57) [Claims] 1. A semiconductor memory device for receiving an external clock signal having a rising edge and a falling edge, comprising: a memory cell array; and a read cycle and a write cycle of the memory cell array operably connected to the memory cell array. A first latch which receives a control signal indicating one of them and latches the control signal in response to one of a rising edge and a falling edge of the external clock signal
And a second latch circuit that is operably connected to the memory cell array, receives write data, and latches the write data in response to the other rising edge or falling edge of the external clock signal. A write signal is supplied to the memory cell array when the control signal latched by the first latch circuit is operatively connected to the memory cell array and the first latch circuit and indicates the write cycle. A semiconductor memory device comprising: a write signal generating circuit, wherein a write data input terminal and a read data output terminal used for writing and reading data with the memory cell array are connected in common.