JP2001135083A - Multi-port memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a multi-port memory system in which identity of data is high and whose operation speed is high by using an access mediating circuit. SOLUTION: This memory is provided with a memory cell array 101 from/in which data is read out and written by plural ports, a bypass buffer 108 inserted bi-directionally into an I/O circuit 107 being corresponding to a port and independent, an address competition detecting circuit 109 comparing address signals from plural ports with each other, an address register 102 setting which access has priority when access request for the same address is performed, and an access mediating circuit 110 adjusting so that write-in operation and read-out operation are not caused at the same timing, control is performed so that only one side out of write-in or read-out for the same memory cell array 101 is performed, potential variation of a needless bit line is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device,
Especially multi-port static random access
It is about memory.

[0002]

2. Description of the Related Art Generally, a multi-port memory (in this example, a dual-port memory having two ports will be described) has a plurality of bit line pairs and word lines (two in this example) in each memory cell. Access from two ports connected to two pairs of bit lines and word lines at the same time to memory cells of the same address is called an access conflict.

[0003] To realize data stability in the event of such access contention is disclosed in, for example, Japanese Patent Laid-Open No. 62-17 / 1987.
No. 5992. In this example, if an access conflict occurs in which a write request from port A and a read request from port B occur simultaneously, read data is output from port B after the write operation from port A is completed. Control the output section on the B port side.

[0004]

In the conventional configuration as described above, when an access is requested from two ports to a memory cell at the same address, an output is triggered by a negation of a write signal to the port. This is used as a control signal for the latch of the section to prevent unstable data from being output to the outside in the process of writing into the memory cell.

[0005] Therefore, for a bit line to be read, after the bit line potential changes due to the data stored in the memory cell before being rewritten, the bit line based on the newly rewritten data is changed. A change in potential is performed.

Therefore, when the data in the memory cell is updated before and after the writing, an extra change in the potential of the bit line occurs, and extra reading time is required as compared with the case where access competition does not occur. .

Particularly, in a memory system using a sense amplifier circuit which amplifies a potential change of a bit line and outputs the amplified signal to the outside, in order to avoid a malfunction in which amplification occurs in a transient state, activation of the sense amplifier is performed. Since it is necessary to design the timing in accordance with the timing when the access conflict occurs, the output timing cannot be advanced even when the access conflict does not occur.

Therefore, when a write request and a read request for the same memory cell conflict, the data in the memory cell being rewritten by the write circuit once drives the read bit line. If the data read to the bit line is different from the data to be rewritten, it is necessary to read the data on the read bit line again.

Since it is necessary to correct the potential change of the bit line with a heavy load in the reverse direction, the reading is delayed as compared with the normal reading timing. In some cases, there is a possibility that data being written is output to the outside.

An object of the present invention is to provide a multi-port memory which can solve the above-mentioned drawbacks and can also support a read priority mode at the time of access contention.

[0011]

According to a first aspect of the present invention, there is provided an address conflict detecting circuit for detecting an access conflict and an input / output buffer connected to each input / output port. By providing an inserted controllable buffer and an access arbitration circuit for controlling writing / reading to / from a memory cell, when an access conflict occurs, a circuit for reading from the memory cell is deactivated and an input / output buffer is provided. By activating only a desired portion of the controllable buffer inserted therebetween, the write data is directly read.

According to a second aspect of the present invention, an access arbitration circuit for adjusting a write operation and a read operation so as not to occur at the same timing based on a result of an address conflict detection circuit, and an address for storing data and an address when a conflict occurs. By providing a buffer, when an access conflict occurs, only a read operation is performed on a memory cell, and address information and data at that time are stored in a write buffer. The data stored in the write buffer is written to the memory cells during a time period when any port is vacant. By restricting access to the memory cells to read only, data identity is guaranteed.

According to a third aspect of the present invention, a write buffer unit for temporarily storing write data / write address, a setting register for setting write priority / read priority in advance, and controlling writing / reading to / from a memory cell are provided. By providing the access arbitration circuit, it is possible to easily switch between the write priority and the read priority without generating a penalty for the access time.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention (claim 1) provides a plurality of ports to which address signals and control signals can be independently inputted, an independent I / O circuit corresponding to the ports, and a read / write operation from the plurality of ports. Memory and the plurality of I / Os
A read buffer inserted bidirectionally into the circuit, an address conflict detection circuit for comparing and comparing address signals from a plurality of ports, and a write operation and a read operation occur at the same timing based on the result of the address conflict detection circuit. A multi-port memory that has an access arbitration circuit that adjusts the data so that the data arbitration circuit controls the column selection circuit and the bypass buffer, thereby guaranteeing data consistency in the form of write priority. I do.

According to a second aspect of the present invention, when the access request to the same address is detected by the address contention detection circuit, the access arbitration circuit negates a control signal on a read request port which has a lower priority. Features and
Control is performed so that only the circuit on the write request port side operates and the bit line on the read request port side does not operate.

According to the present invention (claim 3), a plurality of ports to which an address signal and a control signal can be independently inputted, an independent I / O circuit corresponding to the port, and a memory read / written from the plurality of ports are provided. A read buffer bidirectionally inserted into the plurality of I / O circuits, an address conflict detection circuit for comparing and comparing address signals from a plurality of ports, and a write operation and a read operation based on the result of the address conflict detection circuit. It has an access arbitration circuit that adjusts the operation so that it does not occur at the same timing, and an address buffer that stores data and addresses when contention occurs. Is stored in the write buffer.

The present invention (claim 4) provides a plurality of ports to which address signals and control signals can be input independently, an independent I / O circuit corresponding to the ports, and a memory read / written from the plurality of ports. A read buffer bidirectionally inserted into the plurality of I / O circuits;
A read buffer inserted bi-directionally into the O circuit, an address conflict detection circuit for comparing address signals from a plurality of ports, and which access should be given priority when an access request to the same address occurs. A setting register to be set and an access arbitration circuit for adjusting so that a write operation and a read operation do not occur at the same timing are provided, and control when an address conflict occurs is selected by the setting register.

<First Embodiment> FIG. 1 is a schematic configuration diagram of a multiport memory according to a first embodiment of the present invention.
FIG. 2 shows a configuration of a memory cell of the multiport memory. For the sake of simplicity, the present embodiment will be described using a dual-port memory having two independent ports (A port and B port).

In FIGS. 1 and 2, reference numeral 101 denotes a memory cell array including memory cells 100 for storing data. The memory cells 100 correspond to two ports independent of an inverter of a flip-flop configuration for storing data. A pair of bit lines BL (A) and XB for outputting data, comprising input / output gates composed of N-channel transistors
L (A), BL (B) and XBL (B), and word lines WL1 and WL2 which control input / output of data to / from the memory cells.

Reference numerals 102 (A) and 102 (B) are address registers for storing addresses, and 103 (A) and 103 (B) are row decoders for decoding row address information. The output terminals of the row decoders 103 (A) and 103 (B) have word line control circuits 104 (A), 1
04 (B) is connected.

Each bit line pair has a column selection circuit 10 for selecting a bit line corresponding to the corresponding column address information.
6 (A) and 106 (B), the output of which amplifies the data read on the bit line during reading and outputs the amplified data to the outside, and writes the data into the selected memory cell during writing. I / O circuits 107 (A) and 107 (B) for writing are connected.

108 (A) and 108 (B) are I / O circuits 107
This is a bypass buffer connecting between (A) and 107 (B). 1
An address conflict detection circuit 09 detects that the address input to the A port matches the address input to the B port.

Reference numeral 110 denotes an address conflict detection circuit 10.
9 and the read request signals RRE (A), RRE (B) and write request signals WRE (A), WRE (B) for each port as inputs, and the word line control circuits 104 (A), 104 ( B),
I / O circuits 107 (A) and 107 (B), bypass buffers 108 (A) and 108 (B), and precharge circuits 105 (A) and 105 for setting bit lines to a predetermined potential.
An access arbitration circuit for controlling (B).

The operation of the multi-port memory configured as described above will be described below with reference to FIGS. 1, 2 and 3. Here, FIG. 3 shows a schematic operation timing of the multiport memory. In the present embodiment, an example will be described in which a cycle in which access contention occurs during a three-cycle period and a cycle in which access contention does not occur are included.

In the multiport memory of this embodiment, address signals, read request signals, and write request signals of different systems are input to two independent ports A and B, respectively.

In the multi-port memory of this embodiment, in an initial state where no access request is received, each bit line is precharged by the precharge circuits 105 (A) and 105 (B).

The case where a write request is issued to port A at time T0, a read request is issued to port B, and an access conflict occurs, will be described on the assumption that the access start address indicates address An.

At time T0, a read request signal RRE (B) and a write request signal WRE (A) for the memory area are issued, and at the same time, the address An is input to the A port and the B port, respectively.

The address conflict detection circuit 109 compares the addresses, detects that an access conflict has occurred, and inputs the detection result to the access arbitration circuit 110. At this time, it is detected that the access request is a write request to the A port and a read request to the B port, and is not a write request to the same address.

At time T1, the write enable signal WEE (A) is
It is output to the word line control circuit and I / O circuit on the A port side. As a result, write data is output by the I / O circuit 107 (A) to the bit lines BL (A) and XBL (A) selected by the column selection circuit 106 (A), and at the same time, the word corresponding to the A port is output. The line WL (A) is activated, and data is written to the memory cell.

At the same time, the read enable signal REE (B)
The signal is output to the I / O circuit on the port side, and the B-side bypass enable signal RBE (B) is output to the bypass buffer 108 (B).

As a result, the write data on the I / O circuit 107 (A) is directly output to the I / O circuit 107 (B) by the bypass buffer 108 (B) and read out to the external bus. At this time, the read enable signal is not issued to the column selection circuit (B), and the I / O is not performed by the column selection circuit.
The O circuit 107 (B) and the memory cell array are separated from each other, and no collision occurs with data from the memory cell side.

At this point, the writing from the bit line on the A port side is performed in parallel. Even if the data in the memory cell is changed before and after the writing, the data is transferred via the bit line on the B port side. No data transfer occurs.

In other words, there is no potential change on the read bit line in the opposite phase to the data in the memory cell, which may cause erroneous reading. Therefore, no extra timing margin is required for the reading operation.

In particular, in a memory system using a sense amplifier circuit for amplifying a potential change of a bit line in an I / O circuit portion, the potential change in the opposite phase may cause irreversible data output to an external output. This embodiment requires a large timing margin, so that the effect of increasing the speed according to the present embodiment is great.

When the address conflict is detected by the address conflict detection circuit 109 and a write request to the same address is detected, data is written from one of the ports so as to protect data coherency by a system protocol. Is performed with priority.

When only a read request is issued at time T2, a read enable signal REE (B) is output to the column selection circuit (B), the I / O circuit (B), and the word line control circuit (B). , The word line WL (B) of the B side port is asserted,
Data is read from the memory cell to the bit line (B),
It is output to the outside via the column selection circuit (B) and the I / O circuit (B).

Similarly, when only writing is requested at time T4, only the write enable signal is sent from the access arbitration circuit to the column selection circuit (B), I / O circuit (B), and word line control circuit (B). Is output and written to the memory.

As described above, when an access conflict occurs in the multi-port memory of the present embodiment, the circuit on the A side operates according to the write request to the memory cell by the access arbitration circuit, and the write is performed. Bypass enable
Data is directly output from the I / O circuit 107 (A) to the I / O circuit 107 (B) by RBE (B).

In this embodiment, the access arbitration circuit negates the word line control circuit on the side of the read request port where the priority is not given. Therefore, even when access competition occurs, no extra potential change occurs on the read-side bit line. It is possible to reduce unnecessary current consumption and to avoid erroneous reading due to a transient change in bit line potential.

As a result, an extra timing margin for avoiding erroneous reading can be eliminated, so that a high-speed multiport memory can be realized.

<Second Embodiment> Next, a multiport memory according to a second embodiment of the present invention will be described with reference to the drawings.

In this embodiment, a multi-port memory for realizing data consistency with read priority is configured. FIG. 4 is a schematic configuration diagram of the multiport memory according to the present embodiment.

The basic configuration of the entire memory is the same as that of the multi-port memory shown in FIG.
A write buffer for storing data is added. FIG. 5 is a timing chart showing the operation. In the drawings, the same reference numerals denote the same parts.

In FIG. 4, reference numeral 400 denotes a write buffer for storing addresses and data at the time of access contention. The write buffer 400 includes a register that receives and stores the address and data of the A port side and the B port side, and stores the stored address information in the row decoder (A) and the row decoder (B) selectively. It selectively outputs to the I / O circuit (A), column selection circuit (A) or I / O circuit (B), column selection circuit (B).

The operation of the multi-port memory configured as described above will be described below with reference to FIGS.

The case where a write request to port A, a read request to port B, and an access conflict at time T0 will be described assuming that the access start address indicates address An.

At time T0, a read request signal RRE (B) and a write request signal WRE (A) for the memory area are issued, and at the same time, the address An is input to the A port and the B port, respectively. The address conflict detection circuit 109 compares the addresses, detects that an access conflict has occurred, and inputs the detection result to the access arbitration circuit 110.

At this time, the access request is a write request for port A and a read request for port B.
It is detected that the request is not a write request to the same address.

At time T0, a write request signal WRE (A) is input to the access arbitration circuit. At this time, the address conflict detection circuit detects that an access conflict has occurred,
Arbitration request information is output to the access arbitration circuit. With this input, the access arbitration circuit negates the write-side control signal. That is, the word line control circuit (A) and the column selection circuit (A) are deactivated.

At this time, a read enable signal REE (B) is issued to the column select circuit (B), I / O circuit (B), and word line control circuit (B) on the B side in accordance with the priority read request. Thereby, WL (B) is activated, data is read from the memory cell to the bit line BL (B), and data is output to the outside via the column selection circuit (B) and the I / O circuit (B). .

At the same time, a write signal is issued from the access arbitration circuit to the write buffer 400, and the address information where the conflict has occurred and the write data are stored. In this embodiment, addresses are input from each of the A port and the B port. However, at the time of access conflict, since the addresses from both ports are completely the same, it is possible to input only one address.

It is also possible to employ a configuration in which data after use for address comparison is latched. At time T2, the next cycle is entered, and the state transits to a state in which there is only a read request from the B port side. The address conflict detection circuit compares the address information in the write buffer with the current input address information.

If they do not match, the circuit on the B port side operates in the same manner as before, and the data corresponding to the address An + 1 is read from the memory cell array and output to the outside via the I / O circuit (B). Is done. At this time, if it is a normal memory
The circuit on the A port side is empty.

In the multiport memory according to the present embodiment,
Using this empty state, data is written from the write buffer to the memory cell array using the circuit on the A side. That is, the address in the write buffer is output to the row decoder (A) and the column selection circuit (A), and the stored data is written to the memory cell array.

If the address in the write buffer matches the current address, the data in the write buffer is valid, and the data is output to the outside via the B-side I / O circuit.

Time T4 at which the next write cycle starts
The operation after is a normal write operation, and the write operation is executed by the A circuit.

In this embodiment, an example has been described in which writing is performed from the write buffer to the memory cell in a state where the circuit of one of the ports is vacant.
For this control method, there are several control methods such as a method of making a determination at the time of the next write request, a method of simultaneously updating the write buffer and writing to the memory cell array at the time of the next access conflict. Can be

As described above, according to the present embodiment, when an access conflict occurs, it is detected by the address conflict detection circuit, and only the read operation is performed on the memory cell by the access arbitration circuit. Data and address are stored in the write buffer.

As a result, data consistency is guaranteed in the read priority state. Even when an access conflict occurs, no extra potential change occurs on the bit line. It is possible to reduce unnecessary current consumption and to avoid erroneous reading due to a transient change in bit line potential. Since an extra timing margin for avoiding erroneous reading can be eliminated, a high-speed multiport memory can be realized.

Third Embodiment Next, a multiport memory according to a third embodiment of the present invention will be described with reference to the drawings. In the present embodiment, a multi-port memory that realizes data consistency by arbitrarily setting read priority / write priority is configured. FIG. 6 is a schematic configuration diagram of the multiport memory according to the present embodiment.

The basic structure of the entire memory is shown in FIGS.
And a setting register for storing information on the priority order for determining read priority / write priority at the time of contention. In the drawings, the same reference numerals denote the same parts.

The basic operation of each part of this embodiment is common to the multiport memory described in the first and second embodiments. The setting register 601 is a register for storing information on whether to give priority to read or write when access conflict occurs, and outputs the priority information to the access arbitration circuit.

When the write priority flag is stored in the setting register 601, the multiport memory of this embodiment operates in exactly the same manner as in the first embodiment, and achieves data identity, high-speed access, and low power consumption. To achieve.

On the other hand, when the read priority flag is stored in the setting register 601, the multiport memory of the present embodiment operates in exactly the same manner as in the second embodiment, and has the same data, high access speed, and low access speed. Realize power consumption.

Since the read priority / write priority can be easily switched with the same configuration, a memory capable of appropriately switching the read priority / write priority mode depending on the application only by mounting one multiport memory. It is possible to build a system.

When a plurality of the present multi-port memories are mounted in the same system, the read priority portion and the write priority portion can be easily realized by changing the setting of the setting register for each area. A highly flexible memory system can be constructed.

[0068]

As described above, according to the present invention, even when an access conflict occurs as compared with the conventional memory system, an unnecessary potential change does not occur on the bit line and an unnecessary current consumption can be reduced. It is possible to avoid erroneous reading due to a transient bit line potential change.

As a result, data identity, high-speed access, and low power consumption are realized. Embodiment 3
With the same configuration, read priority / write priority can be easily switched with the same configuration. Therefore, a memory system capable of appropriately switching the read priority / write priority mode depending on the application only by mounting one multiport memory. It is possible to construct

When a plurality of the present multiport memories are mounted in the same system, the read priority portion and the write priority portion can be easily realized by changing the setting of the setting register for each area. A highly flexible memory system can be constructed.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a multiport memory according to a first embodiment of the present invention;

FIG. 2 is a configuration diagram of a memory cell of the multiport memory according to the first embodiment of the present invention;

FIG. 3 is a timing chart showing an operation in the embodiment.

FIG. 4 is a schematic configuration diagram of a multi-port memory according to a second embodiment of the present invention;

FIG. 5 is a timing chart showing an operation in the embodiment.

FIG. 6 is a schematic configuration diagram of a multi-port memory according to a third embodiment of the present invention.

FIG. 7 is a schematic configuration diagram of a conventional multiport memory.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 memory cell 101 memory cell array 102 address register 103 row decoder 104 word line control circuit 105 precharge circuit 106 column selection circuit 107 I / O circuit 109 address conflict detection circuit 110 access arbitration

Claims (4)

[Claims] A plurality of ports to which address signals and control signals can be independently inputted, and independent I / Os corresponding to the ports.
An O-circuit, a memory for reading / writing from / from the plurality of ports, a read buffer bidirectionally inserted into the plurality of I / O circuits, and an address conflict detection circuit for comparing and comparing address signals from the plurality of ports. And an access arbitration circuit for adjusting a write operation and a read operation so as not to occur at the same timing based on a result of the address conflict detection circuit. 2. An access arbitration circuit for negating a control signal on a read request port which has a lower priority when an access request to the same address is detected by the address conflict detection circuit. Multi-port memory. 3. A plurality of ports to which address signals and control signals can be independently inputted, and independent I / Os corresponding to the ports.
An O-circuit, a memory for reading / writing from / from the plurality of ports, a read buffer bidirectionally inserted into the plurality of I / O circuits, and an address conflict detection circuit for comparing and comparing address signals from the plurality of ports. An access arbitration circuit that adjusts a write operation and a read operation so as not to occur at the same timing based on a result of the address conflict detection circuit, and an address buffer that stores data and an address when a conflict occurs. Features multiport memory. 4. A plurality of ports to which address signals and control signals can be input independently, and independent I / Os corresponding to the ports.
An O circuit, a memory that reads and writes from the plurality of ports, a read buffer bidirectionally inserted into the plurality of I / O circuits, and a read buffer bidirectionally inserted into the plurality of I / O circuits. An address conflict detection circuit that compares address signals from a plurality of ports, and a setting register that sets which access is prioritized when an access request to the same address is generated. A multi-port memory comprising an access arbitration circuit for adjusting so that operations do not occur at the same timing.