JPH05258557A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To shorten cycle time by latching an inputted data at the time of inputting of an address signal, thereby eliminating confliction of data of read modified write mode. CONSTITUTION:When the inverse of RAS becomes active, line addresses on address signal A-A are latched, and when the inverse of CAS become active, row addresses on address lines A-A are latched. While, writing data on an I/O terminal is latched, and it is stored in a register. Continuously, when the inverse of WE becomes active, writing data in the register is written in a designated memory cell by the line addresses and the row addresses.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device. In particular, the present invention relates to a semiconductor memory device having read / modify / write functions in which output data at the time of reading and input data at the time of writing are input / output through the same terminal.

[0002]

2. Description of the Related Art The structure of a conventional address type multiplex type dynamic semiconductor memory device is shown in FIG.
The operation at the time of reading will be described. n address signal lines A
_{0 to} A _n are connected to the row address buffer 401 and the column address buffer 403. / RAS is connected to the first clock generation circuit 405. The row address on the address signal lines A _{0 to} A _n is latched by the output signal of the first clock generation circuit 405, and the row address signal is input to the row decoder 409. The row decoder 409 decodes a row address and selects one memory cell row in the memory cell array 411. The data of the selected memory cell row is output to the sense amplifier 413 as a minute voltage amplitude signal. / CAS is connected to the second clock generation circuit 407. The column address on the address signal lines A _{0 to} A _n is latched by the output signal of the second clock generation circuit,
The column address signal is input to the column decoder 415. The column decoder 415 decodes the column address and selects the memory cell column. The sense amplifier 413 outputs the data of the selected memory cell column to the output buffer 417, and the output buffer I / O is output only when the output enable signal / OE is active.
Output data to the terminal.

The signal waveform of the operation at the time of reading is shown in FIG. / RAS is the address signal lines A ₀ to A _n row above address when activated latched, / CAS a column address on the signal line A ₀ to A _n when activated is latched. Then, after a while after / OE becomes active, data is output to the I / O terminal.

Next, the operation at the time of writing will be described. / RA
When S becomes active, the first clock generation circuit 405
Outputs a first clock signal. This output signal latches the row address on the address signal lines A _{0 to} A _n , and the row address signal is input to the row decoder 409.
The row decoder 409 decodes a row address and selects one memory cell row in the memory cell array 411. /
When CAS becomes active, the second clock generation circuit 4
07 outputs the second clock signal. This output signal latches the column address on the address signal lines A _{0 to} A _n , and the column address signal is input to the column decoder 415. The column decoder 415 decodes the column address and selects the memory cell column. Then, when / WE becomes active, the write data on the I / O terminal is transferred to the input buffer 419.
Latches and inputs to the sense amplifier 413. The sense amplifier 417 operates as a drive source for the data writing operation to the memory cell, and writes the data to the memory cell designated by the row address and the column address.

FIG. 8 shows the signal waveform of the operation during writing. / RAS is the address signal lines A ₀ to A _n row above address when activated latched, / CAS a column address on the signal line A ₀ to A _n when activated is latched. Then, when / WE becomes active, the write data on the I / O terminal is latched, and the data is written in the memory cell designated by the row address and the column address.

The read operation and write operation of the dynamic semiconductor memory device have been described above, but there is another operation mode called read modified write. The read modified write is an operation of writing the content of the memory cell immediately after reading the content of the memory cell by inputting the address once. The data to write depends on the content of the read data. In this case, the object can be achieved by continuously performing the read operation and the write operation, but the same address must be input twice. The read-modify-write operation requires only one address input, so high-speed operation is expected.

The operation of the read modified write will be described below. When / RAS becomes active, the first clock generation circuit 405 outputs the first clock signal.
This output signal latches the row address on the address signal lines A _{0 to} A _n , and the row address signal is transferred to the row decoder 40.
9 is input. The row decoder 409 decodes a row address and selects one memory cell row in the memory cell array 411. The data of the selected memory cell row is output to the sense amplifier 413 as a minute voltage amplitude signal. When / CAS becomes active, the second clock generation circuit 407 outputs the second clock signal. This output signal latches the column address on the address signal lines A _{0 to} A _n , and the column address signal is input to the column decoder 415. The column decoder 415 decodes the column address,
Select a memory cell column. The sense amplifier 413 outputs the data of the selected memory cell column to the output buffer 417, and the output buffer outputs the data to the I / O terminal only when the output permission signal / OE is active. Then, / WE
Becomes active, the input buffer 419 latches the write data on the I / O terminal and inputs it to the sense amplifier 413. The sense amplifier 417 operates as a drive source for the data writing operation to the memory cell, and writes the data to the memory cell designated by the row address and the column address.

The signal waveform of the read modified write operation is shown in FIG. / RAS is the address signal lines A ₀ to A _n row above address when activated latched, / CAS signal lines A ₀ to A when activated
The column address on _n is latched. Then, after a while after / OE becomes active, data is output to the I / O terminal. I / O when / OE becomes inactive
The terminal is in a high impedance state when viewed from the outside. Then, when / WE becomes active, the write data on the I / O terminal is latched, and the data is written in the memory cell designated by the row address and the column address.

The conventional dynamic semiconductor memory device having the read modified write mode has been described above. However, since the I / O terminal is generally connected to the external data bus, a slight time interval is allowed before inputting write data to the I / O terminal after the read operation is completed in order to avoid data collision. .. Therefore, there is a drawback that the cycle time of the read modified write becomes long.

[0010]

As described above, the conventional semiconductor memory device has a drawback that the cycle time in the read modified write mode becomes long. It is an object of the present invention to eliminate the above-mentioned drawbacks and provide a semiconductor memory device having a short cycle time in the read modified write mode.

[0011]

In order to achieve the above object, output data at the time of reading and input data at the time of writing are input / output through the same terminal, and an address signal is generated in response to a first signal. In a semiconductor memory device having a plurality of memory cells in which the contents of the register are latched and held in response to the first signal, and the contents of the register in the address in response to a second signal. A semiconductor memory device is provided, which comprises: a transmission means for writing data in the memory cell designated by a signal.

Output data at the time of reading and input data at the time of writing are input and output through the same terminal, the row address signal is latched in response to the first signal, and the row address signal is responded to in response to the second signal. In a semiconductor memory device having a plurality of memory cells of an address multiplex system in which a column address signal is latched, a register that latches and holds the input data in response to the second signal, and a register that responds to a third signal And a transmission means for writing the contents of the register into the memory cell designated by the address signal.

[0013]

When the means provided by the present invention is used, the input data can be stored in the register at the same time when the address signal is input, and the input data in the register can be written in the memory cell according to the content of the output data. I can. That is, since the input data is latched when the address signal is input, there is no data collision in the read modified write mode and a short read modified cycle is realized.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment will be described below with reference to FIG.

First, the operation at the time of reading will be described. The n address signal lines A0 to An are connected to the row address buffer 10.
1 and the column address buffer 103. / R
AS is connected to the first clock generation circuit 105.
The row address on the address signal lines A _{0 to} A _n is latched by the output signal of the first clock generation circuit 105, and the row address signal is input to the row decoder 109. The row decoder 109 decodes the row address, and the memory cell array 1
One memory cell row in 11 is selected. The data of the selected memory cell row is output to the sense amplifier 113 as a minute voltage amplitude signal. / CAS is connected to the second clock generation circuit 107. The column address on the address signal lines A _{0 to} A _n is latched by the output signal of the second clock generation circuit, and the column address signal is transmitted to the column decoder 115.
Entered in. The column decoder 115 decodes the column address and selects the memory cell column. The sense amplifier 113 outputs the data of the selected memory cell column to the output buffer 117.
The output buffer outputs data to the I / O terminal only when the output enable signal / OE is active.

Next, the operation at the time of writing will be described. / RA
When S becomes active, the first clock generation circuit 105
Outputs a first clock signal. This output signal latches the row address on the address signal lines A _{0 to} A _n , and the row address signal is input to the row decoder 109.
The row decoder 109 decodes the row address and selects one memory cell row in the memory cell array 111. /
When CAS becomes active, the second clock generation circuit 1
07 outputs the second clock signal. The output signal latches the column address on the address signal lines A _{0 to} A _n , and the column address signal is input to the column decoder 115. The column decoder 115 decodes the column address and selects the memory cell column. Then, when / WE becomes active, the write data on the I / O terminal is transferred to the input buffer 119.
Are latched and output to the register 121. The input gate 123 writes the write data to the memory cell designated by the row address and the column address of the memory cell array 111 according to the / WE signal. The signal waveforms at the time of reading and writing are the same as those of the conventional example.

Next, the operation of the read modified write mode will be described. When / RAS becomes active, the first clock generation circuit 105 outputs the first clock signal. This output signal latches the row address on the address signal lines A _{0 to} A _n , and the row address signal is input to the row decoder 109. The row decoder 109 decodes the row address and selects one memory cell row in the memory cell array 111. When / CAS becomes active,
The second clock generation circuit 107 outputs the second clock signal. This output signal causes the address signal lines A _{0 to} A _n.
The upper column address is latched and the column address signal is input to the column decoder 115. The column decoder 115 decodes the column address and selects the memory cell column. At the same time, in response to / CAS, write data is latched by the input buffer and taken into the register 121. The data of the selected memory cell row is output to the sense amplifier 113 as a minute voltage amplitude signal, and is output to the I / O terminal only when / OE is active by the output buffer 117. Then, in response to / WE, the input gate 123 transfers the write data, which is the contents of the register 121, to the memory cell 111.
To the memory cell designated by the row address and the column address.

The signal waveform of the read modified write mode is shown in FIG. / RAS is the address signal lines A ₀ to A _n row above address when activated latched, / CAS signal lines A ₀ ~ when activated
The column address on A _n is latched and at the same time I / O
The write data on the terminal is latched and stored in the register. Then, after a while after / OE becomes active, data is output to the I / O terminal. Then, / W
When E becomes active, the write data in the register is written in the memory cell designated by the row address and the column address.

Although the first embodiment has been described above, when this method is used, the write data is written during the time when the address signal is input to the semiconductor memory device, in many cases when the external bus is idle. Pre-filled. Further, since the write data is input before the read data is output, there is no data collision. Therefore, the cycle can be completed in a short time as compared with the read modified write cycle of the conventional semiconductor memory device.

There is a limit to write data in the read modified write mode operation in the semiconductor memory device of the first embodiment. In the semiconductor memory device of the conventional example, the write data can be determined according to the read data, but the semiconductor memory device of the first embodiment inputs the write data before reading the data, and therefore the write data is written later. You cannot change the data. The control that can be performed by an external signal after inputting the write data is only whether or not the write data is written in the memory cell. However, in applications using the read modified write mode, such as a Z buffer used for image processing, this is sufficient in many cases. That is, the data to be written is determined in advance, and it is determined whether or not the writing should be performed according to the read data. If it is determined that the write data need not be written, / WE need not be activated.

Although the input gate 123 is provided separately from the column decoder and the sense amplifier in the first embodiment, the output of the register and the column decoder 115 are connected via the transmission gate 125, and the transmission gate 125 is connected to / WE. It may be controlled to be open when active. This is shown in [Fig. 3]. In this way, the input gate 123 can be omitted.

Next, a second embodiment which is not the address multiplex system will be described with reference to FIG. The operation at the time of reading and writing is exactly the same except that / RAS and / CAS are replaced with only one signal / CE.

The operation of the read modified write mode will be described. When / CE becomes active, the first clock generation circuit 205 outputs the first clock signal. The address on the address signal lines A _{0 to} A _n is latched by this output signal, and the row address signal is input to the row decoder 209. The row decoder 209 decodes a row address and selects one memory cell row in the memory cell array 211. In addition, the column address signal is input to the column decoder 215. The column decoder 215 decodes the column address and selects the memory cell column. At the same time, /
In response to CE, the write data is latched by the input buffer 219 and taken into the register 221. The data of the selected memory cell row is output to the sense amplifier 213 as a minute voltage amplitude signal, and the output buffer 217 outputs / O.
It is output to the I / O terminal only when E is active. Then, in response to / WE, the input gate 223 causes the register 221 to
The write data, which is the content of, is transmitted to the memory cell 211 and written in the memory cell designated by the row address and the column address.

The signal waveform of the read modified write mode is shown in FIG. When / CE becomes active, the addresses on the signal lines A _{0 to} A _n are latched, and at the same time, the write data on the I / O terminal is latched and stored in the register. Then, after a while after / OE becomes active, data is output to the I / O terminal.
Then, when / WE becomes active, the write data in the register is written in the memory cell designated by the address.

The second embodiment which is not the address multiplex system has been described above. However, in this way, it can be used not only for a general-purpose semiconductor memory device but also for an on-chip cache on a microprocessor. In this example as well, as in the first embodiment, the cycle can be completed in a short time as compared with the read modified write cycle of the conventional semiconductor memory device.

Although the dynamic semiconductor memory device has been described above in both the first and second embodiments, the present invention is not limited to this, and it is possible to read and write a semiconductor memory device such as a static type semiconductor memory device. I wish I had it.

[0027]

By using the means provided by the present invention, it is possible to provide a semiconductor memory device having a shorter cycle time compared to the read-modified write cycle of the conventional semiconductor memory device.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a signal waveform during a read modified write operation according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram showing a first embodiment of the present invention.

FIG. 4 is a configuration diagram showing a second embodiment of the present invention.

FIG. 5 is a signal waveform during a read modified write operation according to the second embodiment of the present invention.

FIG. 6 is a configuration diagram showing a conventional example.

FIG. 7 is a signal waveform during a read operation of a conventional example.

FIG. 8 is a signal waveform during a write operation of a conventional example.

FIG. 9 is a signal waveform during a read modified write operation of a conventional example.

[Explanation of symbols]

 101, 201, 401 row address buffers 103, 203, 403 column address buffers 105, 205, 405 first clock generation circuit 107, 407 second clock generation circuit 109, 209, 409 row decoders 111, 211, 411 memory cell array 113, 213, 413 Sense amplifier 115, 215, 415 Column decoder 117, 217, 417 Output buffer 119, 219, 419 Input buffer 121, 221 Register 123, 223 Input gate 125, 225 Transmission gate

Claims (2)

[Claims] 1. A semiconductor memory having a plurality of memory cells in which output data at the time of reading and input data at the time of writing are input and output through the same terminal, and an address signal is latched in response to a first signal. In the device, a register for latching and holding the input data in response to the first signal, and a write for writing the contents of the register in the memory cell specified by the address signal in response to a second signal. A semiconductor memory device comprising: 2. Output data at the time of reading and input data at the time of writing are input and output through the same terminal, a row address signal is latched in response to a first signal, and a row address signal is responded to in response to a second signal. In a semiconductor memory device having a plurality of address multiplex type memory cells in which column address signals are latched, a register for latching and holding the input data in response to the second signal, and a register for responding to a third signal And a writing means for writing the contents of the register into the memory cell designated by the address signal.