JPH02276090A - Semiconductor memory integrated circuit - Google Patents

Abstract

PURPOSE:To decrease the number of signals between a testing equipment by providing a pattern generator circuit which generates an address signal and data according to a clock signal in a test mode, and testing a dynamic burn-in operation, etc. CONSTITUTION:When the input terminal of a chip selective signal the inverse of CS is at a higher voltage than a normal level, a pattern generator circuit 1 is activated. According to a clock signal CK inputted from the input terminal of an address signal AN-1, the pattern generator circuit 1 transmits a control signal CS to a control circuit 7, an internal address signal IAD to an address buffer circuit 2, and internal data DT11 to an input/output circuit 6, respectively. The address buffer circuit 2 holds the internal address signal IAD, the signal is written/read to/from a memory cell array 5 in the same way as a normal operation, and the operation test proceeds. Thus the signals from the outside are reduced, the testing equipment is simplified and made generally applicable, and the testing equipment can be made inexpensive.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor memory integrated circuits.

[Conventional technology]

Conventional semiconductor memory integrated circuits - For example, as shown in FIG. 2, an external address signal A is used.

An address buffer circuit 2A that inputs and temporarily holds ~A N -1, and a row decoder 3 that selects a row line and a column line of the memory cell array 5 according to the address signal held in the address buffer circuit 2A. column decoder 4
and a memory cell array 5 that writes and reads data to and from memory cells connected to row lines and column lines selected by row decoder 3 and column decoder 4, and inputs data D T + for writing. An input/output circuit 6 receives input from terminal T1 to control transmission to the memory cell array 5, and controls transmission of data read from the memory cell array 5 to output terminal To, and inputs chip select signal C8 to activate and write enable. The control circuit 78 controls the input/output circuit according to the signal WF.

In addition, when performing an operation test such as a dynamic burn-in test of this semiconductor memory integrated circuit, a test device for memory integrated circuits is used, and address signals AO to AN-1 and write signals for testing are sent from this test device. data D
After inputting T1 and writing data into the memory cell array 5, address signals Ao to AN-1 were inputted to read and test the written data.

[Problem to be solved by the invention]

When performing an operation test on the conventional semiconductor memory integrated circuit described above, a test device dedicated to memory integrated circuits is used to test the address signal A. ~ Since the configuration is such that the test is performed by inputting AN-1 and the write data D T+ for testing, a test equipment dedicated to memory integrated circuits is required, and a large number of signals are generated by the test equipment. Moreover, since the wiring of these signal lines becomes complicated, there is a drawback that the test equipment becomes expensive.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory integrated circuit that can reduce the number of external signals, simplify and generalize a test device, and reduce the cost of the test device.

[Means to solve the problem]

The semiconductor memory integrated circuit of the present invention is activated by inputting a dead mode signal, generates a control signal by inputting a clock signal, and sequentially generates an internal address signal and internal data for testing corresponding to this internal address signal. a generated pattern generator circuit, and when the internal address signal is input, this internal address signal is held with priority;
When an address signal is manually input from the outside, an address buffer circuit that holds this address signal and a plurality of memory cells are provided, and data is written to the memory cell at the address of the address signal held in the address buffer circuit. , a memory cell array that performs reading, an input/output circuit that controls transmission of the internal data and external write data to the memory cell array, and controls transmission of data read from the memory cell array to an output terminal; and a control circuit that controls the input/output circuit using a control signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

pattern generator circuit] is a chip select signal C
By making the input terminal of 8 a higher voltage than the level of the normal chip select signal C8, the dead mode signal TM is input and activated, and the control signal C8 is activated according to the clock signal CK input from the input terminal of the address signal AN-1. At the same time, it generates an internal address signal IAD and internal test data D T corresponding to this internal address signal IAD.
＋ ＋ is generated sequentially.

When the internal address signal IAD is input to the address buffer circuit 2, the internal address signal IAD is input to the address buffer circuit 2.
is held with priority, and there is no internal address signal IAI), and address signals Ar) to AN- are received from the outside.

When input, this address signal A, ~AN-1
is held and output.

The memory cell array 5 includes a plurality of memory cells, and writes data to memory cells connected to row lines and column lines selected by the row decoder 3 and column decoder 4 according to address signals held in the address buffer circuit 2. , performs reading.

The input/output circuit 6 controls the transmission of internal data D T + + from the pattern generator circuit and external write data inputted from the input terminal TI to the memory cell array 5, and controls data read from the memory cell array 5. Controls transmission of data (1) 'l'θ) to output terminal TO.

The control circuit 7 controls the input/output circuit 6 according to the control signal C3 from the pattern generator circuit.

Next, the operation of this embodiment will be explained.

First, in the normal operation mode, which is not the test mode, since the chip select signal C8 is at the normal level, the pattern generator circuit becomes activated, and the semiconductor memory integrated circuit operates as before. will be carried out.

When the input terminal of the chip select signal C8 becomes a higher voltage than the normal level, the pattern generator circuit 1 is activated, and this pattern generator circuit 1 receives the address signal AN.
-, the control signal C8 is sent to the control circuit 7 according to the clock signal CK input from the input terminal of the internal address No. 18 I.
AD to address buffer circuit 2, internal data DT
+ + is transmitted to the input/output circuit 6.

The address buffer circuit 2 holds the internal address signal IAD, and from now on, the memory cell array 5
Writing and reading are performed to proceed with the operation test.

In this way, the only signals necessary for operation testing are the dead mode signal TM and the clock signal CK, and the output signal is only the read data D To, so the test equipment can be simplified. Moreover, it can also be used for integrated circuits other than memory integrated circuits. Furthermore, the terminal for input/output signals with the test equipment can be shared with the terminal for input/output signals during normal operation, so there is no need to provide a special terminal for testing.

〔Effect of the invention〕

As explained above, the present invention provides a pattern generator circuit that generates an address signal and data according to a clock signal in a test mode, and is configured to perform an operational test such as a genetic burn-in test. Since the number of signals can be reduced, the test equipment can be simplified and made more versatile, which has the effect of making the test equipment cheaper.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional semiconductor memory integrated circuit. DESCRIPTION OF SYMBOLS 1... Pattern generator circuit, 2, 2A... Address buffer circuit, 3... Row decoder, 4... Column decoder, 5... Memory cell array, 6... Input/output circuit, 7, 7A...・Control circuit. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] a pattern generator circuit that is activated by inputting a test mode signal, inputs a clock signal to generate a control signal, and sequentially generates an internal address signal and internal data for testing corresponding to the internal address signal; The address buffer circuit includes an address buffer circuit that prioritizes and holds this internal address signal when a signal is input, and holds this address signal when an address signal is input from the outside, and a plurality of memory cells. a memory cell array that writes and reads data to and from the memory cell at the address of a held address signal; and a memory cell array that controls transmission of the internal data and external write data to the memory cell array; What is claimed is: 1. A semiconductor memory integrated circuit comprising: an input/output circuit that controls transmission of data read from a semiconductor device to an output terminal; and a control circuit that controls the input/output circuit using the control signal.