JPH07272498A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To efficiently test a function by reducing a count of external signal terminals of a memory tester necessary for inputting of addresses, and increasing a count of external signal terminals for inputting/outputting of data. CONSTITUTION:In the semiconductor memory which latches all addresses together by an address strobe signal without having an RAS and a CAS, address control circuits 3, 6 are provided which divide address inputs to a plurality of address input groups A1-A4, A5-A8 and control to latch in different manners between at a normal time and at a testing time. When tone semiconductor memory is in a normal operating mode, the address latch control circuits 3, 6 latch the input address groups A1-A4, A5-A8 altogether. On the other hand, in a test mode, tone address latch control circuits 3, 6 sequentially latch the address input groups A1-A4, A5-A8 in a time-sharing manner. A count of signal terminals necessary for inputting of addresses is reduced in a memory tester 1 having a limited number of signal terminals, so that, the count of signal terminals necessary for inputting/outputting of data is increased. Accordingly, the inputting number of times of data and the evaluating number of times of signals necessary for a test are reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device (memory), and more particularly to improvement of a semiconductor memory of the type in which address signals are collectively latched by one address strobe signal during normal operation.

[0002]

2. Description of the Related Art As one type of conventional semiconductor memory, a memory for writing / reading data by one address strobe signal without a row address strobe (RAS) and a column address strobe (CAS), for example, a field. A memory (image memory) is known. In the case of such a semiconductor memory, for example, the address coordinates are designated by assigning the row address of the memory cell as a numerical value of the lower digit and the column address of the memory cell as the upper digit.

For example, access (addressing) in the image memory starts from the memory cell in the first row in the memory cell group in the first column of the memory cell array, and is hereinafter referred to as the memory cells in the second and third rows. When the addressing for one column is performed according to the row order and the addressing for all the rows in the first column is completed, the memory cell group of the second column is moved to and the addressing according to the row order is similarly performed. Addressing is performed up to the last line in the same manner.

FIG. 9 is a timing chart of signals at the time of writing / reading each memory cell in the conventional semiconductor memory of the above type. In this semiconductor memory, the row address strobe (XRAS, where XRAS is RA
Shows S with top bar. The same applies hereinafter) and addressing is performed by activating one address strobe signal (chip enable signal) XCE without having a column address strobe (XCAS). The figure shows an example of a memory in which the upper bits are assigned to the column address and the lower bits are assigned to the row address, and the row and column addresses are each 4 bits.

First accessed address [0,0]
Is “0” in both the upper digit and the lower digit. By activating the address strobe signal XCE, the address [0, 0] specified by the 8-bit address inputs A1 to A8 is sampled. As a result, 8-bit address outputs AX1 to AX8 are obtained as "0, 0", and accordingly, data writing / writing to the memory cell is performed.
Read-out is performed.

The second accessed address is [0,
1], the upper digit “0” and the lower digit “1” are designated by the address inputs A1 to A8, and the address [0, 1]
The data is written in the memory cell. After that, when all the memory cells having the same column address "0" are sequentially accessed in the same manner, the memory cells having the column address "1" are successively accessed in the same manner. The above operation is repeated for all addresses, whereby data is written in or read from all memory cells. In the above access method, the access at the time of normal operation is described, but the same access method is performed at the time of test operation.

In the conventional semiconductor memory of the above-mentioned type, in order to write / read data in a functional test in which the characteristics are evaluated by using a memory tester or the like, the memory tester needs to have an address terminal of the semiconductor memory. It requires the same number of external signal terminals (drivers).

[0008]

In the conventional semiconductor memory, all address input terminals are used when data is written in or read from each memory cell in the functional test. Therefore, when performing a functional test with a memory tester having limited external signal terminals, the number of external signal terminals that can be used for data input / output is limited by using many external terminals for address input. Therefore, the number of data input or signal evaluation points that can be performed at one time is limited.
Since it is necessary to input data and evaluate signals many times, there is a problem that it takes a lot of time and cost for a functional test.

In view of the above, the present invention is directed to RAS and CAS.
It is a semiconductor memory of a type that does not have a memory and inputs addresses all at once with one address strobe line, and since the number of address signal terminals of the memory tester can be reduced at the time of the test, the number of external signal terminals is limited. It is an object of the present invention to provide a semiconductor memory in which the restriction on the number of data input / output points is small and the data input and signal evaluation need not be repeated many times.

[0010]

In the semiconductor memory of the present invention, an address input section to which a plurality of address input groups constituting one address signal are respectively input, and a normal operation mode and a test operation mode are selected. A mode selection means and an address latch control circuit for simultaneously latching the plurality of address input groups when the normal operation mode is selected and time-divisionally latching the plurality of address input groups when the test operation mode is selected. It is characterized by

When the number of the address input groups is selected to be 2, for example, these can be configured as a column address and a row address, so that a test can be performed similarly to a memory having RAS and CAS.

The address latch control circuit is, for example, an address latch signal generation circuit that generates an address latch signal corresponding to a plurality of address input groups, and an address latch that latches a corresponding address input group based on each address latch signal. In this case, when the normal operation mode is selected, the address latch signal generation circuit receives the activation of the normal address strobe signal and outputs the address latch signals corresponding to the plurality of address input groups all at once. When the test operation mode is selected, each address latch signal is sequentially activated by receiving the normal address strobe signal and at least one test address strobe signal or a plurality of test address strobe signals when the test operation mode is selected.

[0013]

In the semiconductor memory of the present invention, a plurality of address input groups are simultaneously latched in the normal operation mode.
It can be operated like a conventional semiconductor memory without RAS and CAS. On the other hand, in the test operation mode, since a plurality of address input groups are latched in a time-division manner, an external signal required for address input in the memory tester. Even in the case of a memory tester in which the number of terminals is small and the number of external signal terminals is limited, a large number of external signal terminals can be allocated to data input / output according to the number.

[0014]

First Embodiment FIG. 1 is a block diagram showing a semiconductor memory according to a first embodiment of the present invention in a state where its address input terminal is connected to an address signal terminal of a memory tester shown by reference numeral 1.
The semiconductor memory 2 of this embodiment includes an address latch circuit 3 and an address latch signal generation circuit (latch signal generation circuit).
An address latch control circuit composed of 6 is provided, and an 8-bit address input terminal as an external signal terminal and a first
An address strobe signal terminal, a second address strobe signal terminal, and a mode selection signal terminal are provided.

To the address input terminals, a first address input group A1 to A4 forming a row address and a second address input group A5 to A8 forming a column address are input. The normal address strobe signal XCE and the test address strobe signal XTCE are input to the first and second address strobe signal terminals, respectively, and the test mode signal is input to the mode signal selection terminal.

The address latch circuit 3 receives the first address input groups A1 to A4 and latches them.
A latch unit (row address latch unit) 4 and a second address input group A5 to A8 are input and second latched
It is composed of a latch unit (column address latch unit). The first latch unit 4 outputs the first address latch signal XCEA which is the output of the address latch signal generation circuit 6, and the second latch unit 5 outputs the second address latch signal XCEA which is the output of the address latch signal generation circuit 6. The signal XCE is input as a control signal, respectively. Address output groups (row addresses) AX1 to AX4 obtained by latching the address input groups A1 to A4 at the falling timing of the first address latch signal XCE are output from the first latch unit 4, and the second latch unit 5 outputs , Address output groups (column addresses) XA5 to XA8 are output by latching the address input groups A5 to A8 at the falling timing of the second address latch signal XCE.

The address latch signal generation circuit 6 is supplied with a normal address strobe signal XCE, a test address strobe signal XTCE, and a test mode signal. The test mode signal becomes H level when the test operation mode is selected, and becomes L level when the normal operation mode is selected.

FIG. 2 is a logic circuit diagram illustrating the address latch signal generation circuit. The address latch signal generation circuit 6 includes an inverter 61, first and second AND circuits 6
2, 63 and an OR circuit 64. First AN
The first address strobe signal XCE is input to one input of the D circuit 62, and the signal obtained by inverting the test mode signal by the inverter 61 is input to the other input. The test-time address strobe signal XTCE is input to one input of the second AND circuit 63, and the test mode signal is input to the other input.

The outputs of both AND circuits 62 and 63 are O
It is input to the R circuit 64 and its output becomes the first address latch signal (row address latch signal) XCEA. The address strobe signal XCE during normal operation is output as it is as the second address latch signal (column address latch signal) XCE. Therefore, the first address latch signal XCE
A is a signal which is synchronized with the first address strobe signal XCE in the normal operation mode, and is a signal which is synchronized with the test address strobe signal XTCE in the test operation mode.

FIG. 3 is a timing chart of signals in the normal operation mode. In the normal operation mode, the test mode signal is kept at L level and the address strobe signal XTCE at test is kept at H level. When the first address strobe signal XCE is active, the first and second latch units 4 and 5 of the address latch circuit 3 respectively have the first address input groups A1 to A4 (signals a and c) and the second address input groups A1 to A4. Address input groups A5 to A8 (signals b and d) are latched and their outputs AX1 to AX4 and AX5 to AX8, respectively.
Is output to an address buffer (not shown) provided in the next stage. Therefore, in the address buffer, the addresses “b, a”, addresses “d, c”, ... Are fetched collectively for each address. As a result, the semiconductor memory of this embodiment operates in the normal operation mode like the conventional semiconductor memory.

FIG. 4 is a timing chart of signals in the test operation mode of the semiconductor memory of the above embodiment. In the figure, the test mode signal is maintained at the H level, and the address strobe signal XCE, that is, the second
Address latch signal XCE alternately repeats L level and H level. Further, the address strobe signal XTCE at the time of the test is the address strobe signal XCE at the normal time.
Falls to the L level prior to the fall of, and normally rises to the H level at the same time as the address strobe signal XCE. Therefore, as shown in the figure, the first address latch signal XCEA is a signal that falls prior to the second address latch signal XCE and rises at the same time.

From the memory tester, the address signal DI1
Signals a, b, c, ... Are sequentially output as DI4. The signals a and b are the addresses “b,
a ”is designated, and the signals c and d are assigned addresses“ d,
"c" is designated. Address input groups A1 to A4, A5
A8 is the same signal as the address signals DI1 to DI4, respectively. At the first falling edge of the first address latch signal XCEA, the signal a of the address input groups A1 to A4 is latched and output as the row address outputs AX1 to AX4. Subsequently, the falling edge of the second address latch signal XCE causes the signal b of the address input groups A5 to A8 to be latched and output as the column address outputs AX5 to AX8.

Next, the first and second address latch signals XCEA and XCE rise simultaneously, and the first and second address latch signals XCEA and XCE continue to rise.
When the address latch signal XCEA of 1 falls, the signal c of the address signals DI1 to DI4 at that time is latched and output as address outputs AX1 to AX4. Such an operation continues, and each memory cell is sequentially accessed. Before the signal a of the first address output group AX1 to AX4 is changed to the signal c, the address buffers have the first and second address output groups AX1 to AX4 and AX5 to AX8.
Since the signal a and the signal b of 1 are fetched together, it becomes possible to access the memory cell of the address [b, a].

Second Embodiment FIG. 5 shows a semiconductor memory according to a second embodiment of the present invention similarly to the embodiment shown in FIG. The semiconductor memory 8 of this embodiment is
Address latch circuits 10 to 13 are provided in the address latch circuit 9.
Equipped with. In the address latch circuit 9, the first and second latch units 10 and 11 form a row address latch unit, and
The fourth latch units 12 and 13 form a column address latch unit. Address signals DI1 to D from the memory tester 7
I4 is a first address signal group (row address signal) DI
1, DI2 and second address signal group (column address signal)
It is divided into DI3 and DI4.

The row addresses DI1 and DI2 correspond to the first and second address input groups A1, A2 and A3, A4, and are latched by the first and second latch units 10 and 11 to output the row address outputs AX1 and AX1. It becomes AX2, AX3, and AX4. The column addresses DI3 and DI4 correspond to the third and fourth address input groups A5, A6 and A7, A8, and are latched by the third and fourth address latch units 12 and 13 to output the column address outputs AX5, AX6 and It becomes AX7 and AX8. Other configurations are almost the same as the embodiment of FIG.
Detailed description is omitted.

FIG. 6 is a timing chart in the normal operation mode of the semiconductor memory of the second embodiment. The test mode signal is maintained at the L level, and the first and second address latch signals XCEA and XCE are the same signals as the address strobe signal XCE and change at the same timing. The address input groups A1 and A2 receive signals a, e, ..., the address input groups A3 and A4 receive signals b, f, ..., and the address input groups A5 and A6 receive signals c, g ,. .., signals d, h, ... Appear in the address input groups A7 and A8, respectively. For example, each of the signal a, the signal b, the signal c, and the signal d is a 2-bit signal,
The whole is aggregated to form one address signal "dc, ba". These are latch signals XCEA,
Address output AX1 latched simultaneously according to XCE
~ Is output as AX8.

FIG. 7 is a timing chart of signals in the test operation mode of the second embodiment. The test mode signal, each address strobe signal, and each address latch signal are the same as each signal of FIG. The address signals DI1 to DI4 of the memory tester are divided into two groups. The signals a, b, ... Appear at the row addresses DI1 and DI2, and the signals c, d, ... Appear at the column addresses DI3 and DI4. The signal a output from the memory tester as the lower digit of the row addresses DI1 and DI2 is the first address input group A.
The signal c as the lower digit of the column addresses DI3 and DI4 is input to the third address input groups A5, A6 and the fourth address input groups A3 and A4, respectively.
Are input to the address input groups A7 and A8, respectively. At the falling edge of the first address latch signal XCEA, the signal a of the address input groups A1 and A2 is latched by the first latch unit and output as the row address outputs AX1 and AX2 of the lower digits, and at the same time, the address input Signals c of groups A5 and A6
Are latched by the third latch unit and output as the lower digit column address outputs AX5 and AX6.

Next, the memory tester outputs signals b and d as the upper digit address signals DI1, DI2 and DI3, DI4, respectively, and outputs the first and second address input groups A1, A2 and A3, A4, respectively. And to the third and fourth address input groups A5, A6 and A7, A8. Subsequently, the signal b of the address input groups A3 and A4 is latched by the second address latch unit by the falling edge of the second address latch signal XCE, and is output as the row address outputs AX3 and AX4 of the higher digits. At the same time, the signals d of the address input groups A7 and A8 are latched by the fourth address latch unit, and the upper digit column address outputs A7 and A8 are output.
Is output as.

At this time, the address buffer takes in the signals a to d from the respective address outputs. in this case,
The address "dc, ba" constitutes one address.

Third Embodiment FIG. 8 shows a logic circuit diagram of an address signal generation circuit in a semiconductor memory according to a third embodiment of the present invention. In this address signal generation circuit, the number of address input groups is n
1 and 5 in the case of n = 2.
Can be used for semiconductor memory. This address latch signal generation circuit includes an inverter 65 and n + 1 AND circuits 6
6 ₁ , 66 ₂ , ... And n OR circuits 67 ₁ , 6
7 ₂ , ... In the normal operation mode, the address signal generation circuit has a normal address strobe signal XCE.
Is input, and in the test operation mode, n corresponding to the number of groups is input.
Address test strobe signals IN ₁ , IN ₂ ,
・ ・ Is entered.

In the normal operation mode, since the test mode signal is at the L level, the address strobe signal XCE sent from the first AND circuit 66 ₁ is output as the address latch signals XCEA, XCEB, .... Therefore, in each address latch unit, each address input group is collectively latched in synchronization with the address strobe signal XCE. On the other hand, in the test operation mode, the test mode signal is at the L level, and the test-time address strobe signals IN ₁ , IN ₂ , ... Which are sequentially activated are output as the respective address latch signals XCE1, XCE2. Based on the address latch signals XCE1 and XCE2, the address input groups are sequentially time-divisionally latched in the corresponding latch units.

Although the present invention has been described based on its preferred embodiment, the semiconductor memory of the present invention is not limited to the configuration of the above embodiment. For example, it is not always necessary to associate the first and second input groups with row and column addresses, and the semiconductor memory of the present invention is not necessarily limited to an image memory or the like.

[0033]

As described above, according to the semiconductor memory of the present invention, it is possible to reduce the number of address signal terminals required in the memory tester for testing this semiconductor memory. Therefore, the external signal of the memory tester used for data input / output can be reduced. By increasing the number of terminals, it is possible to increase the number of points for data input and signal evaluation at the time of testing. Therefore, the present invention realizes an efficient functional test of a semiconductor memory without RAS and CAS, which is a remarkable effect. Play.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a semiconductor memory of the present invention.

FIG. 2 is a logic circuit diagram illustrating the configuration of an address latch signal generation circuit according to the embodiment of FIG.

3 is a timing chart of signals in a normal operation mode in the semiconductor memory of the embodiment of FIG.

4 is a timing chart of signals in a test operation mode in the semiconductor memory of the embodiment of FIG.

FIG. 5 is a block diagram showing a configuration of a second embodiment of a semiconductor memory of the present invention.

6 is a timing chart of signals in a normal operation mode in the semiconductor memory of the embodiment of FIG.

7 is a timing chart of signals in a test operation mode in the semiconductor memory of the embodiment of FIG.

FIG. 8 is a logic circuit diagram showing a configuration of a test signal generation circuit adopted in a semiconductor memory according to a third embodiment of the present invention.

FIG. 9 is a timing chart of signals in a conventional semiconductor memory.

[Explanation of symbols]

1, 7 Memory tester 2, 8 Semiconductor memory 3, 9 Address latch circuit 4 First address latch unit (row address latch unit) 5 Second address latch unit (column address latch unit) 6, 14 Address latch signal generation circuit 10 to 13 Address latch unit 61, 65 Inverter 62, 63 AND circuit 64 OR circuit 66 ₁ , 66 ₂ AND circuit 67 ₁ , 67 ₂ OR circuit

Claims (3)

[Claims] 1. An address input section to which a plurality of address input groups constituting one address signal as a whole are respectively inputted, a mode selection means for selecting a normal operation mode and a test operation mode, and selection of the normal operation mode. A semiconductor memory comprising: an address latch control circuit which latches the plurality of address input groups at the same time, and latches the plurality of address input groups in a time division manner when the test operation mode is selected. 2. The address latch control circuit corresponds to each of the plurality of address input groups, receives the activation of the normal time address strobe signal when the normal operation mode is selected, and becomes active at the same time, and the normal time address strobe. An address latch signal generation circuit that generates an address latch signal that sequentially becomes active by receiving a signal and at least one test-time address strobe signal or a plurality of test-time address strobe signals; and a corresponding address latch signal generation circuit when each of the address latch signals is active. The semiconductor memory according to claim 1, further comprising an address latch circuit that latches the plurality of address input groups. 3. The semiconductor memory according to claim 1, wherein the address signal is composed of three or more address input groups.