JPS59194200U - Storage device - Google Patents

Storage device

Info

Publication number
JPS59194200U
JPS59194200U JP8643283U JP8643283U JPS59194200U JP S59194200 U JPS59194200 U JP S59194200U JP 8643283 U JP8643283 U JP 8643283U JP 8643283 U JP8643283 U JP 8643283U JP S59194200 U JPS59194200 U JP S59194200U
Authority
JP
Japan
Prior art keywords
address signal
storage device
supply
signal line
pull
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8643283U
Other languages
Japanese (ja)
Inventor
足立 啓一
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP8643283U priority Critical patent/JPS59194200U/en
Publication of JPS59194200U publication Critical patent/JPS59194200U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は捉来の一例を示すブロック図、第2図は本考案
の一実施例を示すブロック図、第3図は第2図に示す実
施例を印刷基板へ実装したときの、斜視図である。 1・・・メモリマトリックス、2.3・・・レジスタ、
4.5・・・デコーダ、6・・・記憶装置、8−1〜8
−6・・・印刷回路、9・・・印刷基板、10・・・プ
ルアップ抵抗、100−1〜100−8・・・アドレス
信号、1011〜10m−8・・・ICリード。
Fig. 1 is a block diagram showing an example of a trap, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 is a perspective view of the embodiment shown in Fig. 2 mounted on a printed circuit board. It is. 1...Memory matrix, 2.3...Register,
4.5...Decoder, 6...Storage device, 8-1 to 8
-6... Printed circuit, 9... Printed circuit board, 10... Pull-up resistor, 100-1 to 100-8... Address signal, 1011 to 10m-8... IC lead.

Claims (1)

【実用新案登録請求の範囲】 アドレス信号に従って情報の書込み読出しが行なわれる
記憶回路と、 前記アドレス信号を供給する複数のアドレス信号線と、 前記アドレス信号線に接続されたリードと、前記アドレ
ス信号線の少なくとも一つに接続され外部からアドレス
信号が供給されないときに予め定められたアドレス信号
を供給するプルアップ抵抗とを含むことを特徴とする記
憶装置。
[Claims for Utility Model Registration] A memory circuit in which information is written and read in accordance with an address signal, a plurality of address signal lines that supply the address signal, a lead connected to the address signal line, and the address signal line. and a pull-up resistor connected to at least one of the above to supply a predetermined address signal when no address signal is supplied from the outside.
JP8643283U 1983-06-07 1983-06-07 Storage device Pending JPS59194200U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8643283U JPS59194200U (en) 1983-06-07 1983-06-07 Storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8643283U JPS59194200U (en) 1983-06-07 1983-06-07 Storage device

Publications (1)

Publication Number Publication Date
JPS59194200U true JPS59194200U (en) 1984-12-24

Family

ID=30216364

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8643283U Pending JPS59194200U (en) 1983-06-07 1983-06-07 Storage device

Country Status (1)

Country Link
JP (1) JPS59194200U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07272498A (en) * 1994-03-30 1995-10-20 Nec Corp Semiconductor memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07272498A (en) * 1994-03-30 1995-10-20 Nec Corp Semiconductor memory

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