JPS63108747A - Gate array integrated circuit - Google Patents

Abstract

PURPOSE:To perform the scanning path test of a junction of a memory circuit to a logic unit by providing a counter for testing a memory and a selector in the memory, and placing a register at the junction. CONSTITUTION:A memory circuit is tested by inputting a clear signal 9 from an external terminal to counters 8 for data and address, initializing it and inputting an enable signal to count it up. At this time, a signal for controlling the memory circuit is so set as to write the signal, written, and the clear signal 9 is then input to the counter 8 for the address again, and when the enable of the counter for the address is inactivated, even if a clock is input, the same value is held. When a memory control signal is so set that the memory circuit 13 reads, the data of address 0 is set in an output register 14. This data can be read out by using a scanning path.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a gate array integrated circuit having a memory therein, and more particularly to a gate array integrated circuit having a circuit for simplifying a memory section therein.

<Prior Art> Conventionally, a scan path method for logic circuits has been used as a method for testing large-scale circuits in gate array integrated circuits with built-in memories.

The scan path method enables the operation of normal sequential circuits and
By making it possible to freely select one of the shift register operations and applying the select signal of the selector from an external terminal, data can be sequentially shifted in from the external input terminal during the shift register operation and input into any sequential circuit. This method tests the inside of the circuit by setting arbitrary data and shifting out the data of the sequential circuit in the sequential circuit to an external terminal.

An outline will be explained based on FIG. 2. First, select signal 24 is set from an external terminal so that selectors 20 and 21 select shift data 22 and 23. Sequential circuit 25
and 26 form a shift register by wiring sequential circuits with selectors in other circuits in the same way, and data is sequentially shifted by inputting a clock 27. Both ends of the shift register are externally connected. It is connected to a terminal, and by sequentially shifting data in from the external terminal, any data can be set in any sequential circuit.

In this way, a certain value is set in the sequential circuit 25. This value is held until the next clock is input to the sequential circuit 25.
The output 23 is input to a combinational circuit group 28. The output of the sequential circuit 25, the output of other sequential circuits, and signals from external terminals are input to the combinational circuit group 28, and a logical value 29 resulting from a combination of the input values is input to another input of the selector 21. be done. Now selector 21
is set by the select signal 24 to select the output 23 of the sequential circuit 25, but if the select signal 24 is changed to select the output 29 of the combinational circuit group 28 and the clock 27 is input once, , the output 29 of the combinational circuit group 28 is set in the sequential circuit 26. Similarly, the output 30 of another combinational circuit group is set in the sequential circuit 25. Here, the select signal 24 is again set to select shift data, and the data set in the sequential circuit is shifted out to the external terminal. In this way, the logic value of the combinational circuit between two consecutive sequential circuits before and after in the shift register can be changed arbitrarily from the external terminal by changing the combination of the input values and taking out the logic value to the external terminal via the register. The method of using sequential circuits wired like shift registers is called the scan path method, although tests within logic circuits can be performed using the scan path.

A common method for testing the memory section is to input memory control signals such as address, write data input, and chip select write enable directly from an external terminal and output them directly to the external terminal for direct testing.

An outline will be explained based on FIG. During normal operation, a select signal 34 is set from an external terminal so that the selector 33 selects the address, write data, and memory control signal 32 from the logic section 31, and is supplied to the memory circuit 35. During a memory test, the selector 33 selects the address, write data, and memory control signal 3 from the external terminal.
The select signal 34 is set to select 6. On the other hand, in addition to being supplied to the logic section 31, the output 37 of the memory circuit is configured to be directly output to an external terminal.

In this way, memory circuit tests are performed directly from external terminals.

<Problems to be Solved by the Invention> The above-described conventional gate array integrated circuit incorporating a memory requires an external terminal for testing the memory section. As the memory capacity increases, the number of external terminals inevitably increases, and even when considering the possibility of sharing the terminals with other terminals, there is a problem in that restrictions on the terminals become greater. Furthermore, since the connection portion between the memory section and the logic section cannot be tested using the scan path method, there is a problem in that it is extremely difficult to test this section.

<Means and operations for solving the problems> A gate array integrated circuit according to the present invention is a gate array integrated circuit comprising a logic section having basic cells arranged in an array and a memory section having a memory circuit. The memory section has a counter and a selector that can be controlled from an external input terminal, a memory circuit input register, and a memory circuit output register, and the selector receives either the signal from the logic section or the counter output signal from the external terminal. freely choose,
It is characterized in that an input signal is input to the memory circuit via a memory circuit input register, and an output signal from the memory circuit is supplied to the logic via a memory circuit output register.

The gate array integrated circuit having the above configuration includes a counter for generating memory test addresses and data inside the LSI, and a selector for selecting between the normal address and data and the address and data generated by the counter. The select signal of the selector can be set directly from an external terminal, and a register is provided at the connection between the selector, the logic section, and the memory circuit. Tests such as writing and reading can be performed in clock synchronization.

<Example> Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a schematic diagram of an embodiment of the present invention. 1. 2 indicates a gate array integrated circuit, 2 indicates a group of input/output buffers, 3 indicates a portion constituting logic, which is referred to as a logic section here, and 4 indicates a group of basic cells, meaning a group of transistors. The logic section 3 implements the circuit by wiring the transistors of the basic cell group 4. 5 is a memory section which is an implementation section of the present invention. For the purpose of simplifying the explanation, a 256 word x 9 bit RAM is considered here, but any memory can be used. It is necessary to input an 8-bit address to the 256-word RAM, and this 8-bit address signal is provided from the logic section 3. Furthermore, memory control signals such as chip select and write enable, and write data during writing are similarly supplied from the logic section 3 to the memory circuit 13. These signals are indicated by 6 in FIG. 1 and are input to the selector 7. Reference numeral 8 indicates a test address and data generation counter, which is assumed here to be composed of an 8-bit counter for addresses and a 9-bit counter for write data. Each counter can be cleared from an external terminal,
By inputting a counter control signal 9 such as an enable signal so that they can operate separately, arbitrary addresses and arbitrary data can be set. The counter outputs of 9 bits on the data side and 8 bits on the address side, together with memory control signals such as chip select and write enable for memory testing from external terminals, form a memory input signal 10 at the time of testing and are input to the selector 7. The counter 8 can be incorporated into the scan canvas by using a sequential circuit for the scan canvas system and inputting the same clock as that of the logic unit 3 to the sequential circuit constituting the counter 8. The selector 7 receives an input signal 6 from the logic section during normal operation, and receives a select signal 11 directly from an external terminal during a memory test so that it can select the memory input signal 10 during the test. The output of selector 7 is
Input to input register 12. The input register 12 can be incorporated into the scan canvas by inputting the same clock as the sequential circuit of the logic unit 3 and using a sequential circuit for the scan canvas method. The output of the input register 12 is sent to the memory circuit 13 (
In this case, it is input to RAM). The read data from the memory circuit 13 is input to the output register 14, which in this case is a 9-bit register. Input register 12
In the same way, an output register 14 is also incorporated into the scan canvas, the output of which is fed to the logic section.

During normal operation of the LSI, the selector 7 selects the input signal 6 from the logic section, so the operation is similar to that of a conventional gate array integrated circuit with a built-in memory. It becomes synchronous.

Next, as an example of a memory test, a select signal 11 is set from the external terminal so that the selector 7 selects the memory test input signal 10 formed by the output of the counter 8 and the memory control signal from the external terminal. Count clear signal and enable signal 9 from external terminal
Therefore, any data can be set in the data counter and any address can be set in the address counter. To test a memory circuit, for example, first input a clear signal to a data counter and an address counter from external terminals, initialize the counters, and input an enable signal to count up each time a clock is input.

At this time, if a memory circuit control signal is set from an external terminal so that the memory performs a write operation, the same data as the address is dedicated to each address in the memory.

After writing, when a clear signal is input to the address counter again, the address counter indicates address 0. Here, when the enable of the address counter is deactivated, the address counter maintains the same value even if a clock is applied. When a memory control signal is set from an external terminal so that the memory circuit performs a read operation and a clock is input only once, data at address 0 is set in the output register. This data can be read by shifting out to an external terminal using the scan path. A write test can be performed by checking each address in the same way. Also, by changing the clock cycle using this method, it is possible to perform a speed test of the write operation.

For the read test, data is written into the memory using the method described above, the memory is set for read operation from an external terminal, and the address counter is counted up. If the clock is stopped when a certain address n is reached, the data at address n-1 is set in the output register 14, assuming that the memory is operating normally. A read test of the memory circuit can be performed by checking the value of the output register 14 using the scan path. Here again, you can test the speed of the read operation by changing the Glock cycle. When the structure of the present invention is used as a memory testing method, various methods can be considered. Since the input register 12 and the output register 14 are incorporated in the scan path, the other parts except the memory circuit 13 can be tested using the scan path. In this way, it is possible to increase the efficiency of LSI testing of gate array integrated circuits.

<Effects of the Invention> As explained above, the present invention provides a gate array integrated circuit with a built-in memory that has a counter and a selector for memory testing in the memory section. By placing a register at the connection part with the logic section of the LSI and incorporating this register into the scan path, it becomes possible to perform a scan path test of the connection part, which has the effect of improving the test efficiency of LSI testing.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing an embodiment of the present invention. FIG. 2 is a block diagram explaining the scan path method. FIG. 3 is a block diagram explaining a conventional test method for the memory section of a gate integrated circuit with built-in memory It is a diagram. DESCRIPTION OF SYMBOLS 1... Gate array integrated circuit, 2... 7 groups of human output buffers (external input/output terminal group), 3... Logic section, 4... Basic cell group. 5...Memory section, 6...Memory input signal from logic section, 7...Selector, 8...Counter for memory test, 9...Counter control signal, 10...Memory for memory test Input signal, 11...
Select signal, 12... Input register, 13... Memory circuit, 14... Output register,

Claims (1)

[Claims] In a gate array integrated circuit comprising a logic section having basic cells arranged in an array and a memory section having a memory circuit, the memory section includes a counter and a selector that can be controlled from an external input terminal, a register for inputting the memory circuit, and a memory section having a memory circuit. It has a memory circuit output register, and the selector freely selects either the signal from the logic section or the counter output signal from an external terminal, and inputs the input signal to the memory circuit via the memory circuit input register. , a gate array integrated circuit characterized in that an output signal of a memory circuit is supplied to logic via a memory circuit output register.