JPH1074398A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize an efficient memory test without adding memory testing input/output terminals by making an address and a data input separate scan chains. SOLUTION: Registers 100, 101, 102 store respectively the address, the data input and a data output of a RAM 110, and constitute the scan chains by using all registers in logic circuits 240, 241. In the RAM 110, when the data are written, a write enable NWE writes the data specified by a data input DI in a write address specified by the address AD at the timing of a logic value O. Further, when the data are read out, the write enable NWE reads out the data from a data output DO at the timing specifying a read-out address in the address AD when the logic value is 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory test for a semiconductor integrated circuit composed of a memory and a logic circuit.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of semiconductor processes,
Large-scale semiconductor integrated circuits in which logic circuits and memories having various functions are integrated on one chip have been developed.
In a large-scale semiconductor integrated circuit, various test methods for facilitating the test are used in order to reduce the time required for the test. As an example of a test method for facilitating test, there is a scan method. In the scan method, flip-flops in a logic circuit are constituted by scan flip-flops, and each scan flip-flop includes a scan chain for sequentially shifting data. By using the scan chain, arbitrary data can be written to each scan flip-flop, and data of each scan flip-flop can be read from the scan chain, thereby facilitating the test of the logic circuit.

The scan method is used not only for testing a logic circuit but also for testing a memory. Usually, a memory test is performed by writing and reading a specific pattern. When performing a memory test using the scan method,
A register around the memory is provided with a scan chain, and writing and reading are performed using the scan chain.
If the scan chain is shared with the logic circuit, it is not necessary to add a terminal for a memory test. However, when the scan chain is shared with the logic circuit, the length of the scan chain increases. When a memory test is performed by the scan method, one memory access requires a shift corresponding to the length of the maximum scan chain, so that there is a problem that the time required for the test is reduced. In particular, when a large-scale memory test is performed, the number of memory accesses required for the test is enormous, and it is necessary to reduce the number of shifts required for one memory access.

As an example, a memory test by a conventional scan method in which a scan chain is shared with a logic circuit is described as an example.
There is a logic device disclosed in JP-A-56-168270. In the above-described conventional example, a register for storing a memory address and data input is arranged at the head of a scan chain, and a register for storing data output of a memory is arranged at the end of a scan chain. As a result, even with a long scan chain shared with a logic circuit, memory access can be performed with a small number of shifts.

[0005]

However, in the above-described configuration, for example, at the time of writing to a memory, in order to specify an address and a data input, a value obtained by adding at least the number of bits of the data to the number of bits of the address is used. Needs a shift. When testing a large-scale memory, it is desirable to minimize the number of shifts required for one memory access.

Therefore, the present invention is newly obtained by focusing on the fact that memory access can be performed with a small number of shifts by using a different scan chain for a register for storing a memory address and data input / output. It is a thing.

Further, according to the present invention, when the number of bits of a memory address and the number of data input / output bits are different, the larger number of bits is divided and each is provided with a scan chain.
By newly setting the number of bits of the divided register to be equal to or smaller than the smaller number of bits, it is possible to perform memory access with a smaller number of shifts.

Accordingly, an object of the present invention is to provide a semiconductor integrated circuit which realizes an efficient memory test without adding an input / output terminal for a memory test.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit including a memory, a first logic circuit, and a second logic circuit. The register for storing the address of the memory, the register for storing the data input of the memory, the register for storing the data output of the memory, and at least some of the registers in the first logic circuit and the second logic circuit are scan flip-flops. A register for storing an address of the memory in the scan flip-flop, a first scan chain for shifting data in the order of the register in the first logic circuit, a register for storing a data input of the memory, and a second logic. A second scan chain for shifting data in the order of the register in the circuit and the register for storing the data output of the memory; Those were.

According to a second aspect of the present invention, there is provided a semiconductor integrated circuit including a memory, a first logic circuit, and a second logic circuit, wherein a register for storing a memory address and a data input to the memory are provided. And a register for storing the data output of the memory, and at least some of the registers in the first logic circuit and the second logic circuit are constituted by scan flip-flops. A register for storing, a first scan chain for shifting data in the order of the registers in the first logic circuit, a register for storing an address of the memory, a register in the second logic circuit, and a register for storing a data output of the memory , And a second scan chain that shifts data in the following order.

Further, according to a third aspect of the present invention, in a semiconductor integrated circuit including a memory and a logic circuit, a register for storing a memory address, a register for storing a data input of the memory, and a data output of the memory are provided. And at least some of the registers in the plurality of logic circuits are configured by scan flip-flops,
Set the address and data bit width of the memory to NA and ND, respectively.
(NA and ND are positive numbers) If NA ≧ ND, the scan flip-flop stores in the scan flip-flop at least a part of the register below the ND bit which is a part of the register for storing the memory address, and at least a part of the register in the logic circuit. A plurality of address scan chains for shifting data in the order of registers, a register for storing data input of the memory, and a data input scan chain for shifting data in the order of at least some of the registers in the logic circuit, In the case of ≦ ND, the scan flip-flop has a register for storing the address of the memory, an address scan chain for shifting data in the order of at least some of the registers in the logic circuit, and a register for storing the data input of the memory. At least one of the registers below the NA bit that is part of the register in the logic circuit And a plurality of data input scan chains for shifting data in the order of the registers of the section.

Further, in the semiconductor integrated circuit according to the present invention, when NA ≧ ND, the data output of the memory is output to one of the plurality of address scan chains or the data input scan chain. Is connected to a data output scan chain composed of registers for storing the data of the memory, when NA ≦ ND, at least an output of the address scan chain or the plurality of data input scan chains. It is desirable to connect a data output scan chain composed of a register of NA bits or less, which is a part of a register for storing an output.

According to the first or second aspect of the present invention, the number of registers associated with a memory per scan chain can be reduced because the address and the data input are set to different scan chains. And the number of shifts required for memory access can be reduced.

When writing with the above configuration, the address and data input are set using different scan chains, respectively, and memory access is performed. The number of shifts required for one memory access is at least the address and data input. The number of shifts to be set, that is, the number of shifts corresponding to the larger number of bits of the address and the data input is required. Therefore, when the difference between the number of bits of the address and the data input is large, regardless of whether the smaller number of bits can be set with a smaller number of shifts, the number of shifts required for one memory access is at least the larger number of bits. Since the number of shifts is equal to the number of bits, memory access becomes inefficient.

According to the third aspect of the present invention, by dividing the larger number of bits by the above configuration, the number of shifts required for memory access is further reduced, and the number of bits of the divided register is reduced. By making the number of bits smaller than the smaller number of bits, the number of registers related to the memory in each scan chain can be matched, and efficient memory access is achieved.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit according to one embodiment of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 9 is a configuration diagram of a semiconductor integrated circuit using a scan method according to the embodiment. In the figure, Scan-IN1, Scan-IN2
Is a scan input, and Scan-OUT1 and Scan-OUT2 are scan outputs. Reference numerals 100 to 102 and 203 to 206 denote registers constituted by scan flip-flops, and a scan input Scan-IN1.
The scan chain that shifts the data from the scan input 100 to 203 and 204 and outputs it to the scan output Scan-OUT1, and shifts the data from the scan input Scan-IN2 to 101, 205, 206 and 102 in the order of scan output Scan -Equipped with a scan chain that outputs to OUT2. 110 is address AD, data input D
I, a data output DO, and a random access memory (hereinafter referred to as RAM) having a write enable NWE. 120
Selects a write enable NNWE during normal operation and a write enable TNWE during memory test using a switching signal RAMTEST between normal operation and memory test, and
Is a selection circuit for setting the write enable NWE. In a normal operation, the switching signal RAMTEST is set to a logical value 0, and in a memory test, the switching signal RAMTEST is set to a logical value 1. twenty three
0 and 231 are combinational circuits, and 240 is combinational circuit 2.
Reference numeral 241 denotes a logic circuit including a combinational circuit 231 and registers 205 and 206. Registers 100, 101, and 102 each have R
A register for storing the address, data input, and data output of the AM 110, and the registers 203 to 206 are logic circuits 240, 2
It is a register in 41. In the present embodiment, the logic circuit 24
Although the scan chain is configured using all the registers in 0 and 241, it may be configured using at least a part.

FIG. 2 shows a circuit diagram of the registers 100 to 102 and 203 to 206. In the figure, IN [i] and OUT [i] (0≤i≤n-1) are register input and register output, SEN is scan enable, SIN and SOUT are scan input and scan output, and CLK is Clock input. 401, 402, 403,
404 is a scan flip-flop. The registers are
During normal operation, the scan enable SEN is used with a logical value of 0, and during the scan operation, the scan enable SEN is used with a logical value of 1. Register input during normal operation
IN [i] (0 ≦ i ≦ n−1) is latched in synchronization with the clock CLK and output to the register output OUT [i] (0 ≦ i ≦ n−1). During the scan operation, data from the scan input SIN is input to the scan flip-flop and shifted sequentially in synchronization with the clock CLK, and the data of the scan flip-flop is sequentially output from the scan output SOUT. That is, a scan chain that shifts data from the scan input SIN and outputs it to the scan output SOUT is provided, and the scan operation writes data from the scan input SIN to the scan flip-flop and reads data from the scan flip-flop from the scan output SOUT be able to.

FIG. 3 shows a circuit diagram of the scan flip-flop. In the figure, SE is scan enable, D, SD
Is a data input during normal operation, a data input during scanning, Q is a data output, and CK is a clock input. 301
Is a D flip-flop, and 302 is a selection circuit. When the scan enable SE has the logical value 0, the selection circuit 302 selects the data input D in the normal operation. When the scan enable SE has the logical value 1, the selection circuit 302 selects the data input SD in the scan operation. D flip-flop 301 is clock C
In synchronization with K, the selection result of the selection circuit 302 is latched and output to the data output Q.

The operation of the semiconductor integrated circuit using the scanning method configured as described above during a memory test will be described below.

First, FIG. 4 shows a RAM 11 used in the embodiment.
Indicates an operation of 0. The operation shown in the figure is the operation of the asynchronous RAM. When writing data, the data specified by the data input DI is written to the write address specified by the address AD at the timing when the write enable NWE has the logical value 0. When reading data, write enable
Data is read from the data output DO at the timing when the read address is specified by the address AD when NWE is the logical value 1.

A description will be given of a memory test by the above-described RAM scanning method. Note that the RAM has, as an example, three bits each of the address and data bits.
A 2-bit one is used. That is, register 100 is 3
Bits (n = 3), 2 bits for registers 101 and 102 (n = 2)
Use the one with the configuration.

FIGS. 5 and 6 show the write and read operations during the memory test, respectively. In the figure, CLK is a clock input, RAMTEST is a switching signal for normal operation and memory test, TNWE is a write enable during memory test,
Scan-EN is scan enable, Scan-IN1 and Scan-IN2 are scan inputs, and Scan-OUT1 and Scan-OUT2 are scan outputs. Ramad, ramdi, and ramdo are RAM110 respectively.
Register, which stores the address, data input, and data output of the register. The register for storing the address and data input / output of the RAM 110 has a scan chain in which the scan input is the least significant bit, the data is shifted from the lower bit to the upper bit, and the most significant bit is the scan output.

The operation for performing the write operation shown in FIG. 5 will be described. When performing writing, first, in synchronization with the clock CLK, an address for writing is input from the scan input Scan-IN1, and a data input for writing is input from the scan input Scan-IN2. In the shift operation using the scan chain, the data from the scan input Scan-IN1 is shifted from the lower order to the upper address, and the data from the scan input Scan-IN2 is shifted from the lower order to the upper order of the data input. Therefore, input the address to be written from the scan input Scan-IN1 in the order of the lower A2, A1, A0 from the upper address, and input the scan input Scan in the order of the lower D1, D0 from the upper data.
-Input data input to write from IN2. After the register output ramad and ramdi become the write address and data input respectively, write enable TNWE
Is set to the logical value 0 to write data.

The operation in the case of performing the reading shown in FIG. 6 will be described. When reading is performed, first, the scan enable Scan-EN is set to a logical value 1, and an address to be read is input from the scan input Scan-IN1 in synchronization with the clock CLK. As in the case of writing, the address to be read is input from the scan input Scan-IN1 in the order of A2, A1, and A0 from the top of the address. Register output rama
After d becomes the address to be read out, the scan enable Scan-EN is set to the logical value 0. As a result, the register 102 storing the data output of the RAM 110 latches the read data as in the normal operation. Subsequently, the scan enable is again set to the logical value 1, the shift operation is performed, and the data read from the scan output Scan-OUT2 is output. In the shift operation using the scan chain, since the data output shifts from the lower order to the upper order, the data output is output from the scan output Scan-OUT in the order of the lower order D1 and D0 from the upper order.

As described above, the write and read operations in the memory test have been described in the case of performing one memory access. Subsequently, an operation when writing or reading is performed continuously will be described.

FIGS. 7 and 8 show the operations of continuous writing and continuous reading during the memory test, respectively. In FIG. 7, input 1, input 2, and input 3 are an address and a data input that are continuously input.
Write 3 is a write timing corresponding to each input. In FIG. 8, input 1, input 2, input 3
Is an address input continuously, and read 1,
Read 2 and Read 3 are read data corresponding to the respective inputs.

Assuming that one cycle from the rise of the clock CLK to the next rise is one cycle, when performing the write of FIG. 7, the cycle in which the write enable TNWE is set to the logical value 0 can be overlapped with the next input.
Further, by inputting an address from the scan input Scan-IN1 and inputting a data input from the scan input Scan-IN2, input of the address and the data input can be performed in parallel. Therefore, a write cycle necessary for one memory access in the case of performing continuous writing is a cycle value of a larger value of the number of bits of the address and the number of bits of the data input. In the example shown in the figure, the number of bits for address and data input is 3 bits and 2 bits, respectively, and the write cycle is 3 cycles.

In the case of performing the reading shown in FIG. 8, several cycles for outputting data can be performed by overlapping with the next input. Therefore, the read cycle required for one memory access in the case of performing the continuous read is the scan enable Sc in the cycle of the larger value of the number of bits of the address and the number of bits of the data output.
This is a cycle of a value obtained by adding one cycle for setting an-EN to the logical value 0. In the example shown in the figure, the number of bits of the address and the data output are 3 bits and 2 bits, respectively, and the read cycle is 4 cycles.

As described above, according to the present embodiment, RA
Scan input of register to store M address Scan-I
Scan input Sc for scan chain from N1 to scan output Scan-OUT1, register for storing data input / output
By assigning to the scan chain from an-IN2 to the scan output Scan-OUT2 and setting the register that stores the address and data input / output to another scan chain, the address and data input can be set in parallel. Writing can be performed with a small number of shifts and a small number of cycles. In the conventional example, the write cycle is five cycles of the value obtained by adding the number of bits of the data to the number of bits of the address, whereas in the present embodiment, the number of write cycles can be three.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 9 is a configuration diagram of a semiconductor integrated circuit using a scan method according to a second embodiment of the present invention. FIG. 1 showing the first embodiment shows a configuration diagram of an entire semiconductor integrated circuit including a RAM, but FIG. 9 shows only a scan chain in the semiconductor integrated circuit. FIG.
Is a scan chain in the case where the number of bits of the address of the RAM is larger than the number of bits of data. The description will be made on the assumption that the number of bits of the address is n + m and the number of bits of the data is n (n and m are positive numbers).

FIG. 9 differs from FIG. 1 in that FIG. 1 assigns a register for storing an address to a scan chain from scan input Scan-IN1 to scan output Scan-OUT1. The register that stores the address is divided into two, and one is scanned in. Scan-IN1
Scan chain from to the scan output Scan-OUT1,
Scan out the other side from scan input Scan-IN2
This is the point assigned to the scan chain up to -OUT2.
Along with this, the register for storing the data input / output is changed from the scan input Scan-IN2 to the scan output in FIG.
In Fig. 9, the scan input from Scan-IN3 was assigned to the scan chain up to Scan-OUT2.
This is the point assigned to the scan chain up to Scan-OUT2.

In FIG. 9, reference numerals 500 to 506 denote registers constituted by scan flip-flops.
A scan chain that shifts the data from Scan-IN1 in the order of 500, 504 and outputs it to the scan output Scan-OUT1, and shifts the data from the scan input Scan-IN2 in the order of 501 and 505 to the scan output Scan-OUT2 Scan chain to output and data from scan input Scan-IN3 502, 50
It has a scan chain that shifts in the order of 6, 503 and outputs it to the scan output Scan-OUT3. Registers 500 and 501 are R
Registers for storing the address of the AM, 502 and 503 are registers for storing data input and data output of the RAM, respectively, and registers 504, 505 and 506 are at least some registers in the logic circuit. n and m indicate the number of bits of the register, that is, the number of scan flip-flops.

A register for storing the address of the RAM is
It is divided into two registers 500 and 501, and each is assigned to a different scan chain. The number of bits of the divided register is set to be equal to or less than the number of bits of data. In FIG. 9, for n-bit data, the address of (n + m) -bit is set to n.
Bit and m bits, respectively, and scan input Sca
Scan chain from n-IN1 to scan output Scan-OUT1, scan input Scan-IN2 to scan output Scan-OUT2
Up to the scan chain.

The operation of the semiconductor integrated circuit using the scanning method configured as described above during a memory test will be described below. Note that, as in the first embodiment, the RAM uses three bits and two bits of address and data, respectively, and the upper two bits of the address are the register 500 and the lower one bit is the register 501. And so on.

FIGS. 10 and 11 show the operations of continuous writing and continuous reading during the memory test, respectively. FIG.
11 differs from FIGS. 7 and 8 in that the upper two bits of the address from the scan input Scan-IN1 and the scan input
The point is that the lower one bit of the address is input from Scan-IN2. In connection with this, in FIG.
A data input is input from an-IN3, and a data output is output from a scan output Scan-OUT3 in FIG. FIG.
In FIGS. 0 and 11, those having the same functions as those in FIGS. 7 and 8 are denoted by the same reference numerals, and detailed description thereof will be omitted.

When the write operation shown in FIG. 10 is performed, the upper two bits of the address are input from Scan-IN1 and the lower one bit of the address is input from Scan-IN2, so that the upper and lower bits of the address are input in parallel. Can be. Also, Sc
By inputting data input from an-IN2, input of address and data input can be performed in parallel. Since the upper and lower divided addresses each have 2 bits or less, which is the number of bits of the data input, the address can be set with the number of shifts necessary for setting the data input. Therefore, a write cycle necessary for one memory access in the case of performing continuous writing is a cycle of the value of the number of bits of data input. In the example shown in the figure, the number of data input bits is 2 bits, and the write cycle is 2 cycles. This is a reduction of one cycle from the three cycles of the first embodiment (FIG. 7).

In the case of performing the read operation shown in FIG. 11, as in the case of performing the write operation, the upper two bits of the address are input from Scan-IN1 and the lower one bit of the address is input from Scan-IN2. Can be performed in parallel. The data output is output from Scan-OUT2, and the data output and the input of the next address can be performed by overlapping. Since the upper and lower divided addresses each have 2 bits or less, which is the number of bits of the data output, the next address can be input with the required shift number for the data output. Therefore, the read cycle is a cycle of a value obtained by adding one cycle for setting the scan enable Scan-EN to a logical value 0 to the number of bits of the data output, which is necessary for one memory access in the case of performing the continuous read. In the example shown in the figure, the number of bits of the data output is 2 bits, and the read cycle is 3 cycles. This is a reduction of one cycle from the four cycles of the first embodiment (FIG. 8).

As described above, according to the present embodiment, RA
When the number of bits of the address of the address M is larger than the number of bits of the data, the register for storing the address is divided, and the scan chain is provided for each, so that the address can be input in the upper bits and the lower bits in parallel. In addition, memory access can be performed with a small number of shifts and a small number of cycles. In the division of the register for storing the address, by setting the number of bits of the divided register to be equal to or smaller than the bit width of the data, the number of shifts required for setting the address and the data input at the time of writing can be improved.
At the time of reading, the number of shifts required for data output and input of the next address can be matched, and efficient memory access can be achieved.

In the second embodiment, the case where the number of bits of the address of the RAM is larger than the number of bits of the data is described. However, when the number of bits of the data is larger than the number of bits of the address, the register for storing the data is used. And the scan chains are respectively provided, and the number of bits of the register after division may be set to be equal to or less than the number of bits of the address.
FIG. 12 shows a configuration diagram of a semiconductor integrated circuit using a scan method when the number of bits of data in the RAM is larger than the number of bits of an address. In the figure, 600 to 604 and 504 to 506 are registers constituted by scan flip-flops, and include three scan chains as in FIG.

In the first and second embodiments,
Selection circuit for controlling write enable NWE of RAM110
Although 120 is provided, a scan flip-flop for storing a write enable may be provided and incorporated so as to be the first half of the scan chain.

Further, in the first and second embodiments, the asynchronous RAM is used as the memory.
However, a read-only memory (ROM) may be used. ROM
When the memory test is performed, the register 101 for storing the data input and the selection circuit 120 are not required in the first and second embodiments.

In the first and second embodiments, the output of the register storing the input of the RAM is directly connected to the input of the RAM, and the input of the register storing the output of the RAM is directly connected to the output of the RAM. However, logic such as a selection circuit may be inserted between the RAM and the register. At the time of the memory test, the same memory test can be performed by controlling the logic between the RAM and the register so as to perform the same operation as when the RAM and the register are directly connected.

In the first embodiment, one scan chain is assigned to an address, and one scan chain is assigned to a data input and a data output.
Although one scan chain is provided, one scan chain may be provided for data input, and one scan chain may be provided for address and data output.

In addition, in the second embodiment, the register is divided into two. However, the register is divided into three or more as necessary so that the number of bits of the divided register is equal to or less than the number of bits of the undivided register. Needless to say, this may be done.

The smaller of the number of bits of the address and the data is not divided, but the smaller one is divided, and the larger one is divided so that the number of bits is equal to or less than the divided bit number, and each may be provided with a scan chain. . It is important to match the number of shifts required for the input and output of the address and data after division, whereby efficient memory access can be performed.

[0048]

As described above, the present invention provides a register for storing an address of a memory, a first scan chain for shifting data in the order of a register in a first logic circuit, a data input to a memory, and a second logic. By providing a second scan chain for shifting data in the order of the register in the circuit and the register for storing the data output of the memory, the input of the address and the data input can be performed in parallel, and the input / output for the memory test can be performed. An efficient memory test can be realized without adding a terminal.

According to the present invention, if the bit widths of the memory address and data are NA and ND (NA and ND are positive numbers), the memory address is stored in the scan flip-flop when NA ≧ ND. A plurality of address scan chains for shifting data in the order of at least some of the registers in the logic circuit; a register for storing data input of the memory; A scan chain for data input that shifts data in the order of at least some of the registers is provided.If NA ≦ ND, a scan flip-flop stores a memory address, at least a part of a register in a logic circuit. Stores address scan chains that shift data in register order, and memory data inputs By providing multiple scan chains for data input that shift data in the order of registers below the NA bit that is part of the register and at least some of the registers in the logic circuit, the address and data input can be set during writing And the number of shifts required for data output and input of the next address at the time of reading can be matched, and more efficient memory access can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor integrated circuit using a scan method according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a register in the embodiment.

FIG. 3 is a circuit diagram of a scan flip-flop according to the embodiment;

FIG. 4 is a timing chart for explaining the operation of the RAM according to the embodiment;

FIG. 5 is a timing chart for explaining a write operation at the time of a memory test in the embodiment;

FIG. 6 is a timing chart for explaining a read operation during a memory test according to the embodiment;

FIG. 7 is a timing chart for explaining an operation of continuous writing at the time of a memory test according to the embodiment;

FIG. 8 is a timing chart for explaining an operation of continuous reading in a memory test according to the embodiment;

FIG. 9 is a configuration diagram of a semiconductor integrated circuit using a scan method according to a second embodiment of the present invention.

FIG. 10 is a timing chart for explaining an operation of continuous writing at the time of a memory test according to the embodiment;

FIG. 11 is a timing chart for explaining an operation of continuous reading during a memory test in the embodiment.

FIG. 12 is a configuration diagram of a semiconductor integrated circuit using a scan method of another form according to the second embodiment.

[Explanation of symbols]

100 to 102, 203 to 206, 500 to 506, 6
00 to 606 Register composed of scan flip-flops 110 Random access memory (RAM) 120, 302 Selection circuit 230, 231 Combination circuit 240, 241 Logic circuit 401 to 404 Scan flip-flop 301 D flip-flop

Claims (5)

[Claims] In a semiconductor integrated circuit including a memory, a first logic circuit, and a second logic circuit, a register for storing an address of the memory, a register for storing a data input of the memory, and a data output of the memory are provided. The register to be stored and at least some of the registers in the first logic circuit and the second logic circuit are constituted by scan flip-flops, and the scan flip-flops store the address of the memory in the first flip-flop. A first scan chain that shifts data in the order of registers in the logic circuit, a register that stores data input of the memory, a register in the second logic circuit, and a register that stores data output of the memory. A semiconductor integrated circuit comprising a second scan chain for shifting data. 2. A semiconductor integrated circuit including a memory, a first logic circuit, and a second logic circuit, wherein a register for storing an address of the memory, a register for storing a data input of the memory, and a data output of the memory are provided. The register to store, and at least some of the registers in the first logic circuit and the second logic circuit are constituted by scan flip-flops, and the scan flip-flop stores a data input of the memory in the scan flip-flop. A first scan chain for shifting data in the order of registers in one logic circuit, a register for storing an address of the memory, a register in the second logic circuit, and a register for storing a data output of the memory A semiconductor integrated circuit comprising a second scan chain for shifting data. 3. A semiconductor integrated circuit including a memory and a logic circuit, wherein a register for storing an address of the memory, a register for storing a data input of the memory, a register for storing a data output of the memory, and the plurality of logic circuits are provided. At least some of the registers are constituted by scan flip-flops. If the bit widths of the address and data of the memory are NA and ND (NA and ND are positive numbers), the scan flip-flop A plurality of address scan chains for shifting data in the order of at least some of the registers in the logic circuit, the registers being equal to or less than the ND bit which is a part of the register for storing the address of the memory; A register for storing a data input, a register for at least a part of registers in the logic circuit, A scan chain for data input that sequentially shifts data, and when NA ≦ ND, the scan flip-flop stores data in the register for storing the address of the memory and at least some of the registers in the logic circuit in this order. A plurality of data inputs for shifting data in the order of the address scan chain to be shifted, a register of NA bits or less which is a part of a register for storing data input of the memory, and at least a part of registers in the logic circuit. A semiconductor integrated circuit comprising a scan chain for use in a semiconductor device. 4. When NA ≧ ND, a data output scan chain including a register for storing a data output of the memory is provided at one of the plurality of address scan chains or the data input scan chain. If NA ≦ ND, at least a part of the output of the address scan chain or the plurality of data input scan chains has an NA bit or less, which is a part of a register for storing a data output of the memory. 4. A semiconductor integrated circuit according to claim 3, wherein a data output scan chain comprising said register is connected. 5. The semiconductor integrated circuit according to claim 1, further comprising a control circuit for controlling writing and reading of said memory.