JPH0249520B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is applied, for example, to a pattern generator of an IC testing device, and is used to transfer pattern data from a large-capacity pattern file storing pattern data to a pattern memory for generating pattern data to be supplied to an IC under test. The present invention relates to a pattern data transfer device used to transfer pattern data.

<Prior Art> A conventional pattern data transfer device is shown in FIG. A pattern memory 1 that can be accessed at high speed from a pattern file 11 that is a large capacity storage device such as a magnetic disk or magnetic tape.
When transferring pattern data to a, 1b, 1c, and 1d, conventionally the central processing unit (CPU)
12 reads pattern data from the pattern file 11, and provides the pattern data and necessary control signals to the transfer interface 13, and the transfer interface 13 transfers the pattern data from the central processing unit 12 to the pattern memories 1a through the data bus 14. 1d to each data input terminal D,
Further, a common address is given to each address terminal A of the pattern memories 1a to 1d from the address bus 16 through the pattern control circuit 15, and the transfer interface 13 is connected to each of the pattern memories 1a to 1d.
It is connected to the write control terminal W of the write control terminal W by write control lines 2a to 2d, and one of these write control lines 2a to 2d is selected to apply a write pulse.

First, a common address is specified for the pattern memories 1a to 1d, and at the same time, a write pulse is applied to the write control line 2a for the pattern memory 1a to write the pattern data on the data bus 14 at that time to the pattern memory 1a.
Next, after changing the pattern data on the data line 14, a write pulse is applied to the write control line 2b to write the pattern data in the pattern memory 1b, and thereafter in the same manner, pattern data is sequentially written in the pattern memories 1c and 1d, and then The addresses on the address bus 16 are changed and pattern data is sequentially written into the pattern memories 1a to 1d in the same manner.

After writing the required pattern data into the pattern memories 1a to 1d in this way, the central processing unit 12 supplies data indicating timing according to the IC under test to the timing generator 17 via the transfer interface 13, and generates a timing signal. generate. The timing signal generated by the timing generator 17 is applied to the pattern control circuit 15, from which an address for reading is generated according to a predetermined procedure, and the address is applied to the address bus 16 to control the pattern memories 1a to 1d. Read it out more often. This read pattern data is applied to the corresponding terminal pin of the IC under test 18 through a drive circuit not shown in the figure.
Data indicating the expected value for the output from IC 18 is supplied to a comparator, not shown.

In order to perform IC testing efficiently, there are cases where multiple ICs of the same type are tested simultaneously.
In this case, for example, as shown by the dotted line in Figure 1,
ICs 18a and 18b are provided, and test pattern data and expected values from pattern memories 1a and 1b are output to IC 18a under test, and pattern memories 1c and 18b are provided.
From 1d, test pattern data and expected values are output to the IC under test 18b. This IC under test
Since the ICs 18a and 18b are of the same type, the pattern data sequentially applied to them is also the same. Therefore, the pattern data to be written in pattern memories 1a, 1b and pattern memories 1c, 1d is also the same.

In the case of writing the same pattern data in this way, according to the conventional transfer device, after writing a series of pattern data to the pattern memories 1a and 1b, the same series of pattern data is written to the pattern memories 1c and 1d again. Write data, that is, transfer the same pattern data 2 times.
I needed to turn it. By the way, the process of reading pattern data from the pattern file 11 and further transferring it to the pattern memories 1a, 1b, 1d is relatively slow, and the transfer time is relatively long to transfer a long series of pattern data. Transferring the data twice is undesirable because it reduces the efficiency of the test apparatus as a whole.

<Summary of the Invention> An object of the present invention is to make it possible to transfer a series of pattern data with one transfer control when writing the same pattern data to a plurality of pattern memories, thereby shortening the transfer time. For example,
The present invention provides a pattern data transfer device that can be applied to an IC test device to shorten the overall test time.

According to this invention, a write selector is provided corresponding to each pattern memory, and all the write control lines from the transfer interface are connected to the input side of the selector, and the output side of the selector is the write control terminal of the corresponding pattern memory. , and one of the write control lines can be selectively connected to the write control terminal by a selection control signal. In addition, the selection control signal that performs selection for this write selector is given to the selection control signal generation section from the transfer interface with information indicating the number of identical patterns to be stored in the entire pattern memory,
A selection control signal is generated in accordance with information indicating the number of identical patterns. As a result, one write control line is simultaneously connected to the write control terminals of one or more selected pattern memories, thereby making it possible to simultaneously write the same pattern data to a plurality of pattern memories at the same address position.

<Embodiment> For example, as shown in FIG. 2 with the same reference numerals attached to the parts corresponding to those in FIG.
Write selectors 3a to 3d are provided corresponding to d, respectively. Write selectors 3a to 3
Each input side of d is a transfer interface 13
All of the write control lines 2a to 2d are connected to the input side. Each of the write selectors 3a to 3d has one output side, and is connected to the corresponding write control terminal W of the pattern memories 1a to 1d, respectively. These write selectors 3a to 3d are provided with a selection control signal generator 1.
A selection control signal is applied through each of the selection control lines 4a to 4d from 9, and one of the write control lines 2a to 2d on the input side of each write selector 3a to 3d is selectively connected to a line on the output side. Can be done. The selection control signal generator 19 has a pattern memory 1 from the transfer interface 13.
Information indicating the number of times to write the same pattern as a to 1d as a whole is input, and corresponding write control signals are generated on control lines 4a to 4d, respectively, in accordance with the information.

In this configuration, for example, the pattern memory 1a,
1b and the pattern memories 1c and 1d, the pattern data to be stored is outputted to the data bus 14 and the corresponding address is sent through the address control circuit 15 as in the past. The same pattern data and the same address are generated on the address bus 16, and therefore the same pattern data and the same address are applied to the pattern memories 1a to 1d. At this time, a write pulse is generated only on one write control line, for example 2a, as in the conventional case.

In this example, pattern memories 1a to 1d
In this case, information indicating that the same pattern data is stored in two of the pattern memories 1a to 1d as a whole is given to the selection control signal generation section 19, and the selection control signal generation section 19 sends write control to the control line 4a. The signal that selects the line 2a is the control line 4b.
A signal that does not select any write control line is applied to the control line 4c, a signal that selects the write control line 2a is applied to the control line 4d, and a signal that does not select any write control line is applied to the control line 4d. Therefore, write control line 2a is connected to write control terminals W of pattern memories 1a and 1c through write selectors 3a and 3c, respectively. Therefore, when a write pulse is generated on the write control line 2a, the pattern data on the data bus 14 at that time is transferred to the address bus 16 for the pattern memories 1a and 1c.
Written as specified by the address above. Next, the address on the address bus 16 is updated, pattern data to be written next is given to the data bus 14, and a write pulse is given again to the write control line 2a, so that the pattern memory 1
The pattern data can be written to pattern memories 1a and 1c in the same manner.
Write the same pattern data sequentially to

When writing to the pattern memories 1a and 1c is completed in this way, a signal that does not select any write control line is sent to the control line 4a from the selection control signal generator 19, and a signal is sent to the control line 4b to select the write control line 2.
A signal for selecting the write control line 2b is applied to the control line 4c, a signal for selecting no write control line is applied to the control line 4d, and a signal for selecting the write control line 2b is applied to the control line 4d. Therefore, the write control line 2b is selected in the write selectors 3b and 3d and connected to the write control terminal W of the pattern memories 1b and 1d, respectively. In this state, the same pattern data is stored at the same address location in the pattern memories 1b and 1d by performing the same operation as in the past after writing to the pattern memory 1a is completed and writing to the next pattern memory 1b. will be written to.

The device of the present invention is different from the conventional device by providing write selectors 3a to 3d and a selection control signal generation section 19, and providing information indicating the number of identical pattern data from the transfer interface 13 to the selection control signal generation section 19. For example, the same series of pattern data written in the pattern memories 1a and 1b is stored in the pattern memories 1c and 1.
d can be written at the same time.

Note that the number of pattern memories is not limited to four, but can be any number, and the number of identical patterns written simultaneously can also be arbitrary. For example, in FIG. It is possible to write data. The selection control signal generating section 19 generates a control signal corresponding to the number of identical patterns to be stored.
This can be configured, for example, by using information indicating the number of identical patterns from the transfer interface 13 to sequentially read out the memory and generate a necessary selection control signal.

It is also possible to select each bit within one word in each pattern memory. For example, regarding the pattern memory 1a, as shown in FIG. 3, the pattern memory has 1 word and 3 bits, and therefore the pattern memory consists of three memory planes, each of which has write control terminals W ₁ , W ₂ , W. ₃ , and the write selector 3a has selector parts 3a ₁ , 3a ₂ ,
There are three types: 3a ₃ . These selector parts 3
Write control lines 2a to 2d are connected to the input sides of a ₁ , 3a ₂ , and 3a ₃ , and the selector units 3a ₁ to 3a ₃ individually select the write control signal lines by the selection signal from the selection control signal generator 19 . you can choose,
Each output side of the selector sections 3a ₁ , 3a ₂ , 3a ₃ is connected to write control terminals W ₁ to W ₃ , respectively. In this way, it is also possible to freely select the write bit position. In addition, the pattern length may not be an integral multiple of one word length, but even in that case, the same data can be simultaneously written to multiple locations in the pattern memory as a whole by selecting the bit arrangement within one word. Can be done.

<Effects> As described above, according to the pattern data transfer device of the present invention, multiple pieces of the same pattern data can be written to multiple pattern memories at the same time, and when transferring the same pattern data, the transfer time is It only needs to be done once, requires only a small amount of hardware, and can significantly shorten the transfer time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional pattern data transfer device, FIG. 2 is a block diagram showing an example of the pattern data transfer device according to the present invention, and FIG. 3 is a block diagram showing a partial modification thereof. 1a to 1d: pattern memory, 2a to 2
d: write control line; 3a to 3d: write selector; 4a to 4d: selection control line. 11: Pattern file, 12: Central processing unit, 13: Transfer interface, 14: Data bus, 15: Pattern control circuit, 17: Timing generation circuit, 1
6: address bus, 19: selection control signal generator.

Claims (1)

[Claims] 1 Pattern data is commonly given as write data from the transfer interface to a plurality of pattern memories, addresses are specified to these pattern memories from the transfer interface, and each write data is provided corresponding to each of the pattern memories. Select one of the control lines from the above transfer interface and generate a write pulse to it;
In a pattern data transfer device for transferring pattern data to a pattern memory, a pattern data transfer device is provided corresponding to each of the pattern memories, the write control line is connected to the input side, and the output side is connected to the write control terminal of the corresponding pattern memory. and a write selector that selects one of the write control lines on the input side according to a selection control signal and connects it to the write control terminal on the output side, and information indicating the number of identical pattern data stored in the entire pattern memory. A pattern data transfer device comprising: a selection control signal generating section which outputs selection control signals to the write selectors according to the information given from the transfer interface.