JPH0411959B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which the same data can be simultaneously written to a plurality of memory cells during a functional test of the memory cells. It is something.

[Prior Art] FIG. 4 is a schematic block diagram mainly showing the electrical configuration of an input (write) circuit of a conventional semiconductor memory device.

First, the configuration of the semiconductor memory device shown in FIG. 4 will be explained. In Fig. 4, input data W
is applied to the data input buffer 2 via the data write terminal 1. In response, the data input buffer 2 outputs the input data W and a signal obtained by inverting W. The signal W output from the data input buffer 2 is further connected to transistors 3, 5,
given to one conduction terminal of each of 7 and 9,
The signal output from data input buffer 2 is further applied to one conduction terminal of each of transistors 4, 6, 8 and 10. transistor 3
The output from the other continuity terminal of each of 4 and 4 is
After being outputted through preamplifier 11, it is coupled to a selected 1-bit memory cell in memory cell block 15. Similarly, the output from the other conductive terminal of each of transistors 5 and 6 is amplified via preamplifier 12 and then coupled to a selected 1-bit memory cell in memory cell block 16, The output from the other conduction terminal of each of transistors 9 and 8 is output through preamplifier 13 and then coupled to a selected 1-bit memory cell in memory cell block 17, The output from each other conduction terminal is amplified via preamplifier 14 before being applied to a selected one of memory cell blocks 18.
The bit memory cells are coupled to each other. The transistors 3 and 4 are turned on and off by the memory cell selection circuit 1.
The on/off of transistors 5 and 6 is controlled by the output signal C ₂ of the memory cell selection circuit 20, and the on/off of transistors 7 and 8 is controlled by the output signal C ₁ of the memory cell selection circuit 20. The on/off state of the transistors ₉ and 10 is controlled by the output signal C ₄ of the memory cell selection circuit 22.
Terminal 23 receives address signal A _R , terminal 24 receives address signal _R , and terminal 25 receives address signal
A _C is given the address signal _C to the terminal 26,
Depending on these address signals, one of the memory cell selection circuits 19 to 22 is selected and driven.

Next, the operation of the conventional semiconductor memory device shown in FIG. 4 will be explained. At the time of data writing, input data W is applied to the data writing terminal 1. The data input buffer 2 then outputs a complementary signal set (W,). In this state, the signal (W,
In order for W) to reach and be written to the selected memory cell in each memory cell block, transistors 3-10 must be on. In a conventional semiconductor memory device, one address signal specified by address signals A _R , _R , A _C , and _C
A set of transistors (for example, transistors 3 and 4) is turned on by one memory cell selection circuit, and data is written only to the selected 1-bit memory cell in memory block 15. Next, by changing the address signal, other memory cell selection circuits are sequentially designated, and data is sequentially written one bit at a time into the selected memory cell in each memory cell block.

By the way, in general, conventional semiconductor memory devices
Functional tests of memory cells are performed in the wafer state before the semiconductor memory device is assembled into a package. This functional test is executed by exchanging signals between a memory test device (not shown) and the semiconductor storage device. For example, first, all memory cells constituting a semiconductor memory device are set to a certain logic value (for example, "0") by a memory tester.
Write. Next, it is determined whether the memory cell is functioning normally by reading out the memory cell one bit at a time and checking whether it matches a previously written logic value. In a conventional semiconductor memory device, writing of data to each memory cell for the above-mentioned functional test was performed via the conventional data input circuit shown in FIG.

[Problems to be Solved by the Invention] As mentioned above, in the conventional semiconductor memory device, test data had to be written to a plurality of memory cells one bit at a time during a functional test of the memory cells. As the capacity of semiconductor memory devices increases, there has been a problem in that the time required for functional testing of each semiconductor memory device becomes extremely long.

Therefore, the main object of the present invention is to solve the above-mentioned problems and write the same data into multiple memory cells at the same time by simultaneously driving multiple memory cell selection circuits during a memory cell function test. It is an object of the present invention to provide a semiconductor memory device which can significantly shorten functional test time.

[Means for Solving the Problems] A semiconductor memory device according to the present invention has a function of simultaneously driving a memory cell selection circuit during a function test of a memory cell.

[Function] In addition to the normal writing means that selects one memory cell from a plurality of memory cells one by one and writes data, the present invention provides a function of driving all memory cell selection circuits simultaneously. So,
The same data can be written into memory cells of multiple bits at the same time.

[Embodiment] FIG. 1 is a schematic block diagram showing the electrical configuration of a semiconductor memory device which is an embodiment of the present invention.

The configuration of the embodiment shown in FIG. 1 is the same as the configuration of the conventional semiconductor memory device shown in FIG. 4 except for the following points. That is, the drive signal generation circuits 27 to 3 are used instead of the memory selection circuits 19 to 22.
0 is provided, and the TM signal is applied from the test mode switching signal (TM signal) input terminal 31 to each of the drive signal generation circuits 27 to 30.

Next, an outline of the operation of the embodiment shown in FIG. 1 will be explained. The TM signal is a signal that rises to a high level in the test mode, and in a case other than the test mode (hereinafter referred to as normal mode), that is, when the TM signal is at a low level, each of the drive signal generation circuits 27 to 30 operate in the same manner as the memory selection circuits 19 to 22 in FIG.
That is, when the TM signal is at a low level, one drive signal generation circuit selected by the address signals A _R , _R , A _C , and _C operates to control the associated transistor set to be in the on state, and as described above. The input data is written into the selected memory cell in one of the memory cell blocks designated by the address signal of , using the conventional procedure.

On the other hand, in the test mode, that is, when the TM signal rises to a high level, all of the drive signal generation circuits 27 to 30 generate signals C ₁ to C that drive the respective related transistor sets to the ON state regardless of the address signal. Output ₄ at the same time. That is, when the TM signal is at a high level, transistors 3 to 10 are all turned on, and the output signal (W,) of data input buffer 2 is written to the selected memory cells of all memory cell blocks 15 to 18. It will be.

Since the drive signal generation circuits 27 to 30 all have the same circuit configuration, a detailed circuit diagram of the drive signal generation circuit 27 is shown in FIG. 2 as an example.

First, the configuration of the drive signal generation circuit 27 shown in FIG. 2 will be explained. The circuit shown in Figure 2 is
It mainly consists of a drive signal generation section 32, a memory cell selection section 33, and a latch circuit 34. A TM signal is applied to the terminal 35 from the terminal 31 in FIG. This TM signal is the transistor 36
is applied to the control terminal of transistor 37 via.

On the other hand, low level signals are applied to both terminals 38 and 39 when address signals A _R and A _C are signals for selecting the drive signal generation circuit. That is, in this case, transistors 40 and 41 are in an off state. Terminal 42 is supplied with a basic clock signal φ that determines memory cell write timing. Transistor 43 is turned on and off by this clock signal φ, and one conduction terminal of transistor 43 is coupled to transistors 40, 41 and 44. The other conductive terminal of transistor 44 is connected to transistor 45.
is coupled to the control terminal of Terminals 46, 47, 48
and 49 are given high level signals.
The latch circuit 34 includes a terminal 50 that supplies a high-level signal, a terminal 51 that receives the above-mentioned basic clock signal φ, and transistors 52 and 53, and receives a signal controlled by the clock signal φ. This is a circuit for setting the terminal 54 to a low level in advance before outputting _C1 .

Next, the operation of the circuit shown in FIG. 2 will be explained. First, in the normal mode, that is, when the TM signal is at a low level, the transistor 37 is turned off. Instead, the memory cell selection unit 33 functions as a normal memory cell selection circuit, and when the drive signal generation circuit 27 is selected by the address signal, the transistors 40 and 41
Both are turned off, and a high level signal is applied to the control terminal of the transistor 45 in accordance with the clock signal φ, so that the transistor 45 is turned on.
In response, a high level signal C ₁ is output from terminal 54 to turn on related transistors 3 and 4.

On the other hand, in the test mode, that is, while the TM signal is at a high level, the transistor 37 is always on, and a high level signal _C1 is always output to the terminal 54, regardless of the address signal, and the related transistor 3 and 4 are turned on.

Next, FIG. 3 is a circuit diagram of a drive signal generating circuit that turns on related transistors only when writing to a memory cell is performed in the above-described test mode. In FIG. 3, the signal φ _W is a signal that becomes high level when actually writing to the memory cell in the test mode. The configuration of the circuit diagram shown in FIG. 3 is the same as the configuration of the circuit diagram shown in FIG. 2 except for the following points. That is, the signal φ _W is applied to one conduction terminal of the transistor 36 via the terminal 55, and the TM signal is applied to the control terminal of the transistor 36 via the terminal 56. Therefore, only when both the TM signal and φ _W are at high level, the drive signal C ₁ is output from the terminal 54 to turn on the related transistors 3 and 4.

In the above embodiment, a semiconductor memory device in which data is written into a 4-bit memory cell from one data write terminal has been described, but this may be any number of bits, and the format of the semiconductor memory device may also vary.
It can be anything.

Furthermore, it is clear that the test time can be further shortened by providing a means for reading multiple bits in parallel.

[Effects of the Invention] As described above, according to the present invention, by providing a drive signal generation circuit with a simple circuit configuration,
Since the same data can be written to multiple bits of memory cells at the same time, the time required to write memory cells during testing can be shortened, and the time required for functional testing of large-capacity semiconductor storage devices can be greatly reduced. Can be shortened.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing the electrical configuration of an embodiment of the present invention. FIGS. 2 and 3 are circuit diagrams of a drive signal generating circuit constituting an embodiment of the present invention. FIG. 4 is a schematic block diagram showing the electrical configuration of a conventional semiconductor memory device. In the figure, 1 is a data write terminal, 2 is a data input buffer, 11, 12, 13, 14 are preamplifiers, 15, 16, 17, 18 are memory cells,
19, 20, 21, 22 are memory cell selection circuits;
23, 24, 25, 26 are address signal input terminals, 27, 28, 29, 30 are drive signal generation circuits, 31 is a test mode switching signal input terminal, 3
Reference numerals 2 and 32' indicate a drive signal generation section, 33 a memory cell selection section, and 34 a latch circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A data write terminal for receiving input data, a multi-bit memory cell divided into a plurality of blocks, and a plurality of memory cells that connect the plurality of blocks to the data write terminal in parallel. an input line; a plurality of transistor means provided corresponding to the plurality of input lines, each having a conduction path and a control terminal inserted into each of the input lines; and receiving an address signal in a normal mode. A drive signal for supplying a signal specifying a specific block among the plurality of blocks to the control terminal of the plurality of transistor means and simultaneously specifying all of the plurality of blocks in response to a test mode signal in a test mode. drive signal generation means for supplying to the control terminals of the plurality of transistor means, the drive signal generation means comprising signal generation means for generating a timing signal representing the timing of writing data to the data write terminal. A semiconductor memory device further comprising: generating the drive signal in response to the timing signal.