JP2000065904A - Semiconductor tester - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pattern generator for semiconductor testers having constitution for reading out stored data of a low-speed pattern memory and transferring it to a cash high-speed memory, and capable of preventing the occurrence of useless errors by an error check in reading the low-speed pattern memory. SOLUTION: The pattern generator of this tester is provided with a low-speed pattern memory 20 at comparatively low-speed and in a large capacity, and a high-speed memory 40 of cash memory construction which generates a test pattern at a device test speed, and is constituted by fitting an address pointer(AP) 10 which performs read and transfer from the low-speed pattern memory 20 to the cash memory section 40k of the high-speed memory 40 continuously from a specified address in order, and a means of performing a parity check at the time of read and transfer. On this occasion, an unwritten address controlling means 7 which stop-controls read by the AP 10 is provided for addresses of the low-speed pattern memory 20 where parity information is not being stored.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a pattern generator for a semiconductor test device. In particular, the present invention relates to a pattern generator of a semiconductor test apparatus having an error check function of stored data stored in an enormous capacity pattern memory.

[0002]

2. Description of the Related Art In the prior art, a configuration example of a pattern generator using a large-capacity low-speed pattern memory and a high-speed memory shown in FIG. 4, a time chart for reading the low-speed pattern memory by an address pointer and a parity detection shown in FIG. This will be described below with reference to FIG. Since the semiconductor test apparatus is well-known and well-known in the art, the description of the configuration of the entire system is omitted.

The main configuration of the pattern generator according to the present invention is as follows.
As shown in FIG. 4, a storage medium 100, an address pointer (AP) 10, a low-speed pattern memory 20, a parity memory 22, a parity determination unit 24, a sequencer 3
0, a high-speed memory (cache memory) 40, and a cache controller 42.

The storage medium 100 is, for example, a hard disk, and stores a plurality of test pattern files for each test item corresponding to a device under test. In addition, LAN
WS (workstation) via (network)
There is also a mode in which the test pattern file on the side is transferred.

[0005] The AP 10 continuously prefetches the contents of the low-speed pattern memory 20 to read the cache memory 40 described later.
Generate a sequential address to store in
A hold control input terminal for hold-controlling the count-up; an ascending counter having a length of, for example, m = 30 bits, which can be initially set to a desired address value from the outside;
An address signal 10a is supplied to the low-speed pattern memory 20.

The low-speed pattern memory 20 has a predetermined large-capacity memory required for device testing. This has a relatively low access time of about several tens of nanoseconds, but has a large capacity of, for example, 32 M words. Although the word width of the memory varies depending on the test apparatus, the number of channels of the pattern output from the pattern generator is set to, for example, 1000.
If it is a channel, it is as large as 1000 × 3 = 3000 bits wide. The transfer time to the large-capacity memory requires a long time of tens of minutes to several hours. For this reason, pattern data corresponding to the device test items is transferred and stored in advance before the device test. When the contents stored in the low-speed pattern memory 20 are output to the cache memory 40 and the parity determination unit 24, the output is performed using the address signal 10a from the AP 10. In addition, the test pattern 40pat which is output from the pattern generator
A plurality of pattern data 20pat (see FIG. 5F) in parallel with P times the number of channels is supplied to the cache memory 40. The parallel output of the P-phase interleaved configuration enables the low-speed pattern memory 20 to operate at a low speed of 1 / P with respect to the actual device test speed. As the value of the P phase, 4, 8, 16 and the like are used. still,
FIG. 5F shows an example in which four phases are used.

The parity memory 22 has the same memory capacity as the low-speed pattern memory 20. This bit width has a parity memory of 1 bit for every 16 bit width of the plurality of pattern data 20pat. Therefore, in the case of a 3000-bit width, a 188-bit width is provided. For the writing to the parity memory 22, for example, a parity generator circuit is provided for each 16-bit width, the pattern data 100pat read from the storage medium 100 is received, and the parity information is written simultaneously with the writing to the low-speed pattern memory 20. Is set. Note that the storage medium 10 includes parity information regardless of the parity generator circuit.
There is also a form of reading from 0 and storing. By the way, at the beginning of the power-on of the system, the contents of the low-speed pattern memory 20 and the parity memory 22 are in an undefined state.
In the example of FIG. 5, parity information is set (P1 to Pn) for AP addresses 1 to n, and an unwritten AP address n
At +1 (see FIG. 5C), it is in an undefined state.

The parity checker 24 checks the stored data for errors. Each time data is read from the low-speed pattern memory 20 by the address signal 10a by the AP 10, the contents of the address, for example, a plurality of patterns of 3000 bits wide, are read. In response to the data 20pat and the parity data 22p having a width of, for example, 188 bits read from the corresponding parity memory 22, a parity check is performed, and if there is a parity error, a parity error signal Perr is notified to the system. . The parity error signal Perr is used for system control such as immediately stopping the device test. The information once stored in the low-speed pattern memory 20 may be held all day or for several days or more, and may be subjected to a device test while operating day and night. For this reason, accidental erroneous test patterns must not occur, and management of stored data by the above-described parity check is important for maintaining test quality. In addition to the error check method of the stored data by the parity memory 22 and the parity determination unit 24, there is also a configuration method that is an error check method of the stored data by the CRC method.

The sequencer 30 is a micro-pattern generation control unit capable of controlling various pattern generations by a desired pattern program.
(Program counter), index register and other counters / registers. Although the internal configuration and detailed description are omitted, the sequencer supplies a high-speed address signal 30a to the cache memory 40. In addition, a control signal for controlling the buffer of the cache memory 40 is supplied to the cache controller 42. These signals are the test speed of the device, eg, 200M
Hz high-speed signal.

The cache memory 40 is a high-speed memory for generating a test pattern 40pat at a device test speed, and has a memory capacity of, for example, about several K words. Internally, the cache memory unit 40k on the cache side
And an output memory unit 40m on the side of generating and outputting the test pattern 40pat. By alternately switching the at least two memories, a long test pattern can be obtained at a device test speed of, for example, 200 MHz. 40 pat is generated and realized.

In one cache memory unit 40k, A
The low-speed pattern memory 20 is successively and sequentially accessed by the address signal 10a by P10, and receives the read-out P-times parallel plural pattern data 20pat and stores it in the internal memory in cache. In the output memory unit 40m on the other pattern generation side, the test speed of the device from the sequencer 30, for example, 20
In response to the 0 MHz high-speed address signal 30a, the test pattern 4 is read out of the memory contents corresponding to this address.
0pat is sequentially generated and output. In the example shown in FIG. 5G,
Interleaving occurs at a clock cycle four times that of the low-speed pattern data 20pat. As described above, by alternately controlling the two memories, a long and large test pattern stored in the low-speed pattern memory 20 can be generated at a high device test speed.

Here, FIG. 5 will be described. FIG.
In the multiple pattern data 20 pat shown in FIG. 5, an example of P = 4 phases, addresses 1 to n (see FIG. 5B) of the AP 10 are written address spaces read and stored from the storage medium 100, and the address n-1 and thereafter. Is an unwritten address space that has never been stored.
At this time, in the parity data 22p output from the parity memory 22, normal parity data is set for each of P1 to Pn up to before FIG. 5A, but in FIG. It is in. Under the above conditions, the address values 1 to 1 of the low-speed pattern memory 20 are controlled by the
Up to n are continuously read and transferred to the cache memory 40, and a parity check is performed at the same time. By the way, the AP 10 continuously generates sequential addresses for prefetching due to the pipeline operation, and the low-speed pattern memory 20 receives this address and prefetches and outputs the contents of the address. At the same time, a parity check is being performed. For this reason, the address content of the address n + 1 (see FIG. 5B) is also read, but at this address n + 1, indeterminate parity data (see FIG. 5C)
As a result of the parity check, the parity error signal Per
r occurs. However, if the entire address space of the low-speed pattern memory 20 has been written at least once, the problem that the parity error signal Perr occurs does not occur.

The cache controller 42 receives the control signal from the sequencer 30 and performs the above-described alternate switching control of the two types of cache memories and the buffer storage control to one of the pattern storage side cache memories. In addition, in the pattern storage, a hold signal 42h is supplied to a hold control input terminal of the AP 10 in order to temporarily stop the AP 10 when the storage in the cache memory is completed.

[0014]

SUMMARY OF THE INVENTION As described above,
Regardless of whether a conventional pattern generator is used or not, it is necessary to perform initialization for once writing to the entire address space of the huge low-speed pattern memory 20 at the beginning of power-on. This initialization takes tens of minutes to several hours. This may be useless when testing DUTs that require a relatively small test pattern. In this respect, the conventional pattern generator has practical difficulties. Accordingly, an object of the present invention is to provide a pattern generator having a configuration in which data stored in a low-speed pattern memory is read and transferred to a high-speed memory for caching. An object of the present invention is to provide a pattern generator of a semiconductor test apparatus capable of preventing occurrence.

[0015]

First, in order to solve the above-mentioned problems, in the configuration of the present invention, a relatively low-speed and large-capacity low-speed pattern memory 20 in a pattern generator is tested at a device test speed. The high-speed memory 40 having a cache memory configuration for generating the pattern 40pat is provided.
A pattern generator of a semiconductor test apparatus including an address pointer (AP) 10 for sequentially reading and transferring data sequentially from a predetermined address to 0k and a means (for example, a parity memory 22 and a parity determination unit 24) for performing a parity check at the time of read transfer. In the low-speed pattern memory 20 in which no parity information is stored,
The semiconductor test apparatus is provided with an unwritten address management means 70 for stopping and controlling the reading by the semiconductor device 10. According to the above-mentioned invention, in the pattern generator having the configuration of reading out the data stored in the low-speed pattern memory 20 and transferring the data to the high-speed memory 40 for cache, it is possible to prevent the occurrence of unnecessary errors due to the error check in the reading of the low-speed pattern memory 20. It is possible to realize a pattern generator of a semiconductor test apparatus that can make it possible.

FIGS. 1 and 3 show a solution according to the present invention. Second, in order to solve the above problem, in the configuration of the present invention, a low-speed pattern memory 20 and a high-speed memory (for example, a cache memory) 40 are provided in the pattern generator, and the low-speed pattern memory 20 has at least a device test. With relatively slow and large memory capacity,
A parity memory 22 for performing a parity check at the time of reading is provided. The pattern data 100pat for a test pattern is received from an external storage medium 100 and stored in a buffer. The pattern data is supplied to the high-speed memory 40 by a test pattern generated and output by a pattern generator. A plurality of pattern data 20pat of a predetermined number P times the number of channels of 40pat are output in parallel, and the high-speed memory 40 stores the test pattern 40 at the device test speed.
It is a high-speed and relatively small memory that can generate pat,
The high-speed memory 40 has two systems of a cache memory unit 40k for caching and an output memory unit 40m for generating the test pattern 40pat. The two memories are alternately switched to perform a test at a device test speed. A pattern 40pat is generated and output, and one cache memory unit 40k includes an address pointer (AP) 10 for sequentially reading and transferring sequentially from a predetermined address.
A plurality of pattern data 20pa read from the low-speed pattern memory 20 by an address signal 10a of 0
In response to the reading of t, the data is stored in the memory while caching in a predetermined manner.
m, the pattern generator of the semiconductor test apparatus which receives the high-speed address signal 30a from the sequencer 30 and generates and outputs a test pattern 40pat from which the memory content corresponding to the address has been read is sent from the storage medium 100 or the like to the low-speed pattern memory 20. There is a semiconductor test apparatus including an unwritten address management means 70 for controlling the stop of reading by the AP 10 for an address in which storage is not stored.

FIG. 2 shows a solution according to the present invention. The unwritten address management means 70 includes a stop address register 72 that can set a predetermined address value to be compared with the address pointer (AP) 10 through, for example, a tester bus. The semiconductor test apparatus according to claim 1, further comprising a coincidence detecting means 74 for receiving and comparing both the address signal 10a and the stop address register, and supplying a hold signal to the AP 10 for bringing the AP 10 into a hold state when the two coincide with each other. There is a pattern generator on the device.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings together with embodiments.

In the present invention, an example of the configuration of the main part of the pattern generator in FIG. 1, an example of the configuration of the unwritten address management means in FIG. 2, and a time chart and hold for reading the low-speed pattern memory by the address pointer in FIG. This will be described below with reference to a relationship diagram with signals. Elements corresponding to the conventional configuration are denoted by the same reference numerals.

As shown in FIG. 1, the main configuration of the pattern generator according to the present invention is such that an unwritten address management means 70 is added to the conventional components. The unwritten address management means 70 is provided in the low-speed pattern memory 20.
The sequential address generation generated by the AP 10 is controlled based on the information on the end address of the valid data stored in the AP.

FIG. 2A shows an example of this specific configuration. The configuration of the unwritten address management unit 70 includes a stop address register 72, a coincidence detection unit 74, and a flip-flop 76.

The stop address register 72 is a register of, for example, m = 30 bits, which can be set from the outside. The stop address register 72 receives the final storage address information at the time of storage in the low-speed pattern memory 20 and transfers the stop address value to this register. set.

The coincidence detecting means 74 is an m-bit comparator which receives an m = 30-bit address signal 10a from the AP 10 at one input terminal, and receives the m-bit length signal from the stop address register 72. The other input terminal receives the stop address value, compares the two, and outputs a match signal when they match.

The flip-flop 76 is, for example, an RS flip-flop. The flip-flop 76 sets the output of the flip-flop according to the coincidence signal, connects the write signal 72w to the stop address register 72 to the reset input terminal, and receives the signal. To clear the output state. The output of the hold signal 70h is supplied to the hold input terminal of the AP 10.

Next, the AP based on the hold signal 70h
The operation of the ten address signals 10a will be described with reference to FIG. Here, as in the conventional case, addresses 1 to 10 of the AP 10 are used.
It is assumed that n is an already written address space, and that an address after address n-1 is an unwritten address space that has not yet been stored. Also, the stop address register 7
It is assumed that a stop address value of a value n is set in advance for 2. Under the above conditions, the low-speed pattern memory 20 starts reading from the address value 1 of the address signal 10a and proceeds continuously to the address value n. Eventually, when the address n is reached, a match is detected by the match detecting means 74 and the hold signal 70h is set (FIG. 3E).
reference). As a result, the AP 10 is held in the hold state with the address value n, and the subsequent address values remain n. As a result, since the reading is repeatedly performed with the address value n which is the already written address, no parity error occurs. As a result, it is no longer necessary to carry out initialization writing to the unwritten address space as in the related art.

According to the configuration of the present invention, the pattern generator having the unwritten address management means 70 is used to transfer and write predetermined pattern data required for device testing to the low-speed pattern memory 20. Alone, the device test can be performed normally without causing a parity error.
There is an advantage that it is not necessary to perform initialization once to write all address spaces of 0. Therefore, the time required for initialization as in the prior art can be eliminated, and the convenience is improved. In particular,
This is effective in a device test in which a small memory capacity is sufficient for the entire memory capacity of the low-speed pattern memory 20. Further, the present invention is also effective in a test mode in which the power of the system is frequently turned on again.

The means for realizing the present invention is not limited to the above embodiment. For example, as shown in the configuration example of FIG. 2B, a configuration may be adopted in which a control register 73 is provided and its output state is connected to the reset input terminal of the flip-flop 76. In this case, the low-speed pattern memory 20
After the entire address space has been written once,
Since an unnecessary parity error does not occur, the hold signal 70h can be always disabled.

As shown in the configuration example of FIG. 6, a hold signal 70h output from the unwritten address
Is supplied to the parity determination unit 24 and the parity error signal P
It may be configured to stop occurrence of err.

[0029]

According to the present invention, the following effects can be obtained from the above description. As described above, according to the present invention, the pattern generator having the unwritten address management means 70 is used to transfer and write predetermined pattern data required for device testing to the low-speed pattern memory 20. The device test can be normally performed without causing a parity error only by performing the above operation. Therefore, there is obtained an advantage that it is not necessary to perform initialization once to write all address spaces of the huge low-speed pattern memory 20 once. Therefore, there is obtained an advantage that a pattern generator of a semiconductor test apparatus capable of preventing useless errors from occurring due to an error check when reading the low-speed pattern memory 20 can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration example of a main part of a pattern generator according to the present invention.

FIG. 2 is a configuration example of an unwritten address management unit according to the present invention.

FIG. 3 is a diagram showing a relationship between a time chart for reading a low-speed pattern memory using an address pointer and a hold signal according to the present invention;

FIG. 4 is a configuration example of a main part of a conventional pattern generator.

FIG. 5 is a relationship diagram between a conventional time chart for reading a low-speed pattern memory using an address pointer and parity detection.

FIG. 6 is a configuration example of a main part of another pattern generator according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Address pointer (AP) 20 Low-speed pattern memory 22 Parity memory 24 Parity judgment part 30 Sequencer 40 High-speed memory (cache memory) 40k Cache memory part 40m Output memory part 42 Cache controller 70 Unwritten address management means 72 Stop address register 73 Control Register 74 coincidence detecting means 76 flip-flop 100 storage medium

Claims (3)

[Claims] 1. A pattern generator comprising: a relatively low-speed, large-capacity low-speed pattern memory in a pattern generator; and a high-speed memory having a cache memory configuration for generating a test pattern at a device test speed. A pattern generator of a semiconductor test apparatus having an address pointer (AP) for successively reading and transferring a predetermined address from a predetermined address to a cache memory unit and a means for performing a parity check at the time of the read transfer, wherein no parity information is stored. A semiconductor test apparatus, comprising: an unwritten address management means for stopping reading by the AP for an address of the low-speed pattern memory. 2. A pattern generator comprising a low-speed pattern memory and a high-speed memory in the pattern generator, wherein the low-speed pattern memory includes a relatively low-speed and large-capacity memory capable of at least a device test, and performs a parity check at the time of reading. It has a memory, receives pattern data for a test pattern from an external storage medium, stores it in a buffer, and supplies the high-speed memory with a plurality of pattern data having a predetermined multiple of the number of channels of the test pattern generated and output by the pattern generator. The high-speed memory is a high-speed memory capable of generating a test pattern at a device test speed. The high-speed memory has two systems: a cache memory unit for caching and an output memory unit for generating a test pattern. Memory, and alternately switch between the two memories to test pattern at the device test speed. The cache memory unit has an address pointer (AP) for successively reading and transferring the data sequentially from a predetermined address, and reads out the plurality of pattern data read from the low-speed pattern memory by an address signal from the AP. The semiconductor memory receives and stores the data in the memory while caching it in a predetermined manner. At the same time, the other output memory receives a high-speed address signal from the sequencer and generates and outputs a test pattern from which memory contents corresponding to the address are read. A pattern generator of a test apparatus, comprising: an unwritten address management means for controlling stop of reading by the AP for an address in which storage from the storage medium to the low-speed pattern memory is not stored. Testing equipment. 3. An unwritten address management means includes: a stop address register capable of setting a predetermined address value to be compared with an address pointer (AP); an address signal supplied by the AP to a low-speed pattern memory; 3. The semiconductor test apparatus according to claim 2, further comprising: coincidence detecting means for receiving and comparing the two signals, and setting the AP to a hold state when the two signals coincide with each other.