WO1991007754A1

WO1991007754A1 - Read-while-write-memory

Info

Publication number: WO1991007754A1
Application number: PCT/US1990/002939
Authority: WO
Inventors: Mark S. Birritella; Jan A. Wikstrom
Original assignee: Cray Research, Inc.
Priority date: 1989-11-13
Filing date: 1990-05-24
Publication date: 1991-05-30

Abstract

A random-access memory device capable of concurrent reading and writing. The device consists of a READ address input latch, a WRITE address input latch, a READ address decoder, a WRITE address decoder, a memory matrix capable of simultaneously reading and writing data, a comparator for detecting when the WRITE address and the READ address are the same, and a bypass circuit for sending the WRITE input data to the READ data output line when the READ address and the WRITE address are the same.

Description

READ-WHILE-WRITE-MEMORY FIELD OF THE INVENTION

The present invention relates to the design of Random Access Memory (RAM) devices. In particular, the present invention relates to a RAM design having concurrent READ and WRITE capability.

BACKGROUND OF THE INVENTION Modern digital computers, require structures for storing digital information. Various well-known methods of storing and retrieving information are available to the designer. However, when the application requires that digital information be temporarily stored for subsequent quick retrieval, Random Access Memory (RAM) is generally used. A RAM device usually consists of one or more semiconductor devices which are connected to form a storage cell. Large numbers of such cells may be formed into memories. Each cell has a unique address or memory location. The RAM device provides structures for storing data at various address locations. Digital information may be written into a selected address (WRITE) , and may be read from a specific location (READ) .

A conventional RAM device generally has only one address decoder for selecting the specific memory cell to undergo either a READ or WRITE operation. Additionally, the data path to the memory cells during a WRITE operation, is identical with the data path for the READ operation.

Therefore, in conventional RAM devices it is not possible to READ and WRITE concurrently. Typically, 1ΗD and WRITE operations are performed on separate clock phases. This synchronous operation is not always desirable since it can slow overall system performance and/or cause increased complexity. In some applications, such as high speed computer memory, it may be desirable to perform READ and WRITE operation simultaneously The ability to READ and WRITE concurrently can increase overall sysstem performance.

SUMMARY OF THE INVENTION The READ-WHILE-WRITE RAM of the present invention includes: a compare means; an output means; a memory means having WRITE data inputs, READ data outputs, and READ and WRITE address ports. In operation the RAM device can write data into a memory address or READ data stored at an address. These two activities can overlap in time and can occur synchronously σ asynchronously with other logic operations. The compare means compares the address information on the READ and WRITE address ports, setting the memory bypass flag when the READ and WRITE address data match. A match sets the memory bypass flag. When the data does not match the flag is cleared. The state of the memory bypass flag selects between two sources of output data. The output means is coupled to the memory array and to the input latch. When the memory bypass flag is set the data to be written to the address is concurrently avalible at the data output bus. The memory means writes data into memory, stores the data at specified address locations, and reads data stored in specified address locations.

BRIEF DESCRIPTION OF THE DRAWINGS The previously mentioned features of the present invention will become more apparent with reference to the accompanying drawing and the following description thereof. The sole figure, FIGURE 1 is a block diagram of an illustrative embodiment of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT In the following detailed description of the preferred embodiment, reference is made to the sole FIGURE which forms a part hereof, and in which the invention may be practiced. This embodiment is described in sufficient detail to enable those skilled in the art to practice the invention and it is to be understood that other embodiments may be utilized without departing from the spirit and scope of the present invention. The following detailed description is therefore not to be taken in a limiting sense and the scope of the present invention is defined by the appended claims.

Referring to the sole FIGURE, there is shown a memory 10, which incorporates the present invention. Data to be written to the memory is presented to the device through a data input bus 12. Data read from the device is placed on a data output bus 14.

When the chip enable (CE) signal 16 is present on the input latch 21, the WRITE data on the data input bus 12 is clocked into the input latch 21 on the rising edge of the WRITE data clock input 20. The latched WRITE data is presented to the parity generator 22; memory array 23 and output select multiplexer 24.

Parity generator 22 performs a parity check on the latched WRITE data and then outputs a parity bit via line 34, to memory array 23 and output select multiplexer 24. The parity bit 34 is used to detect errors in data stored in memory array 23.

The READ address is applied via the READ data bus 32 to READ address latch 26. On the rising edge of the READ address clock 31, the READ data is latched into READ address latch 26. The latched READ address information is then presented to the READ decoder 28 and to comparator 29. In the embodiment depicted, the READ decoder 28 decodes the latched READ address and applies the decoded output to the READ select circuitry of memory array 23 for selecting the memory cells to be read. The WRITE address information is applied via the WRITE address bus 33 to WRITE latch 25. On the rising edge of the WRITE address clock 31, the WRITE data is latched into WRITE latch 25. The latched WRITE address is presented to the WRITE decoder 27 and to comparator 29. In the preferred embodiment, the WRITE decoder 27 decodes the latched WRITE address and applies the decoded output to the WRITE select circuitry of memory array 23 for selecting the memory cells to be written to.

As indicated earlier, memory array 23 receives the latched WRITE data from the WRITE input latch 21, a parity bit from the parity generator 22, the decoded READ address from the READ decoder 28 and the decoded WRITE address from the WRITE decoder 27. The WRITE data and the parity bit are stored in the address location specified by the decoded WRITE address. Memory array 23 also outputs the data stored at the address locations specified by the decoded READ address to output select multiplexer 24. Memory array 23 can store WRITE data and output READ data either concurrently or at different times, even to the same address.

The latched READ and WRITE addresses applied to comparator 29 are used to set a memory bypass flag. If, and only if, the READ and WRITE addresses are equivalent, comparator 29 outputs a high signal to AND gate 30. If, and only if, the WRITE enable (WE) signal from external circuitry is present and applied to AND gate 30, AND gate 30 sets a memory bypass flag.

The output select multiplexer 24 receives the READ data output from memory array 23, an output enable (OE) signal from circuitry external to the present invention, latched WRITE data from input latch 21, a parity bit from the parity generator 22 and a memory bypass flag signal from AND gate 30.

With output enable (OE) present, output select multiplexer 24 is enabled. When the memory bypass flag signal is not present, output select multiplexer 24 outputs the READ data output from memory Array 23. However, when the memory bypass flag signal from AND gate 30 is present, instead of outputting the changing and possibly unstable data from the memory array 23, the output select multiplexer 24 outputs the latched WRITE data with parity from the input latch 21 and parity generator 22.

In accordance with provisions and statutes, there has been described and illustrated the preferred embodiment of the invention. However, those skilled in the art will appreciate that many changes may be made without departing from the spirit of the invention as set forth in the claims. For example, comparator 29 can be placed after decoding to compare READ and WRITE addresses. Additionally, certain features of the invention may be used to advantage without a corresponding use of other features of the invention. For example, input latches need not be present, and parity is not required. Therefore, the following claims should be interpreted so as to encompass all equivalents which might suggest themselves to one skilled in the art upon a reading of the present specification.

Claims

WHAT IS CLAIMED IS:

1. A READ-WHILE-WRITE RAM device, comprising: a memory array having a plurality of memory cells for the stroage of data:

READ address means coupled to said memory array for selecting a memory cell for connection to an output data bus; WRITE address means for selecting a memory cell for connection to an input data bus; comparator means for comparing the address data present on said READ address means and said WRITE address means and for generating bypass memory flag signal when said address data match; an output select multiplexer coupled to said input data bus and connected to said output data bus; said multiplexer responsive to the state of said bypass flag such that said multiplexer presents data on said input data bus to said output databus when said bypass flag indcates that the address data match.

2. The device according to claim 1 further comprising: parity means coupled to said input data bus for generating a parity bit from said WRITE data inputs and applying said parity bit as an additional WRITE data input bit to said memory means.

3. A READ-WHILE-WRITE RAM device, comprising: a READ address input bus having READ address data; a WRITE address input bus having WRITE address data; memory means with READ and WRITE address ports, a WRITE data input port having WRITE data inputs, and a READ data output bus having READ data outputs, said memory means operable for writing said WRITE data inputs into memory, storing data, and retrieving said READ data outputs and applying it to said READ data output bus, said operations capable of being performed either separately or concurrently; decoder means connected between said READ address input bus and said READ address port of said memory means for decoding said READ address data and applying the decoded READ address data to said READ address port; decoder means connected between said WRITE address input bus and said WRITE address port of said memory means for decoding said WRITE address data and applying the decoded WRITE address data to said WRITE address port; compare means having a memory bypass flag, for comparing said READ address data with said WRITE address data, and for setting said memory bypass flag when they are equivalent; and output means for selecting said READ data outputs when said memory bypass flag is clear, and for selecting said WRITE data inputs when said memory bypass flag is set.

4. The device according to claim 3 further comprising: a parity means connected to said WRITE data input port for generating a parity bit from said WRITE data inputs, and applying said parity bit as an additional WRITE data input bit on an additional line of said WRITE data input port.

5. A READ-WHILE-WRITE RAM device, comprising: a READ address input bus having READ address data; a WRITE address input bus having WRITE address data; a READ data output bus; a WRITE data input bus having WRITE data inputs; WRITE data latch means connected to said WRITE data input bus, said WRITE data latch means for latching said WRITE data inputs and outputting latched WRITE data on a latched WRITE data port; memory means having a latched WRITE data input port connected to said latched WRITE data port, READ data outputs connected to said READ data output bus, and both WRITE and READ address ports, said memory means operable for writing said latched WRITE data into memory at address locations specified by the data on said WRITE address port, storing data, and retrieving READ data outputs from the locations specified by the data on said READ address port, said operations capable of being performed either separately or concurrently; decoder means connected between said READ address input bus and said READ address port of said memory means for decoding said READ address data and applying the decoded READ address data onto said READ address port of said memory means; decoder means connected between said WRITE address input bus and said WRITE address port of said memory means for decoding said WRITE address data and applying the decoded WRITE address data onto said WRITE address port of said memory means; compare means having a memory bypass flag, for comparing said READ address data with said WRITE address data, and for setting said memory bypass flag when they are equivalent; and output means connected to said READ data output bus and said latched WRITE data port for selecting said READ data outputs when said memory bypass flag is clear, and for selecting said latched WRITE data when said memory bypass flag is set.

6. The device according to claim 5 further comprising: parity means connected to said latched WRITE data port for generating a parity bit from said latched WRITE data, and applying said parity bit as an additional bit of said latched WRITE data on an additional line of said latched WRITE data port.

7. A READ-WHILE-WRITE RAM device, comprising: a READ address input bus having READ address data; a WRITE address input bus having WRITE address data; a READ data output bus; a WRITE data input bus having WRITE data inputs; WRITE data latch means connected to said WRITE data input bus, said WRITE data latch means for latching said WRITE data inputs and outputting latched WRITE data on a latched WRITE data port; a READ address latch connected to said READ address input bus, said READ address latch for latching said READ address data and outputting latched READ address data on to a latched READ address bus; a WRITE address latch connected to said WRITE address input bus, said WRITE address latch for latching said WRITE address data and outputting latched WRITE address data on to a latched WRITE address bus; memory means having a latched WRITE data input port connected to said latched WRITE data port, READ data outputs connected to said READ data output bus, and both WRITE and READ address ports, said memory means operable for writing said latched WRITE data into memory at address locations specified by the data on said WRITE address port, storing data, and retrieving READ data outputs from the locations specified by the data on said READ address port, said operations capable of being performed either separately or concurrently; decoder means connected between said latched READ address bus and said READ address port of said memory means for decoding said latched READ address data and applying the decoded READ address data onto said READ address port of said memory means; decoder means connected between said latched WRITE address bus and said WRITE address port of said memory means for decoding said latched WRITE address data and applying the decoded WRITE address data onto said WRITE address port of said memory means; compare means having a memory bypass flag, for comparing said READ address data with said WRITE address data, and for setting said memory bypass flag when they are equivalent; and output means connected to said READ data output bus and latched WRITE data port for selecting said READ data outputs when said memory bypass flag is clear, and for selecting said latched WRITE data inputs when said memory bypass flag is set.

8. The device according to claim 7 further comprising: parity means connected to said latched WRITE data port for generating a parity bit from said latched WRITE data, and applying said parity bit as an additional bit of said latched WRITE data on an additional line of said latched WRITE data port.

9. The method of transferring data between a WRITE digital system and a READ digital system operating asynchronously, comprising: inputting WRITE digital data from said WRITE digital system into a RAM device having a WRITE address select means, said WRITE address select means being controlled by said WRITE digital system; outputting READ data to said READ digital system from said RAM device, said RAM device having a READ address select means independent of said WRITE address select means, said READ address select means being controlled by said READ digital system.

10. The method according to claim 9 further comprising bypassing said RAM device when said WRITE address and said READ address are equivalent.